Atmel AT90S2313 Manual
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Atmel AT90S2313 Manual

8-bit avr microcontroller with 2k bytes in-system programmable flash
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Features
®
•
Utilizes the AVR
RISC Architecture
•
AVR - High-performance and Low-power RISC Architecture
– 118 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 10 MIPS Throughput at 10 MHz
•
Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
– Full Duplex UART
•
• Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
•
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•
Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.8 mA
– Idle Mode: 0.8 mA
– Power Down Mode: <1 µA
•
I/O and Packages
– 15 Programmable I/O Lines
– 20-pin PDIP and SOIC
•
Operating Voltages
– 2.7 - 6.0V (AT90S2313-4)
– 4.0 - 6.0V (AT90S2313-10)
•
Speed Grades
– 0 - 4 MHz (AT90S2313-4)
– 0 - 10 MHz (AT90S2313-10)
Description
The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the
Pin Configuration
PDIP/SOIC
8-bit
Microcontroller
with 2K bytes
In-System
Programmable
Flash
AT90S2313
(continued)
Rev. 0839E–04/99
1

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Summary of Contents for Atmel AT90S2313

  • Page 1 – 0 - 4 MHz (AT90S2313-4) – 0 - 10 MHz (AT90S2313-10) Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the (continued) Pin Configuration PDIP/SOIC Rev.
  • Page 2 AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consump- tion versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.

  • Page 3: Pin Descriptions

    By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

  • Page 4: Crystal Oscillator

    Figure 2. Oscillator Connections MAX 1 HC BUFFER XTAL2 XTAL1 Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure. Figure 3. External Clock Drive Configuration AT90S2313...

  • Page 5: Architectural Overview

    The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S2313 AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
  • Page 6 The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. Figure 5. Memory Maps AT90S2313...

  • Page 7: General Purpose Register File

    AT90S2313 A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory.

  • Page 8: Alu - Arithmetic Logic Unit

    EEPROM Data Memory The AT90S2313 contains 128 bytes of EEPROM data memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 38 specifying the EEPROM address register, the EEPROM data register, and the EEPROM control register.

  • Page 9: Sram Data Memory

    When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y and Z are used and decremented and incremented. The 32 general purpose working registers, 64 I/O registers and the 128 bytes of data SRAM in the AT90S2313 are all directly accessible through all these addressing modes.

  • Page 10: Program And Data Addressing Modes

    Program and Data Addressing Modes The AT90S2313 AVR RISC Microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory. This section describes the different addressing modes supported by the AVR architec- ture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.
  • Page 11 AT90S2313 I/O Direct Figure 11. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct Figure 12. Direct Data Addressing A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source...
  • Page 12 Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction word. Data Indirect Figure 14. Data Indirect Addressing Operand address is the contents of the X, Y or the Z-register. AT90S2313...
  • Page 13 AT90S2313 Data Indirect With Pre-Decrement Figure 15. Data Indirect Addressing With Pre-Decrement The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y or the Z-register. Data Indirect With Post-Increment Figure 16.
  • Page 14 (LSB = 0) or high byte if set (LSB = 1). Indirect Program Addressing, IJMP and ICALL Figure 18. Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the content of the Z-register). AT90S2313...

  • Page 15: Memory Access And Instruction Execution Timing

    AT90S2313 Relative Program Addressing, RJMP and RCALL Figure 19. Relative Program Memory Addressing Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. Memory Access and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access.
  • Page 16 ALU Operation Execute Result Write Back The internal data SRAM access is performed in two System Clock cycles as described in Figure 22. Figure 22. On-Chip Data SRAM Access Cycles System Clock Ø Address Prev. Address Address Data Data AT90S2313...
  • Page 17 AT90S2313 I/O Memory The I/O space definition of the AT90S2313 is shown in the following Table 1: Table 1. AT90S2313 I/O Space Address Hex Name Function $3F ($5F) SREG Status Register $3D ($5D) Stack Pointer Low $3B ($5B) GIMSK General Interrupt MaSK register...
  • Page 18 All AT90S2313 I/O and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instruc- tions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions.

  • Page 19: Reset And Interrupt Handling

    AT90S2313 Stack Pointer - SP An 8-bit register at I/O address $3D ($5D) forms the stack pointer of the AT90S2313. 8 bits are used to address the 128 bytes of SRAM in locations $60 - $DF. $3D ($5D) Read/Write Initial value The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located.
  • Page 20 … Reset Sources The AT90S2313 has three sources of reset: • Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.
  • Page 21 AT90S2313 Table 3. Reset Characteristics (V = 5.0V) Symbol Parameter Units Power-On Reset Threshold Voltage (rising) Power-On Reset Threshold Voltage (falling) 0.85V RESET Pin Threshold Voltage Reset Delay Time-Out Period TOUT FSTRT Unprogrammed Reset Delay Time-Out Period TOUT FSTRT Programmed Notes: 1.
  • Page 22 Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - V on its positive edge, the delay timer starts the MCU after the Time-out period t TOUT expired. Figure 26. External Reset During Operation AT90S2313...
  • Page 23 Figure 27. Watchdog Reset During Operation Interrupt Handling The AT90S2313 has two 8-bit Interrupt Mask control registers; GIMSK - General Interrupt Mask register and TIMSK - Timer/Counter Interrupt Mask register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user soft- ware can set (one) the I-bit to enable interrupts.
  • Page 24 INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits These bits are reserved bits in the AT90S2313 and always read as zero. General Interrupt FLAG Register - GIFR $3A ($5A) INTF1...
  • Page 25 PD6(ICP), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. • Bit 2 - Res: Reserved bit This bit is a reserved bit in the AT90S2313 and always reads as zero. • Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled.
  • Page 26 Initial value • Bits 7, 6 - Res: Reserved bits These bits are reserved bits in the AT90S2313 and always read as zero. • Bit 5 - SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

  • Page 27: Sleep Modes

    TOUT Timer/Counters The AT90S2313 provides two general purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescaling timer. Both Timer/Counters can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting.

  • Page 28: Timer/Counter Prescaler

    The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni- ties. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions. AT90S2313...
  • Page 29 Initial value • Bits 7..3 - Res: Reserved bits These bits are reserved bits in the AT90S2313 and always read zero. • Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0 The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0.
  • Page 30 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation. 16-bit Timer/Counter1 Figure 30 shows the block diagram for Timer/Counter1. Figure 30. Timer/Counter1 Block Diagram AT90S2313...
  • Page 31 AT90S2313 The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter1 Control Register - TCCR1B. The different status flags (overflow, compare match and capture event) and control signals are found in the Timer/Counter Interrupt Flag Register - TIFR. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register - TIMSK.
  • Page 32 In PWM mode, these bits have a different function. Refer to Table 12 for a detailed description. • Bits 5..2 - Res: Reserved bits These bits are reserved bits in the AT90S2313 and always read zero. • Bits 1,0 - PWM11, PWM10: Pulse Width Modulator Select Bits These bits select PWM operation of Timer/Counter1 as specified in Table 9.
  • Page 33 AT90S2313 • Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the com- pare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer.
  • Page 34 The TEMP register is also used when accessing TCNT1 and OCR1A. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. AT90S2313...
  • Page 35 AT90S2313 Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1 - OCR1A, form a 8, 9 or 10-bit, free- running, glitch-free and phase correct PWM with output on the PB3(OC1) pin. Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table 11), where it turns and counts down again to zero before the cycle is repeated.

  • Page 36: Watchdog Timer

    Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S2313 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 23.

  • Page 37: Eeprom Read/Write Access

    AT90S2313 • Bit 3 - WDE: Watchdog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1.
  • Page 38 Initial value • Bit 7 - Res: Reserved bit This bit is a reserved bit in the AT90S2313 and will always read as zero. • Bit 6..0 - EEAR6..0: EEPROM Address The EEPROM Address Register - EEAR6..0 - specifies the EEPROM address in the 128 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127.

  • Page 39: Prevent Eeprom Corruption

    CPU, and will not be subject to corruption. UART The AT90S2313 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud rate generator that can generate a large number of baud rates (bps) •...
  • Page 40 The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD. AT90S2313...

  • Page 41: Data Reception

    AT90S2313 Data Reception Figure 35 shows a block diagram of the UART Receiver Figure 35. UART Receiver The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated.

  • Page 42: Uart Control

    When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit. AT90S2313...
  • Page 43 The OR bit is cleared (zero) when data is received and transferred to UDR. • Bits 2..0 - Res: Reserved bits These bits are reserved bits in the AT90S2313 and will always read as zero. UART Control Register - UCR $0A ($2A)
  • Page 44 28800 UBRR= 0.0 UBRR= 2.1 UBRR= 0.0 UBRR= 38400 UBRR= 0.0 UBRR= 0.2 UBRR= 0.0 UBRR= 57600 UBRR= 0.0 UBRR= 3.7 UBRR= 0.0 UBRR= 76800 UBRR= 0.0 UBRR= 7.5 UBRR= 6.7 UBRR= 115200 UBRR= 0.0 UBRR= 7.8 UBRR= 0.0 UBRR= AT90S2313...

  • Page 45: Analog Comparator

    Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 - Res: Reserved bit This bit is a reserved bit in the AT90S2313 and will always read as zero. • Bit 5 - ACO: Analog Comparator Output ACO is directly connected to the comparator output.
  • Page 46 All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20mA and thus drive LED dis- plays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. AT90S2313...
  • Page 47 AT90S2313 The Port B pins with alternate functions are shown in the following Table 17: Table 17. Port B Pins Alternate Functions Port Pin Alternate Functions AIN0 (Analog comparator positive input) AIN1 (Analog comparator negative input) OC1 (Timer/Counter1 Output compare match output)
  • Page 48 AIN0, Analog Comparator Positive Input. When configured as an input (DDB0 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB0 is cleared (zero)), this pin also serves as the positive input of the on-chip analog comparator. AT90S2313...
  • Page 49 AT90S2313 Port B Schematics Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 38. Port B Schematic Diagram (pins PB0 and PB1) Figure 39. Port B Schematic Diagram Pin PB3 PULL-...
  • Page 50 Figure 40. Port B Schematic Diagram, Pins PB2 and PB4 Figure 41. Port B Schematic Diagram Pin PB5 AT90S2313...
  • Page 51 AT90S2313 Figure 42. Port B Schematic Diagram, Pin PB6 Figure 43. Port B Schematic Diagram, Pin PB7...
  • Page 52 The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. AT90S2313...
  • Page 53 AT90S2313 Port D as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is con- figured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PORTDn is set (one) when configured as an input pin the MOS pull up resistor is activated.
  • Page 54 UART RECEIVE DATA UART RECEIVE ENABLE RXEN: Figure 45. Port D Schematic Diagram, Pin PD1 PULL- RESET DDD1 RESET PORTD1 WRITE PORTD WRITE DDRD TXEN READ PORTD LATCH READ PORTD PIN READ DDRD UART TRANSMIT DATA TXD: TXEN: UART TRANSMIT ENABLE AT90S2313...
  • Page 55 AT90S2313 Figure 46. Port D Schematic Diagram (Pins PD2 and PD3) Figure 47. Port D Schematic Diagram (Pins PD4 and PD5) PULL- RESET DDDn RESET PORTDn WRITE PORTD TIMERm CLOCK WRITE DDRD SENSE CONTROL SOURCE MUX READ PORTD LATCH READ PORTD PIN...

  • Page 56: Memory Programming

    Program and Data Memory Lock Bits The AT90S2313 MCU provides two Lock bits which can be left unprogrammed (‘1’) or can be programmed (‘0’) to obtain the additional features listed in Table 21. The Lock bits can only be erased with the Chip Erase operation.

  • Page 57: Signature Bytes

    The Fuse bits are not accessible in Serial Programming Mode. The status of the Fuses are not affected by Chip Erase. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space.
  • Page 58 Table 24. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS) Load Data (High or Low data byte for Flash determined by BS) Load Command No Action, Idle AT90S2313...
  • Page 59 AT90S2313 Table 25. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes 0000 0100...
  • Page 60 • Address high byte needs only be loaded before programming a new 256 word page in the Flash. • Skip writing the data value $FF, that is the contents of the entire Flash and EEPROM after a Chip Erase. These considerations also applies to EEPROM programming, and Flash, EEPROM and Signature bytes reading. AT90S2313...
  • Page 61 AT90S2313 Figure 50. Programming the Flash DATA ADDR. HIGH ADDR. LOW DATA LOW XTAL1 RDY/BSY RESET Figure 51. Programming the Flash (continued) DATA DATA HIGH XTAL1 RDY/BSY RESET +12V...
  • Page 62 Bit 7-6,4-1 = ‘1’. These bits are reserved and should be left unprogrammed (‘1’). 3. Give WR a wide negative pulse to execute the programming, is found in Table 26. Programming WLWH_PFB WLWH_PFB the Fuse bits does not generate any activity on the RDY/BSY pin. AT90S2313...
  • Page 63 AT90S2313 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to Programming the Flash for details on Command and Data loading): 1. A: Load Command ‘0010 0000’. 2. D: Load Data Low Byte. Bit n = ‘0’ programs the Lock bit.

  • Page 64: Parallel Programming Characteristics

    WR Pulse Width Low for Programming the Fuse Bits WLWH_PFB Notes: 1. Use t for Chip Erase and for Programming the Fuse Bits. WLWH_CE WLWH_PFB 2. If t is held longer than , no RDY/BSY pulse will be seen. WLWH WLRH AT90S2313...

  • Page 65: Serial Downloading

    When writing serial data to the AT90S2313, data is clocked on the rising edge of SCK. When reading data from the AT90S2313, data is clocked on the falling edge of SCK. See Figure 54, Figure 55 and Table 29 for timing details.
  • Page 66 $FF, can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device. Table 27. Read back value during EEPROM polling Part AT90S2313 Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $7F.
  • Page 67 AT90S2313 Table 28. Serial Programming Instruction Set Instruction Instruction Format Operation Byte 1 Byte 2 Byte 3 Byte4 Enable Serial Programming while 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Programming Enable RESET is low. Chip Erase Flash and EEPROM...

  • Page 68: Serial Programming Characteristics

    3.2V 3.6V 4.0V 5.0V 18 ms 14 ms 12 ms 8 ms WD_ERASE Table 31. Minimum wait delay after writing a Flash or EEPROM location Symbol 3.2V 3.6V 4.0V 5.0V 9 ms 7 ms 6 ms 4 ms WD_PROG AT90S2313...

  • Page 69: Electrical Characteristics

    AT90S2313 Electrical Characteristics Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C...
  • Page 70 3] The sum of all I If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum V for Power Down is 2V. AT90S2313...

  • Page 71: External Clock Drive Waveforms

    AT90S2313 External Clock Drive Waveforms Figure 56. External Clock VIH1 VIL1 External Clock Drive = 2.7V to 6.0V = 4.0V to 6.0V Symbol Parameter Units Oscillator Frequency CLCL Clock Period CLCL High Time CHCX Low Time CLCX µs Rise Time CLCH µs...
  • Page 72 = 4V = 3.6V = 3.3V = 3.0V = 2.7V " & " Frequency (MHz) Figure 58. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz T = 25 ˚ T = 85 ˚ AT90S2313...
  • Page 73 AT90S2313 Figure 59. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY T = 25˚C = 6V = 5.5V = 5V = 4.5V = 4V = 3.6V = 3.3V = 3.0V = 2.7V Frequency (MHz) Figure 60. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs.
  • Page 74 T = 85 ˚ T = 70 ˚ T = 45 ˚ T = 25 ˚ Figure 62. Power Down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED T = 25 ˚ T = 85 ˚ AT90S2313...
  • Page 75 AT90S2313 Figure 63. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V T = 25 ˚ T = 85 ˚ Analog comparator offset voltage is measured as absolute offset Figure 64. Analog Comparaor Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs.
  • Page 76 COMMON MODE VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Common Mode Voltage (V) Figure 66. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT V = 6V T = 25 ˚ V (V) AT90S2313...
  • Page 77 AT90S2313 Figure 67. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 T = 25 ˚ 1400 T = 85 ˚ 1200 1000 V (V) Sink and source capabilities of I/O ports are measured on one pin at a time.
  • Page 78 PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 70. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ AT90S2313...
  • Page 79 AT90S2313 Figure 71. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 5V T = 25 ˚ T = 85 ˚ Figure 72. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE V = 2.7V...
  • Page 80 Figure 73. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE V = 2.7V T = 25 ˚ T = 85 ˚ Figure 74. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V T = 25 ˚ AT90S2313...
  • Page 81 AT90S2313 Figure 75. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V T = 25 ˚ 0.18 0.16 0.14 0.12 0.08 0.06 0.04 0.02...

  • Page 82: Register Summary

    2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. AT90S2313...

  • Page 83: Instruction Set Summary

    AT90S2313 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry two Registers Z,C,N,V,H Rdh:Rdl ←...
  • Page 84 ← Clear T in SREG ← Set Half Carry Flag in SREG ← Clear Half Carry Flag in SREG No Operation None SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/timer) None AT90S2313...

  • Page 85: Ordering Information

    AT90S2313 Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range 2.7 - 6.0V AT90S2313-4PC 20P3 Commercial AT90S2313-4SC (0°C to 70°C) AT90S2313-4PI 20P3 Industrial AT90S2313-4SI (-40°C to 85°C) 4.0 - 6.0V AT90S2313-10PC 20P3 Commercial AT90S2313-10SC (0°C to 70°C) AT90S2313-10PI...

  • Page 86: Packaging Information

    .050 (1.27) BSC SEATING PLANE 0.513 (13.0) .015(.381) MIN .150(3.81) 0.105 (2.67) 0.497 (12.6) .022(.559) 0.092 (2.34) .115(2.92) .014(.356) .070(1.78) .110(2.79) .045(1.13) .090(2.29) 0.012 (0.305) 0.003 (0.076) .325(8.26) .300(7.62) .014(.356) 0.013 (0.330) .008(.203) 0.009 (0.229) .430(10.92) MAX 0.035 (0.889) 0.015 (0.381) AT90S2313...
  • Page 87 No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems.

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