Pinout For Spi - Segger J-Link User Manual

424

16.1.4 Pinout for SPI

*On later J-Link products like the J-link ULTRA,
these pins are reserved for firmware extension pur-
poses. They can be left open or connected to GND
in normal debug environment.
The following table lists the pinout for the SPI inter-
face on J-Link.
PIN SIGNAL
1 VTref
Not con-
2
nected
Not con-
3
nected
5 DI
7 nCS
9 CLK
Not con-
11
nected
13 DO
15 nRESET
Not con-
17
nected
5V-Sup-
19
ply
Table 16.6: J-Link / J-Trace pinout
Pins 4, 6, 8, 10, 12 are GND pins connected to GND in J-Link. They should also be
connected to GND in the target system.
J-Link / J-Trace (UM08001)
CHAPTER 16
TYPE
This is the target reference voltage. It is used to check if
the target has power, to create the logic-level reference for
Input the input comparators and to control the output logic levels
to the target. It is normally fed from Vdd of the target board
and must not have a series resistor.
NC Leave open on target side
NC Leave open on target side
Data-input of target SPI. Output of J-Link, used to transmit
Output
data to the target SPI.
Output Chip-select of target SPI (active LOW).
Output SPI clock signal.
NC Leave open on target side
Data-out of target SPI. Input of J-Link, used to receive data
Input
from the target SPI.
Target CPU reset signal. Typically connected to the RESET
I/O pin of the target CPU, which is typically called "nRST",
"nRESET" or "RESET". This signal is an active low signal.
NC Leave open on target side
This pin can be used to supply power to the target hard-
ware. Older J-Links may not be able to supply power on this
Output pin. For more information about how to enable/disable the
power supply, please refer to Target power supply on
page 420.
Target interfaces and adapters
VTref
NC
DI
nCS
CLK
NC
DO
nRESET
NC
5V-Supply
Description
© 2004-2017 SEGGER Microcontroller GmbH & Co. KG
1 2 NC
3 4 GND
5 6 GND
7 8 GND
9 10
GND
11 12 GND
13 14 GND*
15 16
GND*
17 18 GND*
19 20 GND*