Sdio Interface Routing Guidelines - Advantech Qseven SOM-3567 Manual

2.8.2 SDIO Interface Routing Guidelines

Figure 12: Topology for SDIO
Table 14: SDIO Trace Length Guidelines
Parameter
Signal Group
Single End
DATA to CLK Maximum Pin
to Pin Length Mismatch
Main Route segment for
CMD/Data/CD#
Main Route segment for CLK)
Spacing to Other Signal
Group
LA
LB
Max length of LA+LB
Length matching
Reference Plane
Notes:
Main Route Guidelines
SDIO
50Ω ±10%
500 mils
Minimum Trace Spacing Between Other SD
Card and
Interface Signals
5 mils
Minimum Trace Spacing Between Other SD
Card and
Interface Signals
15mils
Min. 15mils
Please see the SOM-3567 Layout Checklist
Carrier Board Length
5"
Data to Clock must be matched within 500mils
GND referencing preferred.
Min 20-mil trace edge-to-major plane edge
spacing.
５３
Notes