Forwarding Of Pcie To Pci-X; Pcie Memory Write Request; Pcie Non-Posted Requests - IDT TSI384 User Manual

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6.6

Forwarding of PCIe to PCI-X

The Tsi384 forwards posted, non-posted, and upstream read completions to PCI-X devices, and stores
the non-posted TLPs' state information to return the completion TLPs to the PCIe Interface.
6.6.1

PCIe Memory Write Request

The Tsi384 forwards the PCIe Memory Write Requests to the PCI-X Interface using either Memory
Write (MW) or Memory Write Block (MWB) command. It translates the PCIe MW into a PCI-X
transaction using the MWB command if the PCIe memory write meets the MWI command rules
specified in the PCI-X Addendum to PCI Local Bus Specification (Revision 2.0), and the No snoop
attribute field is set to 0 in the
remaining part of the MWB transaction if the transaction was disconnected such that the remaining
request does not meet the MWI command rules. The Tsi384 does not support relaxed ordering among
the received requests, and forwards all the requests in the order they were received even if the relaxed
ordering bit is set for some of the requests. Relaxed ordering and No snoop attributes are forwarded
unchanged.
6.6.2

PCIe Non-posted Requests

The Tsi384 translates the PCIe Memory Read Requests into the PCI-X transactions that use one of the
PCI-X memory read commands, either Memory Read DWORD or Memory Read Block, based on
requested byte enables, prefetchable and non-prefetchable memory windows. PCIe Read Request
command translation is completed as follows:
• Memory Read DWORD if the PCIe Read request falls into non-prefetchable address range and
requested byte enables are non-contiguous.
• Memory Read Block if the PCIe Read request falls into the prefetchable range or requested byte
enables are contiguous.
In order to improve bus bandwidth utilization, the Tsi384 keeps attempting the other outstanding
requests if the current request is either retried or disconnected. The Tsi384 decomposes the requests if
the requested data length is greater than 128 bytes and returns the completions in 128-byte boundary
fragments.
The Tsi384 uses PCI-X byte enable fields such that the byte enable information is preserved and no
additional bytes are requested for the transactions that fall into the non-prefetchable address range (for
example, transactions that use configuration, I/O, or memory read DWORD command.
The Tsi384 does not use any timeout for the requests it received split response, and waits indefinitely
for the split completion from the PCI-X completer to return the completion TLP onto the
PCIe Interface. However, the Tsi384 discards a request and returns completion with an Unsupported
Request (UR) completion status if that request is retried on the PCI-X Interface for more than the
programmed number of times (see
Tsi384 User Manual
May 5, 2014
"PCI Control and Status Register". An MW command is used for the
"Secondary Retry Count Register").
Integrated Device Technology
6. Bridging
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