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Zynq UltraScale+ User Manual

Rfsoc rf data converter evaluation tool (zcu111)
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Zynq UltraScale+ RFSoC
RF Data Converter
Evaluation Tool (ZCU111)
User Guide
UG1287 (v2018.2) October 1, 2018

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Summary of Contents for Zynq UltraScale+

  • Page 1 Zynq UltraScale+ RFSoC RF Data Converter Evaluation Tool (ZCU111) User Guide UG1287 (v2018.2) October 1, 2018...

  • Page 2: Revision History

    Revision History The following table shows the revision history for this document. Section Revision Summary 10/01/2018 Version 2018.2 DAC Data Flow Added information about feeding data to the RF-DAC. Streaming MUX Added channel control selection information. GPIO Selection Replaced Table 3-2.

  • Page 3: Table Of Contents

    Zynq UltraScale+ RFSoC Overview ........
  • Page 4 Multi-Tile Sync ..............54 Chapter 8: Zynq UltraScale+ RFSoC Data Converter Bare-metal/Linux Driver Chapter 9: System Considerations Boot Process.

  • Page 5: Chapter 1: Introduction

    RFSoCs. The RFSoC design demonstrates the capabilities and performance of the RF data converter (RFDC—RF-ADC and RF-DAC) available in the RFSoC devices. The evaluation tool serves as a platform for you to evaluate the Zynq UltraScale+ RFSoC features and helps accelerate the product design cycle.
  • Page 6 This user guide describes the architecture of the design and provides a functional description of its components. It is organized as follows: Chapter 1, Introduction (this chapter) provides a high-level overview of the Zynq UltraScale+ RFSoC device architecture, the design architecture, and a summary of key features.

  • Page 7: Zynq Ultrascale+ Rfsoc Overview

    Chapter 1: Introduction Zynq UltraScale+ RFSoC Overview The Zynq UltraScale+ RFSoC family integrates the key subsystems required to implement a complete software-defined radio including direct RF sampling data converters, enabling CPRI and Gigabit Ethernet-to-RF on a single, highly programmable SoC.
  • Page 8 For device specifications and additional information, see: • Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) [Ref 1] • Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) [Ref 2] • Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref...

  • Page 9: Reference Design Overview

    Chapter 1: Introduction Reference Design Overview The evaluation tool targets the Zynq UltraScale+ RFSoC ZU28DR-FFVG1517 running on the ZCU111 evaluation board and provides a platform to evaluate the RFSoC features. The system level block diagram of the evaluation tool design is shown in Figure 1-3.
  • Page 10 [Ref Components • Evaluation platform ZCU111 evaluation board ° Daughter card (HW-FMC-XM500) ° Cables and filters (see the Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit Quick ° Start Guide (XTP490) [Ref 5] • Xilinx tools Vivado® Design Suite 2018.2 [Ref 6] °...
  • Page 11 Chapter 1: Introduction AXI interconnect ° AXI Streaming IPs ° • Auxiliary peripherals ° ° PS-GPIO ° Gigabit Ethernet ° UART ° JTAG ° Software Components • Operating systems APU: SMP Linux ° • Linux frameworks Ethernet ° Clock ° Contiguous memory allocator (CMA) °...
  • Page 12 Chapter 1: Introduction • Board-specific components Voltage controller ° RFSoC Data Converter Evaluation Tool User Guide Send Feedback UG1287 (v2018.2) October 1, 2018 www.xilinx.com...

  • Page 13: Chapter 2: Package Details

    Chapter 2 Package Details The evaluation tool ZIP file package rdf0476-zcu111-rf-dc-eval-tool-2018-2.zip contains the following components grouped by application processor unit (APU) or programmable logic (PL). petalinux_bsp: PetaLinux board support package (BSP) is included to build a pre-configured SMP Linux image for the APU. The BSP includes the following components: •...

  • Page 14: Chapter 3: Hardware Design

    Chapter 3 Hardware Design Hardware Overview The Vivado IP integrator flow is used to create the hardware design which is partitioned between the processing system (PS), RF Data Converter (RFDC), and programmable logic (PL). Figure 3-1 shows the hardware block diagram. X-Ref Target - Figure 3-1 Processing System Controller...

  • Page 15: Dac Data Flow

    Chapter 3: Hardware Design The design is configured to operate in 8x8 mode (8-channel RF-DAC and 8-channel RF-ADC). The RFDC datapath consists of AXI DMA and Stream Pipe IPs for high performance data transfers between PS/PL DDR memories and RFDC IP. The RFDC datapath is based on AMBA AXI4-Stream protocol and the control path is based on the AXI4-Lite interface.
  • Page 16 Chapter 3: Hardware Design X-Ref Target - Figure 3-2 Memory DAC0 Loopback 0 Memory DAC1 Loopback 1 Memory DAC2 Loopback 2 Memory DAC3 Loopback 3 PL DDR + MIG SG DMA Stream Mux Memory DAC4 Loopback 4 Memory DAC5 Loopback 5 Memory DAC6 Loopback 6...
  • Page 17 Chapter 3: Hardware Design Streaming MUX The streaming MUX connects the incoming pattern to the selected channel(s) based on a GUI command. Figure 3-3 shows the stream data interface with AXIS FIFOs. X-Ref Target - Figure 3-3 Memory Loopback Memory Loopback TDATA ------------ Memory Loopback...
  • Page 18 Chapter 3: Hardware Design X-Ref Target - Figure 3-4 Memory Loopback Memory Loopback ------------ Tvalid 0..7 Memory Channel Select 0..7 Loopback Channel Arbiter X21236-092118 Figure 3-4: Channel Selection Control Signals Figure 3-5 shows the TREADY signal generation. Only a single TREADY signal is selected based on the Channel Select signal;...
  • Page 19 Chapter 3: Hardware Design Memory Loopback Details Figure 3-6 illustrates the working of memory loopback (BRAM mode) in one DAC path. X-Ref Target - Figure 3-6 AXIS FIFO To DAC Interface Control AXIS AXI Stream (S00) AXIS FIFO Switch Broadcaster Loopback (S01) AXIS...
  • Page 20 Chapter 3: Hardware Design DAC Control Switch Control switch is control logic before the streaming interface is connected to the DAC. This logic provides tight control over the streaming path and helps synchronize all the stream interfaces at any given time. Figure 3-7 shows the control switch.

  • Page 21: Adc Data Flow

    Chapter 3: Hardware Design ADC Data Flow Figure 3-8 shows the datapath implementation for 8-channel RF-ADC (RF-ADC0 and RF-ADC7). The default configuration of Real to IQ is enabled in the design so that all possible streaming interfaces from RF-ADC are accessible. X-Ref Target - Figure 3-8 Control AXIS FIFO...
  • Page 22 Chapter 3: Hardware Design ADC Control Switch The control switch is the final control logic before the streaming interface is connected to the ADC. This logic controls the streaming path and also helps to synchronize all the stream interfaces when required through software control. Figure 3-9 shows the control switch.
  • Page 23 Chapter 3: Hardware Design X-Ref Target - Figure 3-10 Data Width Converter I (Real) Stream AXIS Broadcaster AXI4-Stream AXIS Combiner Q Stream IQ Select X21242-091318 Figure 3-10: IQ Datapath Channel Select MUX The Channel MUX implementation is an 8:1 streaming selection logic as shown in Figure 3-11.

  • Page 24: Stream Pipes Control And Status Registers

    Chapter 3: Hardware Design Stream Pipes Control and Status Registers The register sets in the design are available under the user_axilite_control block. The block has an AXI4-Lite interface through which the registers can be accessed. In the current implementation, the base address of the user_axilite_control is 0xB005_0000. Table 3-1 lists the registers that are available currently.
  • Page 25 Chapter 3: Hardware Design Table 3-2: Control Signals (Cont’d) Common DAC0 Loopback select Reserved Reserved DAC1 Memory Loopback Reset ADC0203 FIFO Reset DAC Multi Tile Select DAC1 Loopback select ADC0203_IQ_Merge_sel Reserved DAC1 Channel Control ADC0203 Channel Control Reserved DAC2 Loopback select Reserved Reserved 79:71...
  • Page 26 Chapter 4 Clocking The evaluation tool design has 256 MHz, 409.625 MHz, 300 MHz, and 512 MHz clock domains. The RF-DAC output is a maximum of 409.625 MHz and RF-ADC 256 MHz. The 256 MHz output from ADC is supplied to the clocking wizard for generating 512 MHz for driving the PL ADC path whereas 409.625 MHz drives the PL DAC path directly.

  • Page 27: Chapter 4: Clocking

    In each Zynq UltraScale+ RFSoC, each RF-ADC or RF-DAC tile has its own clock input. Additionally, there is a dedicated input PL SYSREF pin pair per package. The PL SYSREF clock is used for multi-tile and multi-chip synchronization. For multi-tile designs, the PL SYSREF connects into a master tile and the signal is distributed within the master tile and all the other tiles in the design.

  • Page 28: Clock Switching

    Figure 4-2. This output of the second stage synchronizer is connected to user_sysref ports of RFDC IP. Refer to Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) for more details on multi-tile synchronization [Ref Clock Switching The design supports multi-tile synchronization (MTS) mode and non-MTS mode.
  • Page 29 Chapter 4: Clocking this signal is overridden with a global start/stop signal which is generated using Channel Select of the Master DAC block, i.e., tile 0 block 0. This signal selection is controlled using multi-tile mode select. X-Ref Target - Figure 4-4 Multi-Tile Control PL CLK Tile0 _ADC_Clock out...
  • Page 30 Chapter 4: Clocking X-Ref Target - Figure 4-5 Channel 0 Control ADC 0 Control Multi-Tile Control N-stage ADC 1 Control Channel 1 Control Sync logic PL CLK ADC 0 Tile0_clk PL CLK Tile0 _ADC_Clock out ADC 0 Analog Clock (PCB) Tile 0 Channel 2 Control ADC 2 Control...
  • Page 31 Chapter 4: Clocking Table 4-1 lists the clocks used for the RF-ADC control path and datapath. Table 4-1: Clock Domains in RF-ADC Control and Datapath ADC Stream Clock Domain ADC Clock Domain Logic Block Clock Domain (300 MHz) (256 MHz) (512 MHz) ADC (usp_rf_data_converter) Channel select multiplexer...
  • Page 32 Chapter 4: Clocking X-Ref Target - Figure 4-7 Loopback AXIS FIFO Clock Example: DAC 0 Component Converter 64 KS Fs = 6.4 GHz Interpolation = x1 SYREF = 8 MHz Loopback AXIS FIFO Clock DAC 1 PL SYSREF = 8 MHz 64 KS Converter Component...
  • Page 33 Chapter 4: Clocking X-Ref Target - Figure 4-9 Tile0 _clk Tile1 _clk PS Clock PS Clock DAC 4 CONTROL Synchronizer Synchronizer Channel 0 Control Channel 4 Control DAC 0 CONTROL Multi-Tile Control Multi-Tile Control DAC 5 CONTROL Synchronizer Synchronizer Channel 1 Control Channel 5 Control DAC 1 CONTROL Multi-Tile Control...

  • Page 34: Resets

    Chapter 4: Clocking Resets The following reset sources are in the design: • pl_resetn0 (from PS to PL) This active Low reset is asserted by the PS during initialization. • ddr4_sync_rst (or c0_ddr4_ui_clk_sync_rst from the PL DDR memory interface group (MIG)) This active High reset is asserted by the PL DDR MIG.
  • Page 35 Chapter 4: Clocking Table 4-3: Reset Distribution in the Evaluation Tool Design (Cont’d) User-controlled Logic Block pl_resetn0 ddr4_sync_rst Reset Block DAC 4 block- output AXIS data FIFOs x (dac reset_4_n) DAC 5 block- output AXIS data FIFOs x (dac reset_5_n) DAC 6 block- output AXIS data FIFOs x (dac reset_6_n) DAC 7 block- output AXIS data FIFOs...

  • Page 36: Chapter 5: Evaluation Tool System Configuration Using The Gui

    Chapter 5 Evaluation Tool System Configuration using the GUI The evaluation tool GUI is PC-based software that allows you to configure the operating modes of the ADCs and DACs. The GUI also generates test patterns which can be downloaded for DAC testing and manages the upload of data from the ADCs for analysis in the GUI.

  • Page 37: External Component Configuration

    Chapter 5: Evaluation Tool System Configuration using the GUI External Component Configuration In the overview tab, when clicking on Clock Settings, the external PLL can be configured with a set of predefined frequencies as shown in Figure 5-1. X-Ref Target - Figure 5-1 X21283-090918 Figure 5-1: Overview of External PLLs When clicking on Power Settings, the DAC power mode can be changed between 20 mA...

  • Page 38: Adc Configuration

    Chapter 5: Evaluation Tool System Configuration using the GUI When selecting a tile, the tile status is displayed on the left side as shown in Figure 5-2, including the power up state machine’s current state. Controls for reset and shutdown/startup are provided. A reset reconfigures the tile to its original bitstream state. X-Ref Target - Figure 5-2 X21284-090918 Figure 5-2: Overview of Tile Status...
  • Page 39 Chapter 5: Evaluation Tool System Configuration using the GUI Converter IP GUI. A notable difference is the multi-band and complex/real settings available in the crossbar setting shown in Figure 5-4. X-Ref Target - Figure 5-3 X21280-090918 Figure 5-3: ADC Configuration RFSoC Data Converter Evaluation Tool User Guide Send Feedback UG1287 (v2018.2) October 1, 2018...
  • Page 40 Chapter 5: Evaluation Tool System Configuration using the GUI X-Ref Target - Figure 5-4 X21281-092118 Figure 5-4: ADC Crossbars RFSoC Data Converter Evaluation Tool User Guide Send Feedback UG1287 (v2018.2) October 1, 2018 www.xilinx.com...

  • Page 41: Adc Clock Configuration

    Chapter 5: Evaluation Tool System Configuration using the GUI ADC Clock Configuration The GUI supports: • Selection of external or internal (PLL) sample clock options • On-chip PLL configuration for internal sample clock generation (see Figure 5-5). • The configuration of the RF PLLs on the evaluation board for external clocking RFPLL (LMK) is also used to set up the reference clock for the on-chip PLLs.

  • Page 42: Digital Down Converter Configurations

    Chapter 5: Evaluation Tool System Configuration using the GUI Digital Down Converter Configurations The GUI supports: • Setting up complex mixer functionality and NCO frequency • Setting the decimation rate on the decimation filters • Selecting and configuring the decimation filter in the PL, if desired •...

  • Page 43: Digital Up Converter Configurations

    Chapter 5: Evaluation Tool System Configuration using the GUI Digital Up Converter Configurations The GUI supports: • Setting the complex mixer functionality and NCO frequency • Setting the interpolation rate on the filters • Selecting and configuring the interpolation filters in the PL, if desired •...
  • Page 44 Chapter 6 Software Architecture This chapter describes the software platform running on the application processor unit (APU), which is logically further subdivided into user and kernel space components (see Figure 6-1). The Linux application rftool in the user space receives the command over Ethernet and performs the appropriate action.

  • Page 45: Software Architecture

    Chapter 6: Software Architecture Software Architecture Figure 6-1 shows the APU Linux software platform which has two logical software flows, namely control path and datapath. Datapath and control path are implemented using two different TCP sockets. The components involved in the software flows are implemented in the user space and kernel space.
  • Page 46 Chapter 6: Software Architecture Kernel Space Components • GEM driver provides the interface to send and receive packets over the GEM Ethernet controller. • TCP/IP stack provides the interface to create a transmission control protocol (TCP) socket. It also provides the interface to send and receive data over the TCP socket. The stack uses the GEM driver to send and receive packets from a network interface card (NIC).
  • Page 47 Chapter 6: Software Architecture Figure 6-2 shows the application execution flow. X-Ref Target - Figure 6-2 TCP Socket (Command/Data) Protocol Layer Command Handler DMA Client I2C/Clock RFdc User Space Driver Driver Driver X21254-091318 Figure 6-2: Application Execution Flow RFSoC Data Converter Evaluation Tool User Guide Send Feedback UG1287 (v2018.2) October 1, 2018 www.xilinx.com...

  • Page 48: Chapter 7: Protocol Specification

    Chapter 7 Protocol Specification The communication between the GUI and Linux application uses a string-based, space-separated command and response protocol. The Linux application maintains a table that maps command, arguments, and the corresponding method for that command (see Figure 7-1). X-Ref Target - Figure 7-1 X21255-090918 Figure 7-1: Command Table...

  • Page 49: Socket Interface

    Chapter 7: Protocol Specification Socket Interface The TCP/IP socket protocol is used for the datapath and control path. The LabVIEW GUI running on the host machine has TCP clients, and the TCP servers are running under the Linux application on the RFSoC PS. The control path works on TCP port 8081 and datapath works on TCP port 8082.
  • Page 50 Chapter 7: Protocol Specification Datapath The datapath interface is used to get the data and commands. The interface accepts the command and data on TCP port 8082. It accepts two commands: readdatafrommemory and writedatatomemory. Based on the received command, it triggers the DMA. It uses the DMA client driver to perform DMA operations.

  • Page 51: Command Types

    Chapter 7: Protocol Specification Command Types The commands for the evaluation tool fall into the following categories: • Basic commands • RFDC API commands—Arguments are 1:1 with the RFDC API definition, with the order specified by the order they appear in the API and C structures (Struct). •...
  • Page 52 Chapter 7: Protocol Specification 1. Depending on the memory type, select BRAM/DDR and set GPIOs. (If it is BRAM, the hardware loops back the data; if it is DDR, DMA loops back the data.) 2. Map the memory, copy content, and trigger DMA. 3.
  • Page 53 Chapter 7: Protocol Specification Figure 7-4 shows the control path and datapath flow. X-Ref Target - Figure 7-4 Remote Machine TCP Socket TCP Socket Control Path Datapath (TCP port 8081) (TCP port 8082) User Space TCP Socket TCP Socket Firmware/Application RFdc User Space Driver PL Memory Device...

  • Page 54: Multi-Tile Sync

    DMA. Multi-Tile Sync For details about the multi-tile sync feature, see the “Multi-Converter Synchronization” section of the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) [Ref DAC Flow for Non-MTS 1. This sequence needs to be followed for each writedatatomemory () command per DAC channel: a.
  • Page 55 Chapter 7: Protocol Specification g. Deassert external FIFO RESET for corresponding DAC channel. h. Enable RFDC FIFO for corresponding DAC channel. Trigger SG DMA. On DMA completion, enable Channel X Control GPIO (X = 0…7) as per selected DAC. DAC Flow for MTS 1.
  • Page 56 Chapter 7: Protocol Specification MTS Disable Flow for DAC 1. Send MTS_Setup (disable, DAC) command with disable argument. a. Configure Multi-Tile Control select signal to enable Tile0_DAC_Clock and Tile1_DAC_Clock out of BUFGMUX and to disable Channel 0 Control (common channel control signal). b.
  • Page 57 Chapter 7: Protocol Specification 5. This sequence needs to be followed for each readdatafrommemory () command per ADC channel. a. Get Tile Id, Block ID, and size of data. b. Select requested ADC channel by configuring streaming MUX GPIO. c. Enable IQ GPIO, if IQ mode is selected. d.

  • Page 58: Chapter 8: Zynq Ultrascale+ Rfsoc Data Converter Bare-Metal/Linux Driver

    Zynq UltraScale+ RFSoC Data Converter Bare-metal/Linux Driver The Linux APIs for the Zynq® UltraScale+™ RFSoC Data Converter is described in the Zynq UltraScale+ RFSoC Data Converter Bare-metal/Linux Driver appendix of Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269)

  • Page 59: Chapter 9: System Considerations

    Chapter 9 System Considerations This chapter describes the boot process and address mapping. Boot Process The design uses a non-secure boot flow and SD boot mode. The sequence diagram in Figure 9-1 shows the steps and order in which the individual boot components are loaded and executed.

  • Page 60: Global Address Map

    11], and chapter Boot and Configuration in the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref Global Address Map For more information on system addresses, see the System Addresses chapter in the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref Memory The DMA instances in the PL use a 36-bit address space so they can access the DDR Low and DDR High address.

  • Page 61: Memory Mapping For Rf-Dac/Rf-Adc

    Chapter 9: System Considerations Memory Mapping for RF-DAC/RF-ADC PL DDR is divided into four partitions (reserved memory), and each partition is 512 MB. It can run either RF-DAC/RF-ADC from these partitions. It can run either RF-DAC/RF-ADC from this partition. Table 9-2 lists partitions, their starting address, and their size.

  • Page 62: Appendix A: Reference Design Protocol Specification

    Appendix A Reference Design Protocol Specification Commands Table A-1 lists the commands used in the evaluation tool design. Table A-1: Command List Command Arguments Return Purpose/Comments Basic Commands RFdcVersion None Version Number(s) RFdc API Version, for example, "v3_1" Version None Version Number(s) Protocol Version, for example, "v1_0"...
  • Page 63 Appendix A: Reference Design Protocol Specification Table A-1: Command List (Cont’d) Command Arguments Return Purpose/Comments GetQMCSettings Type, Tile, Block Type, Tile, Block, Get QMC settings for the QMCSettings requested type, tile, and block. ShutDown Type, Tile None Shuts down a tile (the tile must be enabled in the bitstream).

  • Page 64: Example Commands And Responses

    Appendix A: Reference Design Protocol Specification Table A-1: Command List (Cont’d) Command Arguments Return Purpose/Comments MTS_Setup Type, Enable Success/Fail Setup resources for multi-tile synchronization feature. SetMemtype Mem_type Success/Fail Set memory type to DDR or BRAM. GetMemtype None Mem_type Get selected memory type. ZCU111 Board Commands SetExtParentclk board id, frequency...

  • Page 65: Control Path Core Implementation

    Appendix A: Reference Design Protocol Specification #invalid number of arguments SetMixerSettings 0 Error: SetMixerSettings: Invalid Number of Arguments # valid command and response (no data returned - args: Type, Tile, Block, Freq, PhaseOffset, EventSource, FineMixerMode, CoarseMixerFreq, FineMixerScale) SetMixerSettings 0 1 2 3.4 0.0 .. SetMixerSettings: #valid command and response (data returned - Freq, PhaseOffset, EventSource, FineMixerMode, CoarseMixerFreq, FineMixerScale)
  • Page 66 Appendix A: Reference Design Protocol Specification • cmd_interface (.c/.h) This is the core of the command protocol. It contains a menu/table of commands ° and their expected arguments. This menu is implemented as an array of command-structures. ° The command-structures contain the command name, the expected arguments, the argument number format (long, unsigned, double), and a function-pointer to call if the command matches.
  • Page 67 Appendix A: Reference Design Protocol Specification This function should be pointed to the method used to actually transmit strings or ° characters over the desired communication interface. • Non-blocking Implementation of command and datapath is non-blocking. ° RFSoC Data Converter Evaluation Tool User Guide Send Feedback UG1287 (v2018.2) October 1, 2018 www.xilinx.com...

  • Page 68: Appendix B: Additional Resources And Legal Notices

    Appendix B Additional Resources and Legal Notices Xilinx Resources For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. Solution Centers See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.

  • Page 69: References

    These Xilinx documents provide supplemental material useful with this guide: 1. Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889) 2. Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) 3. Zynq UltraScale+ Device Technical Reference Manual (UG1085) 4. ZCU111 RFSoC RF Data Converter Evaluation Tool Getting Started Guide This document is inside the evaluation tool ZIP file package rdf0476-zcu111-rf-dc-eval-tool-2018-2.zip available at the...

  • Page 70: Please Read: Important Legal Notices

    LIABILITY. © Copyright 2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. ARM is a registered trademark of ARM in the EU and other countries.

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