Intel Arria 10 User Manual page 317

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 220. Standard PCS Parameters
Standard PCS / PMA interface width
FPGA fabric / Standard TX PCS interface width
FPGA fabric / Standard RX PCS interface width
Enable 'Standard PCS' low latency mode
TX FIFO mode
RX FIFO Mode
Enable tx_std_pcfifo_full port
Enable tx_std_pcfifo_empty port
Enable rx_std_pcfifo_full port
Enable rx_std_pcfifo_empty port
TX byte serializer mode
RX byte deserializer mode
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
RX rate match FIFO mode
RX rate match insert/delete -ve pattern (hex)
RX rate match insert/delete +ve pattern (hex)
Enable rx_std_rmfifo_full port
Enable rx_std_rmfifo_empty port
PCI Express* Gen 3 rate match FIFO mode
Enable TX bit slip
Enable tx_std_bitslipboundarysel port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment patterns to achieve sync
Parameter Range
8, 10, 16, 20
8, 10, 16, 20, 32, 40
8, 10, 16, 20, 32, 40
On/Off
Off (for Basic with Rate Match)
low_latency
register_fifo
fast_register
low_latency
register_fifo
On/Off
On/Off
On/Off
On/Off
Disabled
Serialize x2
Serialize x4
Disabled
Deserialize x2
Deserialize x4
On/Off
On/Off
On/Off
Disabled
Basic 10-bit PMA (for Basic with Rate Match)
Basic 20-bit PMA (for Basic with Rate Match)
User-defined value
User-defined value
On/Off
On/Off
Bypass
On/Off
On/Off
bitslip
manual (PLD controlled)
synchronous state machine
7, 8, 10, 16, 20, 32, 40
User-defined value
0-255
® ®
Intel Arria 10 Transceiver PHY User Guide
continued...
317