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BitFlow NEO-PCE-CLB Hardware Reference Manual

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The Neon
Hardware Reference Manual
BitFlow, Inc.
400 West Cummings Park, Suite 5050
Woburn, MA 01801
USA
Tel: 781-932-2900
Fax: 781-933-9965
Email: support@bitflow.com
Web: www.bitflow.com
Revision G.5

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  • Page 1 The Neon Hardware Reference Manual BitFlow, Inc. 400 West Cummings Park, Suite 5050 Woburn, MA 01801 Tel: 781-932-2900 Fax: 781-933-9965 Email: support@bitflow.com Web: www.bitflow.com Revision G.5...
  • Page 2 BitFlow, Inc. BitFlow, Inc. makes no implicit warranty for the use of its products and assumes no responsibility for any errors that may appear in this document, nor does it make a commit- ment to update the information contained herein.

  • Page 3: Table Of Contents

    Technical Support NEO-P-1 Sales Support NEO-P-1 Conventions NEO-P-2 1 - General Description and Architecture The Neon NEO-1-1 NEO-PCE-CLB General Description NEO-1-2 NEO-PCE-CLD General Description NEO-1-4 NEO-PCE-CLQ General Description NEO-1-6 NEO-PCE-DIF General Description NEO-1-8 Virtual vs Hardware Frame Grabbers NEO-1-10 The Virtual Frame Grabber (VFG) NEO-1-10...
  • Page 4 Example NEO-5-2 Restrictions NEO-5-2 PLL Locking NEO-5-3 Handling Encoder Slow Down or Stopping NEO-5-3 Encoder Divider Control Registers NEO-5-4 6 - Power Over Camera Link (PoCL) Introduction NEO-6-1 PoCL Compatibility NEO-6-2 PoCL Safe Power NEO-6-3 PoCL Control Registers NEO-6-5 BitFlow, Inc.
  • Page 5 CON20 Register NEO-8-79 CON21 Register (Bayer Version) NEO-8-82 CON22 Register NEO-8-85 CON23 Register NEO-8-87 CON24 Register NEO-8-89 CON25 Register NEO-8-93 CON26 Register NEO-8-95 CON27 Karbon Register NEO-8-97 CON27 Neon-DIF Register NEO-8-99 CON36 Register NEO-8-101 CON37 Register NEO-8-103 CON38 Register NEO-8-105 BitFlow, Inc.
  • Page 6 11 - Electrical Interfacing Introduction NEO-11-1 Trigger NEO-11-2 Trigger Input Types NEO-11-2 The Optocoupled Trigger NEO-11-2 Encoder NEO-11-4 Encoder Input Types NEO-11-4 The Optocoupled Encoder NEO-11-4 General Purpose Inputs (GPIN) NEO-11-6 Introduction NEO-11-6 General Purpose Outputs (GPOUT) NEO-11-7 BitFlow, Inc.
  • Page 7 Switches NEO-13-11 Switch S1, All Neon models NEO-13-11 Switch S2, NEO-PCE-CLB Revision 2 Only NEO-13-11 Switches S3 and S6, NEO-PCE-CLB Revision 2 Only NEO-13-11 Switches S4 and S7, NEO-PCE-CLB Revision 2 Only NEO-13-12 Switch S5, NEO-PCE-CLB Revision 2 Only NEO-13-12...
  • Page 8 -TOC-6 BitFlow, Inc. Version...

  • Page 9: Support Services Neo

    Second, it is a reference manual describing in detail the functionality of all of the board’s registers. P.1.1 Support Services BitFlow, Inc. provides both sales and technical support for the Neon family of prod- ucts. P.1.2 Technical Support Our web site is www.bitflow.com.
  • Page 10 Table P-1 Base Abbreviations Base Designator Example Binary 1010b Decimal None 4223 Hexidecimal 12fah Table P-2 shows the numerical abbreviations that are used in this manual. Table P-2 Numeric Abbreviations Abbreviation Value Example 1024 256K 1048576 NEO-P-2 BitFlow, Inc. Version G.5...

  • Page 11: General Description And Architecture

    There are a few models in the Neon family: NEO-PCE-CLB, supports one base CL cameras (Revision 1 and Revision 2) NEO-PCE-CLD, supports two base CL cameras NEO-PCE-CLQ, supports four base CL cameras NEO-PCE-DIF, supports one differential camera Version G.5...

  • Page 12: Neo-Pce-Clb General Description Neo-1-2

    PCI Express Bus Figure 1-1 NEO-PCE-CLB Block Diagram The NEO-PCE-CLB implements the Camera Link base configuration, i.e. it can accept a single camera putting out up to 24 bits of data. The NEO-PCE-CLB can accept input data at up to 85 Mhz.
  • Page 13 General Description and Architecture NEO-PCE-CLB General Description The FIFO block decouples the camera from the DMA engine. It is implemented with dual ported memories. The Camera Control block handles both camera synchronization as well as external I/ O. The block contains the CTABs which are uses to synchronize acquisition with the camera, determine which pixels/lines get acquired and which do not, generate con- trol signals to the camera and to external devices.

  • Page 14: Neo-Pce-Cld General Description Neo-1-4

    Each interface is really a completely independent Virtual Frame Grabber (VFG). Put another way, the NEO-PCE-CLD has two complete copies of the NEO-PCE-CLB as shown in Figure 1-1. The main difference being that both VFGs share a common I/O connector (P1).
  • Page 15 CPU cycles. There is an on-board UART, as required by the CL specification. The IO connector block has transmitters/receivers to communicate with external industrial equipment (triggers, encoders, light strobes etc.). Version G.5 BitFlow, Inc. NEO-1-5...

  • Page 16: Neo-Pce-Clq General Description Neo-1-6

    Each interface is really a completely independent Virtual Frame Grabber (VFG). Put another way, the NEO-PCE-CLQ has four complete copies of the NEO-PCE-CLB as shown in Figure 1-1. The main difference being that all VFGs share a common I/O connector (P1).
  • Page 17 CPU cycles. There is an on-board UART, as required by the CL specification. The IO connector block has transmitters/receivers to communicate with external industrial equipment (triggers, encoders, light strobes etc.). Version G.5 BitFlow, Inc. NEO-1-7...

  • Page 18: Neo-Pce-Dif General Description Neo-1-8

    FIFO. This block re-arranges on-the-fly the data from the camera’s taps so that the data is written in raster scan format in the host memory. The FIFO block decouples the camera from the DMA engine. It is implemented with dual ported memories. NEO-1-8 BitFlow, Inc. Version G.5...
  • Page 19 CPU cycles. There is an on-board UART which can be use with cameras that support serial commu- nications. The IO connector block has transmitters/receivers to communicate with external industrial equipment (triggers, encoders, light strobes etc.). Version G.5 BitFlow, Inc. NEO-1-9...

  • Page 20: Virtual Vs Hardware Frame Grabbers Neo-1-10

    BitFlow drivers. 1.6.1 The Virtual Frame Grabber (VFG) The Karbon family was the first board from BitFlow that supports the concept of the virtual frame grabber (VFG). The NEO-PCE-CLD and NEO-PCE-CLQ also use this con- cept. The idea behind the VFG is to separate the hardware platform (connectors, lam- inate, FPGAs, etc.) from the frame grabbing functionality that software applications...

  • Page 21: Firmware, Camera Files And Downloads Neo-1-11

    Note that all the devices present on a NEO-PCE-CLD and NEO-PCE-CLQ will appear in SysReg as separate BitFlow Boards Found. The order that the VFGs appear in Sys- Reg is determined by the operating system and is somewhat arbitrary. However, Sys- Reg lists the connector(s) associated with each VFG, so that a connection can be made between VFG and physical connector on the board.
  • Page 22 Virtual vs Hardware Frame Grabbers The Neon NEO-1-12 BitFlow, Inc. Version G.5...

  • Page 23: Acquisition And Camera Control

    Acquisition and Camera Control Introduction Acquisition and Camera Control Chapter 2 2.1 Introduction This section covers acquisition and camera control for the R64-CL, Karbon-CL, Neon- CL, Neon-Dif, Karbon-CXP and the Alta-AN families of frame grabbers. Version G.5 BitFlow, Inc. NEO-2-1...

  • Page 24: Bitflow's Flow-Thru Architecture Neo-2-2

    BitFlow’s Flow-Thru Architecture The Neon 2.2 BitFlow’s Flow-Thru Architecture The MUX component of the block diagrams for the Alta, Karbon, Neon and R64 is composed of a chain of sub-blocks that make up the Flow-Thru Architecture (FTA). Figure 2-1 shows the structure of the FTA for the Camera Link boards. Figure 2-2 shows the structure of the Alta family.
  • Page 25 Acquisition and Camera Control BitFlow’s Flow-Thru Architecture The amount of data written in the FIFOs is controlled by the Acquisition Window. The vertical and horizontal size of this window is programmed in the ALPF and the ACLP registers respectively (see Section 2.4). The timing of this window is determined by the camera and the acquisition state machine.
  • Page 26 BitFlow’s Flow-Thru Architecture The Neon Channel Channel Channel Link Chip Link Chip Link Chip Channel X Channel Y Channel Z Equalizer Equalizer Equalizer FIFO FIFO FIFO Camera Link Pixel PIX_DEPTH Data Descrambler SHIFT_RAW, SHIFT_DSP, SHIFT_RAW_LEFT, Barrel Barrel Barrel Barrel SHIFT_DISP_LEFT,...
  • Page 27 Acquisition and Camera Control BitFlow’s Flow-Thru Architecture A-to-D A-to-D A-to-D Camera Link Pixel PIX_DEPTH Data Descrambler SHIFT_RAW, SHIFT_DSP, SHIFT_RAW_LEFT, Barrel Barrel Barrel Barrel SHIFT_DISP_LEFT, Shifter Shifter Shifter Shifter SHIFT_DISP_SELECT 2:1 MUX Synthetic Video VID_SOURCE 32-Bit 32-Bit VIDEO_MASK Mask Mask 8-Bit...
  • Page 28 BitFlow’s Flow-Thru Architecture The Neon CoaXPress Data Packet Router Pixel Data Descrambler PIX_DEPTH SHIFT_RAW, SHIFT_DSP, SHIFT_RAW_LEFT, Barrel Barrel Barrel Barrel SHIFT_DISP_LEFT, Shifter Shifter Shifter Shifter SHIFT_DISP_SELECT 2:1 MUX Synthetic Video VID_SOURCE 32-Bit 32-Bit VIDEO_MASK Mask Mask 8-Bit 8-Bit 8-Bit 8-Bit...
  • Page 29 Bayer decoder, 1 tap 8 bit MUX_BAY_OE Bayer decoder, 2 taps, odd-even pixels MUX_BAY_2TS Bayer decoder, 2 taps, segmented MUX_4WI 4 taps, 4-way interleaved MUX_2TOEPI 2 taps, odd-even pixels, both inverted MUX_1TI 1 tap, inverted Version G.5 BitFlow, Inc. NEO-2-7...

  • Page 30: Camera Specific Firmware For Camera Link Models (Cl Models Only) Neo

    MUX_8WI 8 taps, 8-way interleaved MUX_BAY_2TS_RI Bayer decoder, 2 taps, segmented, right inverted MUX_4TS2RI Four taps, segmented, right two taps inverted MUX_8TSOEP4RI Eight taps, segments, odd/even pixel, for right taps inverted MUX_10WI Ten taps, interleaved NEO-2-8 BitFlow, Inc. Version G.5...

  • Page 31: Generation Of Acquisition Windows Neo-2-9

    (HSTART or LEN). This is done by the DELAY bits in CON14. The HCTAB is the Horizontal Control Table that generates the HSTART, see section on CTABs. Figure 2-4 shows the controls that generate the HAW. Version G.5 BitFlow, Inc. NEO-2-9...

  • Page 32: The Vertical Active Window, Vaw Neo-2-10

    The VSTART bit in the VCTAB, if VAW_START = 1. The start of FEN, if VAW_START = 0. Data will be acquired in the window defined by the HAW and the VAW Figure 2-5 shows the controls that generate the VAW. NEO-2-10 BitFlow, Inc. Version G.5...
  • Page 33 Acquisition and Camera Control Generation of Acquisition Windows ALPF VSTART Vertical CTAB Generator VAW_START Figure 2-5 Generation of the Vertical Active Window, VAW Version G.5 BitFlow, Inc. NEO-2-11...
  • Page 34 INC_V ENVLOAD LOGIC VCOUNT ADDRESS GPV0 GPV1 LOAD LOAD_V GPV2 LOGIC GPV3 VCTAB (SRAM) RESET_V RESET LOGIC VCOUNT (COUNTER) Figure 2-6 Vertical Control Table The Vertical Control Table is made up of the following blocks: NEO-2-12 BitFlow, Inc. Version G.5...

  • Page 35: The Vctab Functions Neo-2-13

    Start of VAW VRESET Vertical Reset ENVLOAD FEN Mask, enable load CTAB Interrupt GPV0 General purpose vertical function 0 GPV1 General purpose vertical function 1 GPV2 General purpose vertical function 2 GPV3 General purpose vertical function 3 Version G.5 BitFlow, Inc. NEO-2-13...
  • Page 36 8000h. At the end of the vertical acquisition window the RESET_V will be asserted, which in turn will reset the VCOUNT. VCOUNT will wait at address 0000h until TRIGGER is asserted. NEO-2-14 BitFlow, Inc. Version G.5...

  • Page 37: Vertical Control Table Size Neo-2-15

    The Horizontal Control Table (HCTAB) is 8 bits wide. The function of each bit is show in the following table. Figure 2-7 depicts the structure of the HCTAB. For clarity, the address and data path that allow the host to program the HCTAB are not shown Version G.5 BitFlow, Inc. NEO-2-15...
  • Page 38 The output of the HCTAB depends on the data that has been written in the HCTAB by the host. If the HCOUNT is free running, it will cyclically scan all the HCTAB’s addresses. Any arbitrary cyclic waveform can be implemented by programming the HCTAB with the adequate data. NEO-2-16 BitFlow, Inc. Version G.5...

  • Page 39: The Hctab Functions Neo-2-17

    There are only two instances when we want to inhibit the incrementing of HCTAB. The first instance is when HCOUNT reaches 0000h, “Stop at Zero” case. The other instance is when HCOUNT reaches 1FF1h, the “Horizontal Stick” case. Version G.5 BitFlow, Inc. NEO-2-17...
  • Page 40 Operation on the rising/falling edge of LEN is selected by LENPOL, see CON14. The RESET_H Control RESET_H is the logic of reset HCOUNT. HCOUNT can be reset from several sources, according to HCNT_RST bitfield, see next section on camera synchronization. NEO-2-18 BitFlow, Inc. Version G.5...
  • Page 41 CTABs. The minimum horizontal pulse is 8 PCLKs. The minimum ver- tical pulse is one line. The CT’s can be steered to the Camera Controls (on the CL connectors) and to the GPOUTs, on the IO connector. Version G.5 BitFlow, Inc. NEO-2-19...

  • Page 42: Horizontal Control Table Size Neo-2-20

    The Control Tables (CTABs) The Neon 2.5.6 Horizontal Control Table Size The Horizontal Control Table has 8000h (32,768) entries. NEO-2-20 BitFlow, Inc. Version G.5...

  • Page 43: Synchronizing Acquisition, Camera, Ctabs And External Signals Neo-2-21

    VCNT_RLS_ZERO VCOUNT reset to 0000h VCNT_RST VCOUNT load with 8000h VCNT_LD VCOUNT frozen/released from 7FF0h VCNT_RLS_STK VCOUNT increment VCNT_INC Acquire (SNAP, GRAB, CONTINUOUS) ACQ_CON FREEZE acquisition FREEZE_CON ABORT acquisition ABORT_CON START vertical acquisition window VAW_START Version G.5 BitFlow, Inc. NEO-2-21...
  • Page 44 None Normal operation mode, no stop at 0000h TRIG_ASRT Edge Mode (aka Letter Mode), always stay at 0000h, release on TRIG_ASRT TRIG_HI Level Mode (aka Luggage Mode), stay at 0000h if TRIG_LO, release on TRIG_ASRT NEO-2-22 BitFlow, Inc. Version G.5...
  • Page 45 7ff0h. See Table 2-9. Table 2-9 VCNT_RLS_STK Initiator VCNT_RLS_STK Comments None Normal operation mode, no stop at 7FF0h VLOAD or VRESET Stick at 7FF0h till load (usually FEN) or reset asserted Version G.5 BitFlow, Inc. NEO-2-23...
  • Page 46 GRAB/SNAP/ SNAP FREEZE TRIG_ASRT Triggered initiated GRAB/SNAP/ FREEZE TRIG_ASRT and HOST_ Triggered SNAP WCMD_GRAB TRIG_HI Continuous data, wo. CTABs Note: See also Section 2.7 for more details on the how the acquisition commands work. NEO-2-24 BitFlow, Inc. Version G.5...

  • Page 47: Horizontal Operations And Events Neo-2-25

    HCOUNT. Each operation can be initiated by some event. The selection of the event that will initiate the specific operation is done by a set of three control bits related to each operation. Version G.5 BitFlow, Inc. NEO-2-25...
  • Page 48 RESET from SW RST_SW FEN asserted FEN_ASRT The sections below enumerate all of the horizontal operations and how the various events can initiate them. The control of each operation is independent from all of the others. NEO-2-26 BitFlow, Inc. Version G.5...
  • Page 49 1ff0h. See Table 2-18. Table 2-18 HCNT_RLS_STK Initiator HCNT_RLS_STK Comments None Normal operation mode, no stop at 1FF0h HLOAD or HRESET Stay at x1FF0 till load (usually LEN) or reset asserted Version G.5 BitFlow, Inc. NEO-2-27...
  • Page 50 This operation controls how and when HCOUNT loads (jumps to) 2000h (see Table 2- 19). Table 2-19 HCNT_LD Initiator HCNT_LD Comments None No load LEN_ASRT Load on LEN assert, qualified with ENHLOAD column ENC_ASRT Load on ENCODER assert, qualified with ENHLOAD column NEO-2-28 BitFlow, Inc. Version G.5...

  • Page 51: Acquisition Command And Status Neo-2-29

    For a SNAP command, when the SNAP starts, the AQCMD bits are cleared. Note that for SNAP, the AQCMD bits are written by the host and cleared by the state machine. If during a SNAP/GRAB operation another SNAP/GRAB command is issued, it is ignored. Version G.5 BitFlow, Inc. NEO-2-29...
  • Page 52 ACQ_CON=2 mode. Here, as long as the GRAB command is on, a frame will be acquired for every assertion of the TRIGGER. In this mode, there is no need for the host to write a new command. NEO-2-30 BitFlow, Inc. Version G.5...
  • Page 53 Freeze command written AQSTAT reset, grabbing ends Figure 2-9 Grab Command Timing VACTIVE AQCMD AQSTAT Grab command written AQSTAT set, grabbing starts Abort command written AQCMD reset, AQSTAT reset, grabbing ends Figure 2-10 Abort Command Timing Version G.5 BitFlow, Inc. NEO-2-31...
  • Page 54 Acquisition Command and Status The Neon VACTIVE AQCMD AQSTAT TRIG Snap command written Trigger asserts AQCMD reset and AQSTAT set AQSTAT reset Figure 2-11 Snap Command Timing with ACQ_CON = 2 NEO-2-32 BitFlow, Inc. Version G.5...
  • Page 55 Acquisition and Camera Control Acquisition Command and Status VACTIVE AQCMD AQSTAT TRIG Grab command written Trigger asserts AQSTAT set AQSTAT set AQSTAT reset AQSTAT reset Figure 2-12 Grab Command Timing with ACQ_CON = 2 Version G.5 BitFlow, Inc. NEO-2-33...

  • Page 56: Trigger Processing (Cl & Dif Models Only) Neo-2-34

    The Neon 2.8 Trigger Processing (CL & Dif Models Only) Note: BitFlow CoaXPress models have a different triggering system. Please see the chapter on the CoaXPress I/O system for more information. This section only applies to Camera Link and Analog models.

  • Page 57: Encoder Processing (Cl & Dif Models Only) Neo-2-35

    Encoder Processing (CL & Dif Models Only) 2.9 Encoder Processing (CL & Dif Models Only) Note: BitFlow CoaXPress models have a different triggering system. Please see the chapter on the CoaXPress I/O system for more information. This section only applies to Camera Link and Analog models.

  • Page 58: The On-Board Signal Generator Neo-2-36

    The On-Board Signal Generator The Neon 2.10 The On-Board Signal Generator The on-board signal generator has been replaced by the New Timing Generator (NTG). Please see Section 3.1 for more information. NEO-2-36 BitFlow, Inc. Version G.5...

  • Page 59: New Timing Generator

    NTG. Note: The NTG replaces the on-board timing generator that was prevouisly available on all boards. The NTG is much more flexible and easier to use. Please contact BitFlow if you have been using the previous on-board timing generator.

  • Page 60: Components And Control Neo-3-2

    Use the reduced frequency when long exposure periods and/or slow frame rates are needed (course granularity) You can use which ever mode suits your application regardless of whether you are using a line scan or an area scan camera.. NEO-3-2 BitFlow, Inc. Version G.5...

  • Page 61: Waveform Polarity Neo-3-3

    Note: On multi-VFG boards, there is always a master and one or more slaves for programming purpose. The master VFG must always have the bit NTG_SLAVE set to 0. The slave VFGs can either be indpendent (NTG_SLAVE = 0) or the same as the master VFG (NTG_SLAVE = 1). Version G.5 BitFlow, Inc. NEO-3-3...
  • Page 62 On the first clock after the trigger is asserted it will assert its output. It will then count up to NTG_EXPOSURE clocks then de-assert its output. Next it will reset itself and wait for another trigger. NEO-3-4 BitFlow, Inc. Version G.5...

  • Page 63: Ntg Control Registers Neo-3-5

    NTG_EXPOSURE CON26[27..0] The exposure time in units of one NTG clock. NTG_RESET CON26[30] Writing a 1 resets the NTG counter NTG_SLAVE CON26[31] 0 = NTG master, 1 = NTG timing slaved to master Version G.5 BitFlow, Inc. NEO-3-5...
  • Page 64 NTG Control Registers The Neon NEO-3-6 BitFlow, Inc. Version G.5...

  • Page 65: Quadrature Encoder

    (decrease the encoder count in a negative direction). This mode is useful in situations where a stage is moving back and forth, and lines need only be acquired if the stage is moving in one direction only. The direction of acquisition is controlled by the QENC_AQ_DIR register. Version G.5 BitFlow, Inc. NEO-4-1...

  • Page 66: Interval Mode Neo-4-2

    For example, the board can be programmed to acquire an interval in the posi- tive direction only, with no lines being reacquired. Many combinations are possible. 4.1.7 Control Registers Starting with Section 4.3 all of the registers needed to control the qudrature encoder system are explained. NEO-4-2 BitFlow, Inc. Version G.5...

  • Page 67: Introduction Neo

    VFGx_ENCODER_B+ VFGx_ENCODER_B- Note: VFGx - refers to the VFG number that you wish to connect to. For example, if you want to connect a TLL A output to VFG 0, then you would use VFG0_ENCODER_TTL. Version G.5 BitFlow, Inc. NEO-4-3...

  • Page 68: Understanding Stage Movement Vs. Quadrature Encoder Modes Neo-4-4

    Stage Movement Direction of Motion Stage Corresponding Encoder Count vs. Time These lines are acquired These lines are not acquried Encoder Counter Time Figure 4-1 Encoder Count vs Time NEO-4-4 BitFlow, Inc. Version G.5...
  • Page 69 Quadrature Encoder Understanding Stage Movement vs. Quadrature Encoder Modes Figure 4-2 shows all of the major quadrature encoder modes. Acquisition Direction Positive Negative Both Not Valid Zoom In Figure 4-2 Quadrature Encoder Modes vs. Acquisition Version G.5 BitFlow, Inc. NEO-4-5...

  • Page 70: Con15 Register Neo

    4.3 CON15 Register Name QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_DECODE QENC_AQ_DIR QENC_AQ_DIR QENC_INTRVL_MODE QENC_NO_REAQ QENC_DUAL_PHASE SCAN_STEP_TRIG QENC_RESET NEO-4-6 BitFlow, Inc. Version G.5...

  • Page 71: Con15 Register Neo

    (or decrease if QENC_AQ_DIR = 1). If there is “jitter” in the encoder signal, often caused by problems with the mechanical systems, it is possible for the board to acquire the same line or lines more than once as the Version G.5 BitFlow, Inc. NEO-4-7...
  • Page 72 The scan step circuit uses the encoder to generate a trigger to the system. The scan step trigger generates a trigger every N lines (N is set in the SCAN_STEP register). SCAN_STEP_TRIG Meaning Trigger comes of the normal source Trigger comes from the scan step circuit NEO-4-8 BitFlow, Inc. Version G.5...
  • Page 73 Quadrature Encoder CON15 Register QENC_RESET WO, CON15[31], Karbon, Neon Poking this bit to a 1 resets the entire quadrate encoder system. Version G.5 BitFlow, Inc. NEO-4-9...
  • Page 74 CON16 Register The Neon 4.4 CON16 Register Name QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_REAQ_MODE QENC_REAQ_MODE QENC_RESET_REAQ NEO-4-10 BitFlow, Inc. Version G.5...
  • Page 75 QENC_REAQ_MODE. However, the register QENC_REAQ_MODE can be used to set the board in a mode where the no re-aquisition circuit is reset automatically every pass over the image. Version G.5 BitFlow, Inc. NEO-4-11...
  • Page 76 4.5 CON22 Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP NEO-4-12 BitFlow, Inc. Version G.5...
  • Page 77 This bitfield controls the number of encoder pulses that must occur before a trigger is issued to the system. See SCAN_STEP_TRIG for more information. The Scan Step cir- cuit takes into account the interval and re-acquisition functions. Version G.5 BitFlow, Inc. NEO-4-13...
  • Page 78 4.6 CON51 Register Name QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_PHASEA QENC_PHASEB QENC_DIR QENC_INTRVL_IN QENC_NEW_LINES Reserved Reserved Reserved NEO-4-14 BitFlow, Inc. Version G.5...
  • Page 79 System is not inside the interval. Encoder counter is not between QENC_INTRVL_LL and QENC_INTRVL_ UL. Lines are not being acquired. System is inside the interval. Encoder counter is between QENC_INTRVL_LL and QENC_INTRVL_UL. Lines are being acquired. Version G.5 BitFlow, Inc. NEO-4-15...
  • Page 80 QENC_NEW_LINES Meaning The system is traversing lines that have already been visited. If QENC_NO_REAQ = 1, lines are not being acquired. The system is traversing new lines. Lines are being acquired. NEO-4-16 BitFlow, Inc. Version G.5...

  • Page 81: Encoder Divider

    Note: The Encoder Divider circuit described in this chapter replaces the previous circuit which could only divide the incoming encoder by an integer value and could not increase the encoder frequncy. Please contact BitFlow if you have been using the previous on-board encoder divider.

  • Page 82: Encoder Divider Details Neo-5-2

    The PLL has been designed to work in most machine visions applications. Support, therefore, is provided for the following inpute frequency range: Minimum input encoder frequency: 1.6 KHz Maximum input encoder frequency: 300 KHz NEO-5-2 BitFlow, Inc. Version G.5...

  • Page 83: Pll Locking Neo-5-3

    The board will stay in this state until Fin goes above 1.6 KHz. This is useful when the encoder is being driven by a stage that is travelling back and forth. At both ends of travel when the stage changes directions, the board will not acquire. Version G.5 BitFlow, Inc. NEO-5-3...

  • Page 84: Encoder Divider Control Registers Neo-5-4

    Output phased locked to input. 1 = Ouput runs open loop. ENC_DIV_FCLK_SEL CON16[31..29] Reserved for future support for alternate Encoder Divider PLL Master clock frequencies. Currently must be set to 0, which selects 50 MHz clock. NEO-5-4 BitFlow, Inc. Version G.5...

  • Page 85: Power Over Camera Link (Pocl)

    There are a number of registers on the Neon that are part of the PoCL system. Some of the registers provide control over PoCL and other provide feedback on the status of the PoCL system. See Section 6.4 for more information. Version G.5 BitFlow, Inc. NEO-6-1...

  • Page 86: Pocl Compatibility Neo-6-2

    In summary, the only way to use a PoCL camera is with a PoCL frame grabber and PoCL cable. However, with non-PoCL cameras, any combination will work. Finally, even if the particular combination does not work, nothing will be damaged should the combination be plugged in. NEO-6-2 BitFlow, Inc. Version G.5...

  • Page 87: Pocl Safe Power Neo-6-3

    PoCL normal state (resets POCL_EN). In order to recover from an over current event, the POCL_EN bit must be set to 1 again. Version G.5 BitFlow, Inc. NEO-6-3...
  • Page 88 (3.0 S) No Clock No Clock Check clock Check Fuse Blows clock Fuse Blows Clock Detected Clock Detected Running Running EN_PO PoCL = PoCL = WER = Power Fuse Blows Figure 6-1 PoCL State Diagram NEO-6-4 BitFlow, Inc. Version G.5...

  • Page 89: Pocl Control Registers Neo-6-5

    Only the register POCL_EN is a user programmable bit. The other registers are useful for determining the current state of the PoCL state machine. The bitfield POCL_EN is located the CON0 register. The other bitfields are all located in the CON38 register. Version G.5 BitFlow, Inc. NEO-6-5...
  • Page 90 PoCL Control Registers The Neon NEO-6-6 BitFlow, Inc. Version G.5...

  • Page 91: Introduction Neo

    Section 7.6 cycling HCOUNT Acquisition status, HCTAB CON6 Section 7.6 cycling LINES_TOGO Acquisition status, current line CON19 Section 7.6 in frame FIFO_EQ Camera status, video value CON20 Section 7.7 DEST_ADD DMA running CON22 Section 7.8 Version G.5 BitFlow, Inc. NEO-7-1...
  • Page 92 FCOUNT is a 3-bit frame counter that is incremented by the rising edge of FACTIVE. It can be used to track acquisition, especially in triggered modes. FCOUNT works for both area scan and line scan cameras. NEO-7-2 BitFlow, Inc. Version G.5...
  • Page 93 LEN does not reach the acquisition cir- cuitry. FENCOUNT is a 2-bit counter clocked by the camera’s FEN. Reading a constant value from this register indicates that the camera’s FEN does not reach the acquisition cir- cuitry. Version G.5 BitFlow, Inc. NEO-7-3...
  • Page 94 RD_TRIG_DIFF/TTL/OPTO, RD_ENC_DIFF/TTL/OPTO The Neon 7.4 RD_TRIG_DIFF/TTL/OPTO, RD_ENC_DIFF/TTL/OPTO The level of all trigger and encoder inputs can be read at any time. This helps estab- lish connection with external industrial equipment. NEO-7-4 BitFlow, Inc. Version G.5...
  • Page 95 SEL_TRIG register. Each individual input can be monitored via the corresponding RD_TRIG_XXX bit, but the TRIG_QUALIFIED always reports the state of the trigger input that is current being used by the acquisition circuitry. Version G.5 BitFlow, Inc. NEO-7-5...
  • Page 96 HCOUNT is the 2 LSB of the HCTAB address counter. This register indicates only if the HCTAB is cycling. Reading a constant value on HCOUNT indicates that the HCTAB address is stuck. LINES_TOGO specifies how more many lines there are till the end of the frame. NEO-7-6 BitFlow, Inc. Version G.5...
  • Page 97 It is helpful to determine if the camera is reacting to light. Covering the cam- era’s lens will yield a low value in this register. Pointing the camera to a light source will yield a high value in this register. Note: This register is not available on all models. Version G.5 BitFlow, Inc. NEO-7-7...
  • Page 98 DEST_ADD The Neon 7.8 DEST_ADD This register gives the DMA destination address. During acquisition, this register should change. Reading a constant value from this register suggests that the DMA operation is not progressing. NEO-7-8 BitFlow, Inc. Version G.5...
  • Page 99 All of the registers are 32 bits wide. These wide registers are named CON0, CON1, etc. Each registers is broken into one or more bitfields. Bitfields can be from one to 32 bits wide. Each bitfield controls a specific function on the board. Version G.5 BitFlow, Inc. NEO-8-1...
  • Page 100 0 to 7. Finally this section also indicates if the register is specific to only one product family. Bitfield discussion This section explains the purposed of the bitfield in detail. Usually meaning of every possible value of the bitfield is listed. NEO-8-2 BitFlow, Inc. Version G.5...
  • Page 101 This bitfield is functional on the Karbon-CL. Karbon-CXP This bitfield is functional on the Karbon-CXP. Neon This bitfield is functional on the Neon This bitfield is functional on the R64 family. Alta This bitfield is functional on the Alta family. Version G.5 BitFlow, Inc. NEO-8-3...
  • Page 102 8.3 CON0 Register Name CFGDATA CFGSTATUS CFGEN CFGDONE CFGCLOCK FW_7MHZ Reserved POCL_EN CFREQ CFREQ CFREQ Reserved L_CLKCON L_CLKCON SEL_UCLKC_7MHZ RELOAD_FPGA FW_SEL FW_SEL FW_SEL CPLD_MODE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved NEO-8-4 BitFlow, Inc. Version G.5...
  • Page 103 On the Karbon-CXP, this bit does not actually have any function but acts as a flag in the camera configuration file. If this bit is set in a camera file, then the software system will turn on the power for a CoaXPress camera. Version G.5 BitFlow, Inc. NEO-8-5...
  • Page 104 This bit selects the frequency that is used to driver the UART for serial communica- tions. This functionality is only available on boards with update firmware. The bit FW_ 7MHZ can be used to check the version of the firmware. SEL_UCLK_ Frequency 7MHZ 8 MHz 7.3 MHz NEO-8-6 BitFlow, Inc. Version G.5...
  • Page 105 CPLD_MODE R/W, CON0[19], Neon On the Neon, the CPLD used to load the FPGAs has two modes. This bit is used to set the mode. This is not a user programmable bit. Version G.5 BitFlow, Inc. NEO-8-7...
  • Page 106 8.4 CON1 Register Name VCNT_RLS_ZERO VCNT_RLS_ZERO VCNT_RLS_ZERO VCNT_RST VCNT_RST VCNT_RST VCNT_LD VCNT_LD VCNT_LD VCNT_RLS_STK VCNT_RLS_STK VCNT_RLS_STK ABORT_CON ABORT_CON ABORT_CON NO_VB_WAIT ACQ_CON ACQ_CON ACQ_CON FREEZE_CON FREEZE_CON FREEZE_CON ACQ_SAFETY NO_RULE INT_CTAB INT_OVSTEP INT_HW INT_TRIG INT_SER INT_QUAD INT_TRIGCON INT_TRIGCON NEO-8-8 BitFlow, Inc. Version G.5...
  • Page 107 VCOUNT is reset by the assertion of FEN or by the VRESET column in the VCTAB. 4 (100b) VCOUNT is reset by the de-assertion of the trigger, or by the VRESET column in the VCTAB. Version G.5 BitFlow, Inc. NEO-8-9...
  • Page 108 This bit has the following properties. NO_VB_WAIT Meaning Wait for the Vertical Active Window before executing the Head Tag Quad. Do not wait for the Vertical Active Window for exe- cuting the Head Tag Quad. NEO-8-10 BitFlow, Inc. Version G.5...
  • Page 109 FREEZE initiated by the Acquisition Counter or by the host command. 2 (010b) FREEZE initiated by the de-assertion of trigger or by the host command. ACQ_SAFETY R/W, CON1[22], Alta, Karbon-CL, Karbon-CXP, Neon, R64 Future use Version G.5 BitFlow, Inc. NEO-8-11...
  • Page 110 1. This interrupt can be cleared by the host writing a 0 to this location. For the host to be able to write to this location, the CMDWRITE code must be set to 3. INT_HW Meaning No interrupt from HW Interrupt from HW asserted. NEO-8-12 BitFlow, Inc. Version G.5...
  • Page 111 0 to this location. For the host to be able to write to this location, the CMDWRITE code must be set to 5. INT_QUAD Meaning No interrupt from QUAD Interrupt from QUAD asserted. Version G.5 BitFlow, Inc. NEO-8-13...
  • Page 112 0 (00b) reserved 1 (01b) Assert interrupt on rising edge of trigger. 2 (10b) Assert interrupt on falling edge of trigger. 3 (11b) Assert interrupt on both the rising and the falling edge of the trigger. NEO-8-14 BitFlow, Inc. Version G.5...
  • Page 113 8.5 CON2 Register Name HCNT_RLS_ZERO HCNT_RLS_ZERO HCNT_RLS_ZERO HCNT_RST HCNT_RST HCNT_RST HCNT_LD HCNT_LD HCNT_LD HCNT_RLS_STK HCNT_RLS_STK HCNT_RLS_STK RST_HVCOUNT RST_DPM_ADDR CTABHOLD Reserved CC1_CON CC1_CON CC1_CON CC2_CON CC2_CON CC2_CON CC3_CON CC3_CON CC3_CON CC4_CON CC4_CON CC4_CON CMDWRITE CMDWRITE CMDWRITE QTBSRC Version G.5 BitFlow, Inc. NEO-8-15...
  • Page 114 HCOUNT will be loaded by assertion of LEN if the ENHLOAD function in the HCTAB is set to 1. 2 (010b) HCOUNT will be loaded by assertion of encoder if the ENHLOAD function in the HCTAB is set to 1. NEO-8-16 BitFlow, Inc. Version G.5...
  • Page 115 This bit has the following properties. RST_DPM_ADDR Meaning Normal operation for DPM_ADDR Reset DPM_ADDR.. CTABHOLD R/W, CON2[14], Alta, Karbon-CL, Karbon-CXP, Neon, R64 This bit has the following properties. CTABHOLD Meaning Normal operation for CTABs Freeze outputs and operation of CTABs.. Version G.5 BitFlow, Inc. NEO-8-17...
  • Page 116 Signal steered to CC2 0 (000b) CT0 from CTAB 1 (001b) CT1 from CTAB 2 (010b) CT2 from CTAB 3 (011b) Free running signal generated on-board 4 (100b) Trigger Input 5 (101b) GPIN0 6 (110b) 7 (111b) NEO-8-18 BitFlow, Inc. Version G.5...
  • Page 117 0 (000b) CT0 from CTAB 1 (001b) CT1 from CTAB 2 (010b) CT2 from CTAB 3 (011b) Free running signal generated on-board 4 (100b) Trigger input 5 (101b) CT3 from CTAB 6 (110b) 7 (111b) Version G.5 BitFlow, Inc. NEO-8-19...
  • Page 118 No interrupt can be accessed by host 1 (001b) INT_CTAB 2 (010b) INT_OVSTP 3 (011b) INT_HW 4 (100b) INT_TRIG 5 (101b) INT_QTAB 6 (110b) INT_EOF 7 (111b) reserved QTBSRC RO, CON2[31], Alta, Karbon-CL, Karbon-CXP, Neon, R64 Always read back 1. NEO-8-20 BitFlow, Inc. Version G.5...
  • Page 119 CON3 Register 8.6 CON3 Register Name AQCMD AQCMD AQSTAT AQSTAT FACTIVE FCOUNT FCOUNT FCOUNT REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC AUX_DETECT GPIN0 GPIN1 GPIN2 GPIN3 GPIN4 Version G.5 BitFlow, Inc. NEO-8-21...
  • Page 120 This is a 3-bit modulo-8 counter. The counter is incremented by the start of the Verti- cal Acquisition Window. It is used as a debug/diagnostic tool. REV_DCC WO, CON3[23..8], Alta, Karbon-CL, Karbon-CXP, Neon, R64 FW revision. NEO-8-22 BitFlow, Inc. Version G.5...
  • Page 121 Controlled by inputs on the IO connector. The logical value applied to the corre- sponding pin will be reflected in this register. See also Section 11.4 for interfacing information. RO, CON3[31..30], Alta, Karbon-CL, Karbon-CXP, Neon, R64 Current state of the switch. Version G.5 BitFlow, Inc. NEO-8-23...
  • Page 122 8.7 CON4 Register Name ENINT_CTAB ENINT_OVSTEP ENINT_HW ENINT_TRIG ENINT_SER ENINT_QUAD EOF_IN_AQ INT_ANY ENINT_ALL AUX_CAM GPOUT0 GPOUT1 GPOUT2 GPOUT3 GPOUT4 GPOUT5 GPOUT6 RST_SER RST_OVS CL_DISABLE LCOUNT LCOUNT PCOUNT PCOUNT FENCOUNT FENCOUNT POP_TOSS PUMP_OFF DMA_BUSY HAW_START VAW_START NEO-8-24 BitFlow, Inc. Version G.5...
  • Page 123 This bit has the following properties. ENINT_HW Meaning HW interrupt disabled HW interrupt enabled ENINT_TRIG R/W, CON4[3], Alta, Karbon-CL, Karbon-CXP, Neon, R64 This bit has the following properties. ENINT_TRIG Meaning Trigger interrupt disabled Trigger interrupt enabled Version G.5 BitFlow, Inc. NEO-8-25...
  • Page 124 This bit can be checked first to see if some event caused the interrupt, before inquiring other bits to see the actual cause of the interrupt. ENINT_ALL R/W, CON4[8], Alta, Karbon, Neon This bit enables or disables all interrupts on boards that use the PLDA engine. NEO-8-26 BitFlow, Inc. Version G.5...
  • Page 125 GPOUT6 R/W, CON4[16], Alta, Karbon-CL, Neon, R64 The value written in this register will be reflected on the IO connector. See also CON8 for signals steered to the GPOUTs and Section 11.5 for electrical interfacing. Version G.5 BitFlow, Inc. NEO-8-27...
  • Page 126 For CXP board, bit enables/disables the clock coming from the CXP engine; used for diagnostics. For normal operation this bit should always be set to 0. CL_DISABLE Meaning Use CXP engine clock. Use internal clock. NEO-8-28 BitFlow, Inc. Version G.5...
  • Page 127 QUADs. PUMP_OFF R/W, CON4[28], R64, Alta, Karbon-CL, Karbon-CXP, Neon, R64 For normal operation this bit should be set to 0. It is used for high-level clean-up. PUMP_OFF Meaning DMA engine’s normal operation. Inhibit DMA operation. Version G.5 BitFlow, Inc. NEO-8-29...
  • Page 128 VAW_START Meaning The start of the Vertical Active Window (VAW) is con- trolled by the start of the FEN. The start of the Vertical Active Window is controlled by the VSTART column in the VCTAB. NEO-8-30 BitFlow, Inc. Version G.5...
  • Page 129 8.8 CON5 Register Name SEL_TRIG SEL_TRIG TRIGPOL SW_TRIG SELENC SELENC ENCPOL SW_ENC RD_TRIG_DIFF RD_TRIG_TTL RD_TRIG_OPTO RD_ENC_DIFF RD_ENC_TTL RD_ENC_OPTO TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY ENINT_EOF INT_EOF RD_FEN CCSYNC CCSYNC CCSYNC EN_TRIGGER EN_ENCODER Version G.5 BitFlow, Inc. NEO-8-31...
  • Page 130 R/W, CON5[3], Alta, Karbon-CL, Neon, R64 The SW trigger is OR-ed with the external trigger. The polarity of the SW trigger is always active-HI. TRIGPOL has no effect on the SW trigger. SW_TRIG Meaning SW trigger de-asserted. SW trigger asserted. NEO-8-32 BitFlow, Inc. Version G.5...
  • Page 131 This register reflects the status of the differential trigger input on the IO connector, pins 1,2. RD_TRIG_TTL RO, CON5[9], Alta, Karbon-CL, Neon, R64 This register reflects the status of the TTL trigger input on the IO connector, pin 3. Version G.5 BitFlow, Inc. NEO-8-33...
  • Page 132 VAW). This ordinarily corresponds to the camera’s end of frame. However, if the board is in start-stop triggered mode, this interrupt with also occur when the trigger de-asserts. The host writing a 1 to this bit will also cause and interrupt. The interrupt NEO-8-34 BitFlow, Inc. Version G.5...
  • Page 133 5 (101b) Reserved 6 (110b) Reserved 7 (111b) Reserved EN_TRIGGER R/W, CON5[30], Alta, Karbon-CL, Neon, R64 This bitfield has the following properties. EN_TRIGGER Meaning External (HW) selected trigger is disabled. External (HW) selected trigger is enabled. Version G.5 BitFlow, Inc. NEO-8-35...
  • Page 134 CON5 Register The Neon EN_ENCODER R/W, CON5[31], Alta, Karbon-CL, Neon, R64 This bitfield has the following properties. EN_ENCODER Meaning External (HW) selected encoder is disabled. External (HW) selected encoder is enabled. NEO-8-36 BitFlow, Inc. Version G.5...
  • Page 135 VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M ENC_DIV, ENC_DIV_M HCOUNT HCOUNT TRIG_QUALIFIED Reserved Version G.5 BitFlow, Inc. NEO-8-37...
  • Page 136 This register reflects the current value of the two LSBs of the HCOUNT. Reading this register and observing changes in its value means that the HCOUNT is cycling. TRIG_ RO, CON6[31], Alta, Karbon-CL, Neon, R64 QUALIFIED This is the current state of the selected (via SEL_TRIG) trigger input. NEO-8-38 BitFlow, Inc. Version G.5...
  • Page 137 8.10 CON7 Register Name AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT SEL_REG_GEN SEL_REG_GEN GEN_ONESHOT Reserved TAG_BANK TAG_BANK TAG_BANK TAG_BANK TAG_BANK TAG_BANK NTG_TO_ENC NTG_TO_TRIG Version G.5 BitFlow, Inc. NEO-8-39...
  • Page 138 This bit provides the ability for the NTG timing generator to rung the encoder input directly. This bit overrides the selection made by the SEL_ENC bit.. NTG_TO_ENC Meaning The encoder circuit is driven by the selected external encoder source. The encoder circuit is driven by the NTG. NEO-8-40 BitFlow, Inc. Version G.5...
  • Page 139 This bit provides the ability for the NTG timing generator to rung the trigger input directly. This bit overrides the selection made by the SEL_TRIG bit.. NTG_TO_TRIG Meaning The trigger circuit is driven by the selected external trigger source. The trigger circuit is driven by the NTG. Version G.5 BitFlow, Inc. NEO-8-41...
  • Page 140 8.11 CON8 Register Name GPOUT0_CON GPOUT0_CON GPOUT0_CON GPOUT1_CON GPOUT1_CON GPOUT1_CON GPOUT2_CON GPOUT2_CON GPOUT2_CON GPOUT3_CON GPOUT3_CON GPOUT3_CON GPOUT4_CON GPOUT4_CON GPOUT4_CON GPOUT5_CON GPOUT5_CON GPOUT5_CON GPOUT6_CON GPOUT6_CON GPOUT6_CON AFPDF AFPDF Reserved RLE_LOAD_H RLE_LOAD_H RLE_LOAD_H RLE_LOAD_H RLE_LOAD_V RLE_LOAD_V RLE_LOAD_V RLE_LOAD_V NEO-8-42 BitFlow, Inc. Version G.5...

  • Page 141: Gpout0_Con

    Internally generated CLOCK (frequency controlled by CFREQ in CON1). 6 (110b) Internally generated signal (frequency and duty- cycle controlled by CON17). 7 (111b) The trigger input signal is routed to the GPOUT1 out- put signal. Version G.5 BitFlow, Inc. NEO-8-43...

  • Page 142: Gpout2_Con

    3 (011b) CT2 from CTAB. 4 (100b) CT3 from CTAB. 5 (101b) Internally generated CLOCK (frequency controlled by CFREQ in CON1). 6 (110b) Internally generated signal (frequency and duty- cycle controlled by CON17). 7 (111b) reserved. NEO-8-44 BitFlow, Inc. Version G.5...

  • Page 143: Gpout4_Con

    3 (011b) CT2 from CTAB. 4 (100b) CT3 from CTAB. 5 (101b) Internally generated CLOCK (frequency controlled by CFREQ in CON1). 6 (110b) Internally generated signal (frequency and duty- cycle controlled by CON17). 7 (111b) reserved. Version G.5 BitFlow, Inc. NEO-8-45...

  • Page 144: Gpout6_Con

    RLE entry, not the CTAB location. In other words, if the jump point is 0x8000 CTAB location, but the RLE entry for this location is 3, then this register should be pro- grammed to 3. NEO-8-46 BitFlow, Inc. Version G.5...
  • Page 145 RLE entry, not the CTAB location. In other words, if the jump point is 0x20000 CTAB location, but the RLE entry for this location is 3, then this register should be pro- grammed to 3. Version G.5 BitFlow, Inc. NEO-8-47...
  • Page 146 8.12 CON9 Register Name MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV TRIM TRIM TRIM TRIM FW_TYPE FW_TYPE FW_TYPE FW_TYPE DISPLAY CLIP SHORT_FRAME RST_CALC_BANK CALC_BANK CALC_BANK CALC_BANK CALC_BANK CALC_BANK CALC_BANK ACPL_MUL ACPL_MUL NEO-8-48 BitFlow, Inc. Version G.5...
  • Page 147 8 LSB of the data will be acquired in each lane. To be able to display the 8 MSB (or any other consecutive group of 8 bits), the data must be shifted accordingly with the barrel shifter. For 9 to 16-bit cameras, setting this bit will result in an 8-bit dis- Version G.5 BitFlow, Inc. NEO-8-49...
  • Page 148 R/W, CON9[23], Alta, Karbon-CL, Karbon-CXP, Neon, R64 BANK For normal operation this bit should be 0. RST_CALC_BANK Meaning Normal operation Reset the calculated starting bank. CALC_BANK RO, CON9[29..24], Alta, Karbon-CL, Karbon-CXP, Neon, R64 Value of the current calculated starting bank. NEO-8-50 BitFlow, Inc. Version G.5...
  • Page 149 ACPL (Active Clocks Per Line) register. ACPL_MUL Meaning 0 (00b) Normal operation. ACPL is used as is 1 (01b) ACPL is multiplied by 2 2 (10b) Reserved 3 (11b) Reserved Version G.5 BitFlow, Inc. NEO-8-51...
  • Page 150 8.13 CON10 Register Name ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL FORMAT FORMAT FORMAT FORMAT FORMAT VID_SOURCE VID_SOURCE VID_SOURCE VID_SOURCE PIX_DEPTH PIX_DEPTH PIX_DEPTH PIX_DEPTH PIX_DEPTH FORCE_8BIT NEO-8-52 BitFlow, Inc. Version G.5...
  • Page 151 MUX_BAY_2TS Bayer decoder, 2 taps, segmented 17 (10001b) MUX_4WI 4 taps, 4-way interleaved 18 (10010b) MUX_2TOEPI 2 taps, odd-even pixels, both inverted 19 (10011b) MUX_1TI 1 tap, inverted 20 (10100b) MUX_8WI 8 taps, 8-way interleaved Version G.5 BitFlow, Inc. NEO-8-53...
  • Page 152 Synthetic horizontal static wedge 4 (0100b) Synthetic dynamic wedge 5 (0101b) Synthetic 00h 6 (0110b) Synthetic FFh 7 (0111b) Synthetic AAh 8 (1000b) Synthetic 55h 9 (1001b) Synthetic ABCDEF0123456789h 10 (1010b) Synthetic vertical static wedge NEO-8-54 BitFlow, Inc. Version G.5...
  • Page 153 3x12 BGR, DMAed as 48 bits (packed), display mode is 24 bits FORCE_8BIT R/W, CON10[31], Alta, Karbon-CL, Karbon-CXP, Neon, R64 This bitfield has the following properties. FORCE_8BIT Meaning 0 (000b) Normal operation 1 (001b) Only 8 LSB of pixel will be acquired Version G.5 BitFlow, Inc. NEO-8-55...
  • Page 154 8.14 CON11 Register Name ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD DPM_WP BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD UART_MASTER NEO-8-56 BitFlow, Inc. Version G.5...
  • Page 155 Last address for lane B (used for diagnostics). UART_MASTER R/W, CON11[31], Karbon-CL This bit controls which Karbon VFG is in control of the UART. Poke this bit to one in order to take control of the UART. Version G.5 BitFlow, Inc. NEO-8-57...
  • Page 156 8.15 CON12 Register Name CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD Reserved DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD RGBHSI NEO-8-58 BitFlow, Inc. Version G.5...
  • Page 157 Last address for lane D (used for diagnostics). RGBHSI R/W, CON11[31], Alta On boards that can do real time color conversion from RGB to HSI color space, the board controls what color space is put out.. RGBHSI Meaning Output RGB Output HSI Version G.5 BitFlow, Inc. NEO-8-59...
  • Page 158 8.16 CON13 Register Name VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK NEO-8-60 BitFlow, Inc. Version G.5...
  • Page 159 With the aid of this mask, individual bits in the video data stream can be set to 0. The 32 bit mask is duplicated for the 32 MSB of a 64 bit word. Bit N in VIDEO_MASK Meaning Set bit N to 0 Pass bit N as is Version G.5 BitFlow, Inc. NEO-8-61...
  • Page 160 8.17 CON14 Register Name SWRESET FENPOL LENPOL BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS SHIFT_RAW SHIFT_RAW SHIFT_RAW SHIFT_RAW SHIFT_RAW_LEFT DELAY DELAY DELAY SWAP UART_CON UART_CON Reserved DPM_SPLIT DPM_SPLIT DPM_SPLIT DPM_SPLIT NEO-8-62 BitFlow, Inc. Version G.5...
  • Page 161 R/W, CON14[15..3], Alta, Karbon-CL, Karbon-CXP, Neon, R64 R/W register for test/diagnostics. SHIFT_RAW R/W, CON14[19..16], Alta, Karbon-CL, Karbon-CXP, Neon, R64 This register defines for the barrel shifter the amount of shift for the data to be acquired Version G.5 BitFlow, Inc. NEO-8-63...
  • Page 162 HAW is delayed by 4 clocks 5 (101b) HAW is delayed by 5 clocks 6 (11ob) HAW is delayed by 6 clocks 7 (111b) HAW is delayed by 7 clocks SWAP R/W, CON14[24], Alta, Karbon-CL, Karbon-CXP, Neon, R64 Future use. NEO-8-64 BitFlow, Inc. Version G.5...
  • Page 163 This register controls how incoming data is written to the DPM. DPM_SPLIT Mode 0 (0000b) Normal mode 1 (0001b) Each tap’s output is split in half. 2 (0010b) to 14 (1110b) Reserved 15 (1111b) Each tap’s output is written in 4K chunks Version G.5 BitFlow, Inc. NEO-8-65...
  • Page 164 8.18 CON15 Register Name QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_DECODE QENC_AQ_DIR QENC_AQ_DIR QENC_INTRVL_MODE QENC_NO_REAQ QENC_DUAL_PHASE SCAN_STEP_TRIG QENC_RESET NEO-8-66 BitFlow, Inc. Version G.5...
  • Page 165 (or decrease if QENC_AQ_DIR = 1). If there is “jitter” in the encoder signal, often caused by problems with the mechanical systems, it is possible for the board to acquire the same line or lines more than once as the Version G.5 BitFlow, Inc. NEO-8-67...
  • Page 166 The scan step circuit uses the encoder to generate a trigger to the system. The scan step trigger generates a trigger every N lines (N is set in the SCAN_STEP register). SCAN_STEP_TRIG Meaning Trigger comes of the normal source Trigger comes from the scan step circuit NEO-8-68 BitFlow, Inc. Version G.5...
  • Page 167 Camera Control Registers CON15 Register QENC_RESET WO, CON15[31], Karbon-CL, Karbon-CXP, Neon Poking this bit to a 1 resets the entire quadrate encoder system. Version G.5 BitFlow, Inc. NEO-8-69...
  • Page 168 8.19 CON16 Register Name QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_REAQ_MODE QENC_REAQ_MODE QENC_RESET_REAQ ENC_DIV_FORCE_DC ENC_DIV_OPEN_LOOP ENC_DIV_FCLK_SEL ENC_DIV_FCLK_SEL ENC_DIV_FCLK_SEL NEO-8-70 BitFlow, Inc. Version G.5...
  • Page 169 This register is used to controls the behavior of the encoder divider when input fre- quency falls below the minimum. ENC_DIV_FORCE_DC Meaning Encoder divider runs in simple divider mode. Encoder divider output stops (goes to DC). Version G.5 BitFlow, Inc. NEO-8-71...
  • Page 170 Ouput runs open loop ENC_DIV_FCLK_ R/W, CON16[31..29], R64, Karbon-CL, Karbon-CXP, Neon This register is reserved for future support for alternate Encoder Divider PLL Master clock frequencies. Currently must be set to 0, which selects 50 MHz clock NEO-8-72 BitFlow, Inc. Version G.5...
  • Page 171 8.20 CON17 Register Name NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE NTG_RATE Reserved Reserved NTG_ONESHOT NTG_TRIG_MODE Version G.5 BitFlow, Inc. NEO-8-73...
  • Page 172 R/W, CON17[31], Alta, Karbon-CL, Karbon-CXP, Neon, R64 MODE This bit determines what triggers the NTG when it is in one shot mode. NTG_ONESHOT Mode NTG is triggered by the selected trigger signal NTG is triggered by the selected encoder signal NEO-8-74 BitFlow, Inc. Version G.5...
  • Page 173 8.21 CON18 Register Name ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV NTG_INVERT NTG_TIME_MODE Version G.5 BitFlow, Inc. NEO-8-75...
  • Page 174 See Section 3.1 for more information. This mode is useful for area scan cameras that need very long exposure times. NTG_TIME_MODE Meaning NTG clock is used as is. NTG clock is divided by 128. NEO-8-76 BitFlow, Inc. Version G.5...
  • Page 175 8.22 CON19 Register Name LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO ENC_DIV_N ENC_DIV_N ENC_DIV_N Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version G.5 BitFlow, Inc. NEO-8-77...
  • Page 176 This register will reflect the number of remaining lines left to be acquired till the end of the frame. ENC_DIV_N R/W, CON19[19..17], R64, Karbon-CL, Karbon-CXP, Neon This register represents the “N” parameter in the encoder divider equation. See Sec- tion 5.1 for more information. NEO-8-78 BitFlow, Inc. Version G.5...
  • Page 177 8.23 CON20 Register Name FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ VID_BRL VID_BRL VID_BRL VID_BRL VID_BRL VID_BRL VID_BRL VID_BRL VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM COLOR_MASK COLOR_MASK SHIFT_DSP_SELECT SHIFT_DSP SHIFT_DSP SHIFT_DSP SHIFT_DSP SHIFT_DSP_LEFT Version G.5 BitFlow, Inc. NEO-8-79...
  • Page 178 Supply barrel shifter with the acquisition shift code Supply barrel shifter with the display shift code. SHIFT_DISP R/W, CON20[30..27], Alta, Karbon-CL, Karbon-CXP, Neon, R64 This register holds the shift amount for data to be displayed. NEO-8-80 BitFlow, Inc. Version G.5...
  • Page 179 Camera Control Registers CON20 Register SHIFT_DSP_LEFT R/W, CON20[31], Alta, Karbon-CL, Karbon-CXP, Neon, R64 This bitfield has the following properties. SHIFT_DSP_LEFT Meaning Shift display data right Shift display data left. Version G.5 BitFlow, Inc. NEO-8-81...
  • Page 180 BLUE_GAIN BLUE_GAIN BLUE_GAIN BLUE_GAIN DECODER_OUT DECODER_OUT DECODER_OUT Reserved BAYER_BIT_DEPTH BAYER_BIT_DEPTH DECODER_PHASE DECODER_PHASE CON21 is a “soft” register. Soft registers change definitions depending on the version board and the firmware that is downloaded to the board. NEO-8-82 BitFlow, Inc. Version G.5...
  • Page 181 Decode intensity on all three channels 3 (011b) Decode red on all three channels 4 (100b) Decode green on all three channels 5 (101b) Decode blue on all three channels 6 (110b) Reserved 7 (111b) Reserved Version G.5 BitFlow, Inc. NEO-8-83...
  • Page 182 CCD. DECODER_PHASE Meaning 0 (00b) First two pixels: Blue, Green 1 (01b) First two pixels: Green, Blue 2 (10b) First two pixels: Red, Green 3 (11b) First two pixels: Green, Red NEO-8-84 BitFlow, Inc. Version G.5...
  • Page 183 8.25 CON22 Register Name FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA FLASH_DATA SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP Version G.5 BitFlow, Inc. NEO-8-85...
  • Page 184 This bitfield controls the number of encoder pulses that must occur before a trigger is issued to the system. See SCAN_STEP_TRIG for more information. The Scan Step cir- cuit takes into account the interval and re-acquisition functions. NEO-8-86 BitFlow, Inc. Version G.5...
  • Page 185 8.26 CON23 Register Name DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE Reserved Reserved Reserved Reserved Reserved Reserved Reserved CTAB_INT_CON LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version G.5 BitFlow, Inc. NEO-8-87...
  • Page 186 CTAB interrupt. The interrupt rate will be every N lines, where N is the value programmed in this register. Note that CTAB_INT_CON must be set to one in order for the interrupts to be seen by the host. NEO-8-88 BitFlow, Inc. Version G.5...
  • Page 187 LUT_HOST_ADDR LUT_HOST_ADDR LUT_HOST_ADDR LUT_HOST_ADDR LUT_BANK LUT_BANK Reserved LUT_DATA_WRITE_ LUT_HOST_LANE LUT_HOST_LANE LUT_WEN LUT_HOST_ACCESS CON24 is a “soft” register. Soft registers change definitions depending on the version board and the firmware that is downloaded to the board. Version G.5 BitFlow, Inc. NEO-8-89...
  • Page 188 R/W CON24[23..16], Alta, Karbon-CL, Karbon-CXP, Neon, R64 ADDR This register is used to set the address for a read operation from the LUT memory or a write operation to the LUT memory. See the description of LUT_HOST_DATA for more details. NEO-8-90 BitFlow, Inc. Version G.5...
  • Page 189 When LUT_DATA_WRITE_SEL is set to 1, Writing a 1 to this bit causes the value in LUT_HOST_DATA to be transferred to the LUT memory. When LUT_DATA_WRITE_SEL is set to 0, writing to this bit has no effect. See LUT_HOST_DATA for more information. Version G.5 BitFlow, Inc. NEO-8-91...
  • Page 190 R/W, CON24[31], Alta, Karbon-CL, Karbon-CXP, Neon, R64 ACCESS These bits turns on and off host access to the LUT.. DECODER_OUT Meaning The LUT cannot be accessed by the host The LUT can be accessed by the host NEO-8-92 BitFlow, Inc. Version G.5...
  • Page 191 8.28 CON25 Register Name DELAY_TAP1 DELAY_TAP1 DELAY_TAP1 DELAY_TAP1_SEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version G.5 BitFlow, Inc. NEO-8-93...
  • Page 192 This bit selects the register that controls the delay for tap 1. Tap 0 is always controlled by the register DELAY. DELAY_TAP1_SEL Meaning Tap 1 is controlled by DELAY Tap 1 is controlled by DELAY_TAP1 NEO-8-94 BitFlow, Inc. Version G.5...
  • Page 193 8.29 CON26 Register Name NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE NTG_EXPOSURE Reserved Reserved NTG_RESET NTG_SLAVE Version G.5 BitFlow, Inc. NEO-8-95...
  • Page 194 This bit determines how whether the NTG is running on its own timing, or slave to the master VFG. Note: This bit must be set to 0 for the master VFG. NTG_SLAVE Mode NTG is running on its own timing NTG is slaved to the master VFG NEO-8-96 BitFlow, Inc. Version G.5...
  • Page 195 8.30 CON27 Karbon Register Name FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_ADDR FLASH_WP FLASH_RST FALSH_BE FLASH_CE FLASH_OE FLASH_WE Version G.5 BitFlow, Inc. NEO-8-97...
  • Page 196 This register is used for read/write to the on board flash memory. FLASH_OE R/W, CON27[30], Karbon-CL, Karbon-CXP This register is used for read/write to the on board flash memory. FLASH_WE R/W, CON27[31], Karbon-CL, Karbon-CXP This register is used for read/write to the on board flash memory. NEO-8-98 BitFlow, Inc. Version G.5...
  • Page 197 8.31 CON27 Neon-DIF Register Name CLK_OUT_FREQ CLK_OUT_FREQ CLK_OUT_FREQ CLK_POL CLK_OUT_LEVEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version G.5 BitFlow, Inc. NEO-8-99...
  • Page 198 This bit controls the clock polarity that used to sample the incoming digital data. CLK_POL Meaning Samples on rising edge Sample on falling edge CLK_OUT_LEVEL R/W, CON27[4],Neon-DIF This bit controls the level of the output clock. CLK_OUT_LEVEL Meaning Clock is LVDS Clock is RS-422 NEO-8-100 BitFlow, Inc. Version G.5...
  • Page 199 8.32 CON36 Register Name MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version G.5 BitFlow, Inc. NEO-8-101...
  • Page 200 CON36 Register The Neon MEM_ADDR_LO R/W, CON25[15..0], Neon This register is the lower 16 bits used to access the flash or ROM memory on boards that have it. This is not a user programmable register. NEO-8-102 BitFlow, Inc. Version G.5...
  • Page 201 8.33 CON37 Register Name MEM_ADDR_HI MEM_ADDR_HI MEM_ADDR_HI MEM_ADDR_HI MEM_CS MEM_WRITE DWNLD_MODE DWNLD_MODE MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version G.5 BitFlow, Inc. NEO-8-103...
  • Page 202 R/W, CON37[7..6], Alta, Neon Future use. MEM_DATA R/W, CON37[15..8], Neon This bitfield provides data access used when reading or writing the flash or ROM on boards that support these features. This is not a user programmable register. NEO-8-104 BitFlow, Inc. Version G.5...
  • Page 203 8.34 CON38 Register Name POCL_POWER_ON POCL_EN_GND POCL_CLOCK_WAIT Reserved POCL_SENSE POCL_CLK_ DETECTED POCL_DETECTED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version G.5 BitFlow, Inc. NEO-8-105...
  • Page 204 PoCL state machine is watching the imped- ance on the CL cable. If the impedance of a PoCL camera is detected, the power will be applied. It a short is detected, indicating a legacy camera/cable has been con- NEO-8-106 BitFlow, Inc. Version G.5...
  • Page 205 This register indicates that the PoCL state machine has detected a PoCL camera.. POCL_DETECTED Meaning The PoCL state machine has not detected a PoCL- camera. The PoCL state machine has detected a PoCL cam- era. Version G.5 BitFlow, Inc. NEO-8-107...
  • Page 206 8.35 CON40 Register Name AFE_PORT_ADDR AFE_PORT_ADDR AFE_PORT_ADDR AFE_PORT_ADDR AFE_PORT_ADDR AFE_PORT_ADDR AFE_PORT_ADDR AFE_PORT_ADDR AFE_PORT_WRITE AFE_PORT_ACCESS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved NEO-8-108 BitFlow, Inc. Version G.5...
  • Page 207 The next access operation will be a read. The next access operation will be a write. AFE_PORT_ WO, CON40[9], Alta ACCESS Writing a 1 to the bit causes the AFE to be accessed. The type of operation depends on the AFE_PORT_WRITE bit. Version G.5 BitFlow, Inc. NEO-8-109...
  • Page 208 8.36 CON41 Register Name AFE_PORT_DATA AFE_PORT_DATA AFE_PORT_DATA AFE_PORT_DATA AFE_PORT_DATA AFE_PORT_DATA AFE_PORT_DATA AFE_PORT_DATA AFE_PORT_BUSY AFE_PORT_ERROR AFE_PORT_RESET Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved NEO-8-110 BitFlow, Inc. Version G.5...
  • Page 209 RO, CON41[9], Alta ERROR A 1 in this bit indicates that an error occurred during the last AFE access operation. AFE_PORT_ WO, CON41[10], Alta RESET Writing a 1 to the bit resets the AFE access mechanism. Version G.5 BitFlow, Inc. NEO-8-111...
  • Page 210 CON42 Register The Neon 8.37 CON42 Register Name FIRST_FI RD_WEN Reserved RD_HD RD_VD SWAP_LINES FI_POL ACQ_IV FEN_SEL FEN_SEL FEN_SEL HD_SEL HD_SEL HD_SEL VD_SEL VD_SEL VD_SEL GEN_IV Reserved ENDIAN Reserved Reserved Reserved Reserved Reserved Reserved Reserved NEO-8-112 BitFlow, Inc. Version G.5...

  • Page 211: First_Fi

    The WEN input is currently high RD_HD R/W, CON42[4], Alta This bit indicates the current status of the of the horizontal sync (HD) I/O signal. RD_HD Meaning The HD input is currently low The HD input is currently high Version G.5 BitFlow, Inc. NEO-8-113...

  • Page 212: Rd_Vd

    Used to swap the polarity of the field index signal, needed for some interlaced cam- eras. FI_POL Meaning Normal polarity Invert polarity R/W, CON42[9..8], Alta This bits dictates which field from an interlaced camera initiates acquisition. Meaning The odd field starts acquisition The even field starts acquisition. NEO-8-114 BitFlow, Inc. Version G.5...

  • Page 213: Acqiv

    1 (001b) HD is an output, source is this VFG”s Video Genera- 2 (010b) HD is an output, source is the master VFG”s Video Generator 3 (011b) HD is an output, source the the CC3 signal Version G.5 BitFlow, Inc. NEO-8-115...

  • Page 214: Hd_Sel

    This bitfield is used to comminicate between multiple VFGs on the same board. What ever value is written to this register can be read from all the other VFGs. This register does not control anything. NEO-8-116 BitFlow, Inc. Version G.5...

  • Page 215: Endian

    Camera Control Registers CON42 Register ENDIAN R/W, CON42[24], Alta This bit is used to select the endianness of the video output. ENDIAN Meaning Little endian, Intel mode Big endian, motorola mode Version G.5 BitFlow, Inc. NEO-8-117...
  • Page 216 8.38 CON43 Register Name GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_PERIOD GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW GEN_H_LOW NEO-8-118 BitFlow, Inc. Version G.5...
  • Page 217 Camera Control Registers CON43 Register GEN_H_PERIOD R/W, CON43[15..0], Alta Horizontal period of Video Generator. GEN_H_LOW R/W, CON43[15..0], Alta Horizontal low period of Video Generator. Version G.5 BitFlow, Inc. NEO-8-119...
  • Page 218 8.39 CON44 Register Name GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_PERIOD GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW GEN_V_LOW NEO-8-120 BitFlow, Inc. Version G.5...
  • Page 219 Camera Control Registers CON44 Register GEN_V_PERIOD R/W, CON43[15..0], Alta Vertical period of Video Generator. GEN_V_LOW R/W, CON43[15..0], Alta Vertical low period of Video Generator. Version G.5 BitFlow, Inc. NEO-8-121...
  • Page 220 8.40 CON51 Register Name QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_PHASEA QENC_PHASEB QENC_DIR QENC_INTRVL_IN QENC_NEW_LINES Reserved Reserved Reserved NEO-8-122 BitFlow, Inc. Version G.5...
  • Page 221 System is not inside the interval. Encoder counter is not between QENC_INTRVL_LL and QENC_INTRVL_ UL. Lines are not being acquired. System is inside the interval. Encoder counter is between QENC_INTRVL_LL and QENC_INTRVL_UL. Lines are being acquired. Version G.5 BitFlow, Inc. NEO-8-123...
  • Page 222 QENC_NEW_LINES Meaning The system is traversing lines that have already been visited. If QENC_NO_REAQ = 1, lines are not being acquired. The system is traversing new lines. Lines are being acquired. NEO-8-124 BitFlow, Inc. Version G.5...
  • Page 223 PLDA DMA engine. This includes the Alta, the Karbon and the Neon families. This chapter also covers the scatter gather DMA instructions (Quads or QTabs). The for- matting of the register sections is explained in Section 8.2. Version G.5 BitFlow, Inc. NEO-9-1...
  • Page 224 9.2 CON28 Register Name FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO NEO-9-2 BitFlow, Inc. Version G.5...
  • Page 225 This is the low word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. This register can be written at any time, but the DMA engine only loads this value when byte count (as set by CHAIN_DATA_SIZE_LO/CHAIN_ DATA_SIZE_HI) goes to zero. Version G.5 BitFlow, Inc. NEO-9-3...
  • Page 226 9.3 CON29 Register Name FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI NEO-9-4 BitFlow, Inc. Version G.5...
  • Page 227 This is the high word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. This register can be written at any time, but the DMA engine only loads this value when byte count (as set by CHAIN_DATA_SIZE_LO/CHAIN_ DATA_SIZE_HI) goes to zero. Version G.5 BitFlow, Inc. NEO-9-5...
  • Page 228 9.4 CON30 Register Name CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO CHAIN_DATA_SIZE_LO NEO-9-6 BitFlow, Inc. Version G.5...
  • Page 229 DMA transfer. When the count reached zero, this value in this register is reloaded into the DMA engine, and the first scatter gather instruction pointed to by FIRST_QUAD_PTR_HI and FIRST_QUAD_PTR_LO is loaded. Version G.5 BitFlow, Inc. NEO-9-7...
  • Page 230 9.5 CON31 Register Name CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI CHAIN_DATA_SIZE_HI NEO-9-8 BitFlow, Inc. Version G.5...
  • Page 231 DMA engine when DMA is initiated. This value is then decremented every DMA transfer. When the count reached zero, this value in this register is reloaded into the DMA engine, and the first scatter gather instruction pointed to by FIRST_QUAD_PTR_HI and FIRST_QUAD_PTR_LO is loaded. Version G.5 BitFlow, Inc. NEO-9-9...
  • Page 232 9.6 CON32 Register Name CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO CHAIN_DATA_TOGO_LO NEO-9-10 BitFlow, Inc. Version G.5...
  • Page 233 Karbon/Neon/Alta DMA CON32 Register CHAIN_DATA_ RO, CON32[31..0], Alta, Karbon-CL, Karbon-CXP, Neon TOGO_LO This register indicates the low word of the 64-bit number of bytes remaining the DMA chain. Version G.5 BitFlow, Inc. NEO-9-11...
  • Page 234 9.7 CON33 Register Name CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI CHAIN_DATA_TOGO_HI NEO-9-12 BitFlow, Inc. Version G.5...
  • Page 235 Karbon/Neon/Alta DMA CON33 Register CHAIN_DATA_ RO, CON33[31..0], Alta, Karbon-CL, Karbon-CXP, Neon TOGO_HI This register indicates the high word of the 64-bit number of bytes remaining the DMA chain. Version G.5 BitFlow, Inc. NEO-9-13...
  • Page 236 9.8 CON34 Register Name DMA_AUTO_START DMA_ABORT DMA_DIRECTION DMA_DONE DMA_STATUS DMA_STATUS DMA_STATUS DMA_STATUS DMA_NO_RULE Reserved Reserved Reserved Reserved Reserved Reserved Reserved DMA_INIT_FUNC DMA_PRIORITY DMA_64_BIT DMA_CHAINING DMA_COMMAND DMA_COMMAND DMA_COMMAND DMA_COMMAND DMA_BEN DMA_BEN DMA_BEN DMA_BEN LATCH_CONTROL LATCH_CONTROL Reserved Reserved NEO-9-14 BitFlow, Inc. Version G.5...
  • Page 237 The actual data that is DMAed will be unpredictable. This bit, therefore, is only useful for diagnostics. DMA_INIT_ R/W, CON34[16], Alta, Karbon-CL, Karbon-CXP, Neon FUNC Future use. Version G.5 BitFlow, Inc. NEO-9-15...
  • Page 238 R/W, CON34[23..20], Alta, Karbon-CL, Karbon-CXP, Neon COMMAND Controls the DMA engine. DMA_COMMAND Meaning 0000b to 1110b Reserved 1111b Normal DMA operation DMA_BEN R/W, CON34[27..24], Alta, Karbon-CL, Karbon-CXP, Neon Future use. LATCH_ R/W, CON34[29..28], Alta, Karbon-CL, Karbon-CXP, Neon CONTROL Future use. NEO-9-16 BitFlow, Inc. Version G.5...
  • Page 239 9.9 CON35 Register Name XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT Version G.5 BitFlow, Inc. NEO-9-17...
  • Page 240 CON35 Register The Neon XFR_PER_INT R/W, CON35[31..0], Alta, Karbon-CL, Karbon-CXP, Neon This register controls how often the board issues an EOF interrupt. Every time XFR_ PER_INT bytes have been DMAed, the board will emit an interrupt. NEO-9-18 BitFlow, Inc. Version G.5...
  • Page 241 A list of instructions are called a Quad Table or QTAB. Each quad con- sists of the following entries. 1. Destination address 2. Size of transfer 3. Next quad address. The following sections document the structure of these quads. Version G.5 BitFlow, Inc. NEO-9-19...
  • Page 242 Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address NEO-9-20 BitFlow, Inc. Version G.5...
  • Page 243 Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Version G.5 BitFlow, Inc. NEO-9-21...
  • Page 244 Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address NEO-9-22 BitFlow, Inc. Version G.5...
  • Page 245 Register and Memory Mapping Introduction Register and Memory Mapping Chapter 10 10.1 Introduction This section explains how the registers and the various chunks of memory are mapped and accessed on the Alta/Karbon/Neon and their virtual frame grabbers. Version G.5 BitFlow, Inc. NEO-10-1...
  • Page 246 256 locations are actually populated. This reason this works is that the RLE CTabs can compress the normal CTabs by a very large amount, considerably reduce that memory requirements for CTabs. NEO-10-2 BitFlow, Inc. Version G.5...
  • Page 247 CON35 00 00 00 88 DMA Register CON36 00 80 00 18 Alta/Neon Only CON37 00 80 00 20 Alta/Neon Only CON38 00 80 00 28 Neon Only CON40 00 00 00 98 Alta Only Version G.5 BitFlow, Inc. NEO-10-3...
  • Page 248 The following pertains to the table above. All registers are treated as 64 bits wide. Two BARs are allocated for PCI access. BAR0, is not currently used. BAR1, memory mapped, 16M size, is used for access to registers, CTABs, DPM. NEO-10-4 BitFlow, Inc. Version G.5...
  • Page 249 The mechanism for downloading is similar to the Neon, how- ever the power up FLASH memory is updated from the host using a special program (FWDownload). Contact BitFlow customer support for more information. Version G.5 BitFlow, Inc.
  • Page 250 Each family of boards has its own device ID as follows: Alta - 0x5000 Karbon - 0x3000 Neon - 0x4000 Information about different models and board capabilities is stored in the INFO_HI and INFO_LO registers. NEO-10-6 BitFlow, Inc. Version G.5...
  • Page 251 This chapter describes the electrical interface of the Karbon/Neon/R64. This includes detailed information on the all if the input and output signals. In addition, information is provided on recommend circuits to use when connecting to these signals. Version G.5 BitFlow, Inc. NEO-11-1...
  • Page 252 The LED is driven by an open collector driver. The user must supply his +5V power to the LED. Note that there is no galvanic connection between the user’s circuit and the acquisition circuitry. NEO-11-2 BitFlow, Inc. Version G.5...
  • Page 253 Electrical Interfacing Trigger TRIGGER_OPTO_A TRIGGER_OPTO Opto Coupler SFH6325 7407 TRIGGER_OPTO_K User Circuit Frame Grabber Figure 11-1 Driver Circuit for Opto-Coupled Trigger Version G.5 BitFlow, Inc. NEO-11-3...
  • Page 254 The LED is driven by an open collector driver. The user must supply his +5V power to the LED. Note that there is no galvanic connection between the user’s circuit and the acquisition circuitry. NEO-11-4 BitFlow, Inc. Version G.5...
  • Page 255 Electrical Interfacing Encoder ENCODER_OPTO_A ENCODER_OPTO Opto Coupler SFH6325 7407 ENCODER_OPTO_K User Circuit Frame Grabber Figure 11-2 Driver Circuit for Opto-Coupled Encoder Version G.5 BitFlow, Inc. NEO-11-5...
  • Page 256 GPIN pin, there is an associated GPIN register. See the pin-out in the mechanical chapter to determine the actual pins each signal resides on. Each frame grabber family has a slightly different arrangement of GPIN signals, please see Chapter 13 for details. NEO-11-6 BitFlow, Inc. Version G.5...
  • Page 257 (see Figure 11-4). Jumpers are used to configure the driver circuits. See the Mechanical chapter on where and how the jumpers are used. Version G.5 BitFlow, Inc. NEO-11-7...
  • Page 258 The user must supply the +5V to this LED and the two systems must have their grounds connected. In this configuration the board and the user’s system must have a common electrical ground. NEO-11-8 BitFlow, Inc. Version G.5...
  • Page 259 The open collector driver will sink the current from the LED. There is no gal- vanic connection between the board and the user’s circuit. Information is passed from the board to the user as light, transmitted by the LED and received by the photo-tran- sistor. Version G.5 BitFlow, Inc. NEO-11-9...
  • Page 260 3 (011b) Free running on board signal generator. Controlled by FREE_RUN_RATE and FREE_ RUN_HIGH 4 (100b) Internally generated clock. Frequency set by CFREQ. 5 (101b) GPIN0’s signal level 6 (110b) Forced low 7 (111b) Forced high NEO-11-10 BitFlow, Inc. Version G.5...

  • Page 261: Specifications

    Minimum clocks between lines Clocks Minimum lines between frames Lines Minimum pixel clocks between frames Clocks Minimum trigger pulse Nanoseconds Minimum encoder pulse Nanoseconds NEO-PCE-CLB Current (3.3V) Amps NEO-PCE-CLB Current (12V) 0.075 Amps Section 12.4 NEO-PCE-CLD Current (3.3V) Amps NEO-PCE-CLD Current (12V) 0.075 Amps Section 12.4...
  • Page 262 Introduction The Neon Table 12-1 Neon Specifications Specifications Value Units Details Mechanical dimensions 6.8 x 4.2 Inches Mechanical dimensions 17.4 x 10.67 Centimeters Minimum UART baud rate Bits/Second Maximum UART baud rate 230K Bits/Second NEO-12-2 BitFlow, Inc. Version G.5...
  • Page 263 A two tap camera that supplies odd/even pixels, Max_pix_per_line = 512K. An RGB camera that supplies RGB over 24 bits, Max_pix_per_line = 256K, as every clock the camera supplies one single pixel. A four tap, two segments, each left right, Max_pix_per_line = 1M Version G.5 BitFlow, Inc. NEO-12-3...
  • Page 264 Line_taps is the number of taps that supply a whole line. Examples: A one tap camera, Max_lines_per_frame = 128K. A two tap camera that supplies odd/even lines, Max_lines_per_frame = 256K. A two tap camera that supplies odd/even pixels, Max_lines_per_frame = 128K. NEO-12-4 BitFlow, Inc. Version G.5...

  • Page 265: Power Consumption

    CLB could draw with a PoCL camera attached is 0.575 Amps on the 12 V rail, and the maximum for the NEO-PCE-CLD/NEO-PCE-CLM is 1.075 Amps on the 12 V rail. Finally the NEO-PCE-CLQ can draw up to 2.075 Amps on the 12 V rail. Version G.5 BitFlow, Inc. NEO-12-5...
  • Page 266 Power Consumption The Neon NEO-12-6 BitFlow, Inc. Version G.5...
  • Page 267 P3, 16 Pin Header (internal) Header (internal) The NEO-PCE-CLB has two revisions. From a software point of view the revisions are the same. However, the revision two laminate includes switches the permit use selec- tion of the available I/O signaled on the external P10 connector. The following sec- tions describe the two revisions.
  • Page 268 The NEO-PCE-CLB Revision 1 The Neon 13.2 The NEO-PCE-CLB Revision 1 The mechanical layout of the NEO-PCE-CLB revision 1 is shown in Figure 13-1. S1.1 S1.2 Jumper Set 1 PCI Express x4 Connector Figure 13-1 NEO-PCE-CLB Revision 1 Layout The revision 1 NEO-PCE-CLB is available with two different I/O configuration. See Section 13.11 and Section 13.12 for detailed information on the different pin outs of...
  • Page 269 The revision 2 version of the NEO-PCE-CLB board only comes in one configuration. However, all of the alternate signals that were available with the alternate version of the revision 1 NEO-PCE-CLB are still available via the use of the switches S2 to S7. Version G.5 BitFlow, Inc.
  • Page 270 The NEO-PCE-CLD The Neon 13.4 The NEO-PCE-CLD The mechanical layout of the NEO-PCE-CLD are shown in Figure 13-3. S1.1 S1.2 Denotes Pin 1 Jumper Set 1 PCI Express x4 Connector Figure 13-3 The NEO-PCE-CLD Layout NEO-13-4 BitFlow, Inc. Version G.5...
  • Page 271 The flex cable allows the fourth connector to be located on either side of the main board, and can be up to three slots away from the main board. The fourth con- nectors is shown in Figure 13-5. Version G.5 BitFlow, Inc. NEO-13-5...
  • Page 272 The NEO-PCE-CLQ The Neon Flex Cable Connector Figure 13-5 NEO-PCE-CLQ CL4 Connector NEO-13-6 BitFlow, Inc. Version G.5...
  • Page 273 Mechanical The NEO-PCE-DIF 13.6 The NEO-PCE-DIF The mechanical layout of the NEO-PCE-DIF Figure 13-6. S1.1 S1.2 PCI Express x4 Connector Figure 13-6 NEO-PCE-DIF Layout Version G.5 BitFlow, Inc. NEO-13-7...
  • Page 274 Camera 4 13.7.2 The I/O Connectors The I/O connector, P10 on NEO-PCE-CLB and P1 on the NEO-PCE-CLD, NEO-PCE- CLQ and P2 on the NEO-PCE-CDIF contain a number of general purpose inputs and outputs. The outputs can be used, for example, to control a strobe light or other NEO-13-8 BitFlow, Inc.
  • Page 275 Some of the inputs have specific functions, for example the Trigger and Encoder, and some are general purpose, for example GPIN0, whose state can be read by software. These signals are described in detail in the following sections. Version G.5 BitFlow, Inc. NEO-13-9...
  • Page 276 Power disconnected GPOUT6_VCC to GPOUT6_VCC from GPOUT6_VCC through a 220 Ohm through a 680 Ohm (factory default) resistor resistor 1K pull-up resistor N.A. No pull-up on installed between GPOUT6 GPOUT6_OC and GPOUT6_VCC (fac- tory default) NEO-13-10 BitFlow, Inc. Version G.5...
  • Page 277 GPOUT6_VCC GPOUT6_OC 13.9.3 Switches S3 and S6, NEO-PCE-CLB Revision 2 Only The switches S3 and S6 are used to control the type of signals that are present on the Pins 2 and 10 o f P10 connector. These settings are illustrates in Table 13-6.
  • Page 278 Switches The Neon 13.9.4 Switches S4 and S7, NEO-PCE-CLB Revision 2 Only The switches S4 and S7 are used to control the type of signals that are present on the Pins 1 and 9 o f P10 connector. These settings are illustrates in Table 13-7.
  • Page 279 It is important to understand that some of these signals are the output of a high speed serial converter chip, and require special instrumentation to be observed. Version G.5 BitFlow, Inc. NEO-13-13...
  • Page 280 13.11 NEO-PCE-CLB Revision 1 I/O Connector, Standard Configuration (P10) The standard pin-out for the I/O Connector (P10) is illustrated in the Table 13-9. Note: The connector P10 is only on the NEO-PCE-CLB Revision 1 model Neon. Table 13-9 P10 I/O Connector, Standard Configuration Signal...
  • Page 281 The alternate pin-out for the I/O Connector (P10) is illustrated in the Table 13-10. Note: The connector P10 is only on the NEO-PCE-CLB Revision 1 model Neon. Note: The alternate configuration I/O is only available as a special ordering option from BitFlow.
  • Page 282 However, certain of the signals can be changed via the switches S2 to S7. See Section 13.9 for more information on these switches. Note: The connector P10 is only on the NEO-PCE-CLB Revision 2 model Neon. Table 13-11 P10 I/O Connector, NEO-PCE-CLB Revision 2...
  • Page 283 LVDS VFG0_TRIGGER_OPTO_A Anode of optocoupling sensor VFG0_TRIGGER_OPTO_K Cathode of optocoupling sensor VFG1_TRIGGER_OPTO_A Anode of optocoupling sensor VFG1_TRIGGER_OPTO_K Cathode of optocoupling sensor VFG0_GPOUT5_OC Open collector driver VFG0_GPOUT5_VCC Pull-up or power for the open col- lector driver Version G.5 BitFlow, Inc. NEO-13-17...
  • Page 284 Table 13-12 P1 I/O Connector Signal Comment VFG1_GPOUT5_OC Open collector driver VFG1_GPOUT5_VCC Pull-up or power for the open col- lector driver VFG0_TRIGGER_TTL VFG0_ENCODERA_TTL VFG0_ENCODERB_TTL TTL, also VFG0_GPIN1_TTL VFG1_ENCODERB_TTL TTL, also VFG1_GPIN1_TTL VFG1_TRIGGER_TTL VFG1_ENCODERA_TTL VFG0_GPOUT2_TTL VFG0_GPOUT3_TTL VFG1_GPOUT2_TTL VFG1_GPOUT3_TTL NEO-13-18 BitFlow, Inc. Version G.5...
  • Page 285 Table 13-13 P3 I/O Connector Signal Comment VFG0_TRIGGER+ LVDS VFG0_TRIGGER- LVDS VFG0_TRIGGER_TTL VFG0_ENCODERA_TTL VFG0_GPOUT0_TTL VFG0_GPOUT1_TTL VFG1_TRIGGER+ LVDS VFG1_TRIGGER- LVDS VFG1_TRIGGER_TTL VFG1_ENCODERA_TTL VFG1_GPOUT0_TTL VFG1_GPOUT1_TTL VFG2_TRIGGER+ LVDS VFG2_TRIGGER- LVDS VFG2_TRIGGER_TTL VFG2_ENCODERA_TTL VFG2_GPOUT0_TTL VFG2_GPOUT1_TTL VFG3_TRIGGER+ LVDS VFG3_TRIGGER- LVDS VFG3_TRIGGER_TTL VFG3_ENCODERA_TTL VFG3_GPOUT0_TTL VFG3_GPOUT1_TTL Version G.5 BitFlow, Inc. NEO-13-19...
  • Page 286 LVDS, also VFG2_GPIN0+ VFG2_ENCODERB- LVDS, also VFG2_GPIN0- VFG2_GPOUT0+ LVDS VFG2_GPOUT0- LVDS VFG2_ENCODERB_TTL TTL, also VFG2_GPIN1_TTL VFG3_ENCODERA+ LVDS VFG3_ENCODERA- LVDS VFG3_ENCODERB+ LVDS, also VFG3_GPIN0+ VFG3_ENCODERB- LVDS, also VFG3_GPIN0- VFG3_GPOUT0+ LVDS VFG3_GPOUT0- LVDS VFG3_ENCODERB_TTL TTL, also VFG3_GPIN1_TTL NEO-13-20 BitFlow, Inc. Version G.5...
  • Page 287 Mechanical NEO-PCE-CLQ I/O Connector Pinout (P3) Table 13-13 P3 I/O Connector Signal Comment VFG0_GPOUT2_TTL VFG1_GPOUT2_TTL VFG2_GPOUT2_TTL VFG3_GPOUT2_TTL Version G.5 BitFlow, Inc. NEO-13-21...
  • Page 288 LVDS DIG11- LVDS Serial Receive+ LVDS Serial Receive- LVDS DIG12+ LVDS DIG12- LVDS DIG13+ LVDS DIG13- LVDS DIG14+ LVDS DIG14- LVDS DIG15+ LVDS DIG15- LVDS CLKOUT+ LVDS/RS422 (see CLK_OUT_ LEVEL) CLKOUT- LVDS/RS422 (see CLK_OUT_ LEVEL) NEO-13-22 BitFlow, Inc. Version G.5...
  • Page 289 RS422 GPOUT1+ RS422 GPOUT1- RS422 GPOUT2+ RS422 GPOUT2- RS422 DIG4+ LVDS DIG4- LVDS DIG5+ LVDS DIG5- LVDS DIG6+ LVDS DIG6- LVDS DIG7+ LVDS DIG7- LVDS TRIGGER+ LVDS TRIGGER- LVDS Serial Transmit+ RS422 Serial Transmit- RS422 Version G.5 BitFlow, Inc. NEO-13-23...
  • Page 290 NEO-PCE-DIF Main Connector Pinout (P7) The Neon Table 13-14 Neon-DIF Main Connector (Data and I/O) Signal Comment CT0+ RS422 CT0- RS422 LEN+ LVDS LEN- LVDS FEN+ LVDS FEN- LVDS NEO-13-24 BitFlow, Inc. Version G.5...
  • Page 291 LVDS DIG27+ LVDS DIG26- LVDS DIG26+ LVDS DIG25- LVDS DIG25+ LVDS DIG24- LVDS DIG24+ LVDS DIG23- LVDS DIG23+ LVDS DIG22- LVDS DIG22+ LVDS DIG21- LVDS DIG21+ LVDS DIG20- LVDS DIG20+ LVDS DIG19- LVDS DIG19+ LVDS Version G.5 BitFlow, Inc. NEO-13-25...
  • Page 292 NEO-PCE-DIF Auxiliary Connector Pinout (P2) The Neon Table 13-15 Neon-DIF Auxiliary Connector (Data) Signal Comment DIG18- LVDS DIG18+ LVDS DIG17- LVDS DIG17+ LVDS DIG16- LVDS DIG16+ LVDS NEO-13-26 BitFlow, Inc. Version G.5...
  • Page 293 Note: The connector P3 is only on the NEO-PCE-DIF model. Table 13-16 Neon-I/O Auxiliary Connector Signal Comment GPIN2+/ENCODER_B+ LVDS GPIN2-/ENCODER_B- LVDS TRIGGER_TTL ENCODER_A_TTL GPOUT3_TTL GPIN0_TTL/ENCODER_B_TTL CC4_TTL CC4+ LVDS CC4- LVDS TRIGGER+ LVDS TRIGGER- LVDS ENCODER_A+ LVDS ENCODER_A- LVDS GPIN1_TTL GPOUT4_TTL Version G.5 BitFlow, Inc. NEO-13-27...
  • Page 294 NEO-PCE-DIF I/O Connector Pinout (P3) The Neon NEO-13-28 BitFlow, Inc. Version G.5...
  • Page 295 CON33 NEO-9-12 CON34 NEO-9-14 CC4_CON NEO-8-19 CFGCLOCK NEO-8-5 CON35 NEO-9-17 CFGDATA NEO-8-5 CON36 NEO-8-101 CFGDONE NEO-8-5 CON37 NEO-8-103 CFGEN NEO-8-5 CON38 NEO-8-105 CFGSTATUS NEO-8-5 CON4 NEO-8-24 CFREQ NEO-8-6 CON40 NEO-8-108 CHAIN_DATA_SIZE_HI NEO-9-9 CON41 NEO-8-110 CHAIN_DATA_SIZE_LO NEO-9-7 CON42 NEO-8-112 BitFlow, Inc.
  • Page 296 ENC_DIV NEO-8-38 GEN_IV NEO-8-116 ENC_DIV_FCLK_SEL NEO-8-72 GEN_ONESHOT NEO-8-40 ENC_DIV_FORCE_DC NEO-8-71 GEN_V_PERIOD NEO-8-121 ENC_DIV_M NEO-8-38 General Purpose Inputs (GPIN) NEO-11-6 ENC_DIV_N NEO-8-78 General Purpose Outputs (GPOUT) NEO-11-7 ENC_DIV_OPEN_LOOP NEO-8-72 GPIN0 NEO-8-23 Encoder NEO-11-4 GPIN1 NEO-8-23 Encoder Divider NEO-5-1 GPIN2 NEO-8-23 BitFlow, Inc.
  • Page 297 GPOUT5_CON NEO-8-45 MEM_WRITE NEO-8-104 GPOUT6 NEO-8-27 MID NEO-8-116 GPOUT6_CON NEO-8-46 MUX_REV NEO-8-49 GREEN_GAIN NEO-8-83 NEO-PCE-CLB Revision 1 I/O Connector, Alter- HAW_START NEO-8-30 nate Configuration (P10) NEO-13-15 HCNT_LD NEO-8-16 NEO-PCE-CLB Revision 1 I/O Connector, Stan- HCNT_RLS_STK NEO-8-17 dard Configuration (P10) NEO-13-14...
  • Page 298 QENC_REAQ_MODE NEO-4-11, NEO-8-71 SWAP NEO-8-64 QENC_RESET NEO-4-9, NEO-8-69 SWAP_LINES NEO-8-114 QENC_RESET_REAQ NEO-4-11, NEO-8-71 Switches NEO-13-11 QTAB NEO-9-19 QTBSRC NEO-8-20 Quad Table NEO-9-19 TAG_BANK NEO-8-40 TOP_REV NEO-8-76 TRIG_QUALIFIED NEO-8-38 R/W NEO-8-3 Trigger NEO-11-2 RD_ENC_DIFF NEO-8-34, NEO-8-35 TRIGGER_DELAY NEO-8-34 RD_ENC_OPTO NEO-8-34 BitFlow, Inc.
  • Page 299 TRIGPOL NEO-8-32 TRIM NEO-8-49 UART_MASTER NEO-8-57 VAW_START NEO-8-30 VCNT_LD NEO-8-10 VCNT_RLS_STK NEO-8-10 VCNT_RLS_ZERO NEO-8-9 VCNT_RST NEO-8-9 VCOUNT NEO-8-38 VD_SEL NEO-8-116 Vertical Control Table Size NEO-2-15 VFG NEO-1-10 VID_BRL NEO-8-80 VID_SOURCE NEO-8-54 VIDEO_2DPM NEO-8-80 VIDEO_MASK NEO-8-61 WO NEO-8-3 XFR_PER_INT NEO-9-18 BitFlow, Inc.
  • Page 300 Index BitFlow, Inc.

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