Cirrus Logic CS8420 Manual

Digital audio sample rate converter

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Digital Audio Sample Rate Converter

Features

Complete IEC60958, AES3, S/PDIF, EIAJ

CP1201-compatible Transceiver with

Asynchronous Sample Rate Converter

Flexible 3-wire Serial Digital I/O Ports

8-kHz to 108-kHz Sample Rate Range

1:3 and 3:1 Maximum Input to Output Sample

Rate Ratio

128 dB Dynamic Range

-117 dB THD+N at 1 kHz

Excellent Performance at Almost a 1:1 Ratio

Excellent Clock Jitter Rejection

24-bit I/O Words

Pin and Microcontroller Read/Write Access to

Channel Status and User Data

Microcontroller and Stand-Alone Modes

VA+ AGND FILT

ILRCK

Serial

ISCLK

Audio

SDIN

Input

RXP

Receiver

RXN

Misc.

Control

H/S

RST

http://www.cirrus.com

RERR

RMCK

Clock &

AES3

Data

S/PDIF

Recovery

Decoder

EMPH U TCBL SDA/

CDOUT

General Description

The CS8420 is a stereo digital audio sample rate con-

verter (SRC) with AES3-type and serial digital audio

inputs, AES3-type and serial digital audio outputs, and

includes comprehensive control ability via a 4-wire mi-

crocontroller port. Channel status and user data can be

assembled

read/modify/write cycles easy.

Digital audio inputs and outputs may be 24, 20, or 16

bits. The input data can be completely asynchronous to

the output data, with the output data being synchronous

to an external system clock.

The CS8420 is available in a 28-pin SOIC package in

both Commercial (-10º to +70º C) and Automotive

grades (-40º to +85º C). The CDB8420 Customer Dem-

onstration board is also available for device evaluation

and implementation suggestions.

Please refer to

dering information.

Target applications include CD-R, DAT, MD, DVD and

VTR equipment, mixing consoles, digital audio trans-

mission

equipment,

converters, effects processors, and computer audio

systems.

Sample

Rate

Converter

C & U bit

Data

Buffer

Control

Port &

Registers

SCL/

AD1/

AD0/

CCLK

CDIN

CS8420

block-sized

buffers,

"Ordering Information" on page 93

high-quality

VD+ DGND

Serial

Audio

Output

AES3

Driver

S/PDIF

Encoder

Output

Clock

Generator

INT

OMCK

making

for or-

D/A

and

A/D

OLRCK

OSCLK

SDOUT

TXP

TXN

APRIL '07

DS245F4

Table of Contents

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Summary of Contents for Cirrus Logic CS8420

Page 1 CS8420 Digital Audio Sample Rate Converter Features General Description The CS8420 is a stereo digital audio sample rate con- Complete IEC60958, AES3, S/PDIF, EIAJ verter (SRC) with AES3-type and serial digital audio CP1201-compatible Transceiver with inputs, AES3-type and serial digital audio outputs, and...
Page 2: Characteristics And Specifications
CS8420 CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25°C. SPECIFIED OPERATING CONDITIONS AGND, DGND = 0 V, all voltages with respect to 0 V.
Page 3: Performance Specifications
CS8420 PERFORMANCE SPECIFICATIONS Parameter* Symbol Units Dynamic Range Input Sample Rate (serial input port) Output Sample Rate Output to Input Sample Rate Ratio 0.33 Total Harmonic Distortion + Noise THD+N 1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 1.7 -117 1 kHz, -1 dBFS, 0.33 <...
Page 4: Digital Input Characteristics
CS8420 DIGITAL INPUT CHARACTERISTICS Parameters Symbol Units μA Input Leakage Current ±10 ±15 Differential Input Voltage, RXP to RXN mVpp DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. Parameters Symbol Units High-Level Output Voltage (I = -3.2 mA), except TXP/TXN...
Page 5: Switching Characteristics - Serial Audio Ports
CS8420 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS Inputs: Logic 0 = 0 V, Logic 1 = VD+; C = 20 pF. Parameter Symbol Units OSCLK Active Edge to SDOUT Output Valid (Note 7) SDIN Setup Time Before ISCLK Active Edge...
Page 6: Switching Characteristics - Control Port - Spi™ Mode
CS8420 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE Inputs: Logic 0 = 0 V, Logic 1 = VD+; C = 20 pF. Parameter Symbol Units CCLK Clock Frequency (Note 13) μs CS High Time Between Transmissions CS Falling to CCLK Edge...
Page 7 CS8420 ® SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE Inputs: Logic 0 = 0 V, Logic 1 = VD+; C = 20 pF. Parameter Symbol Units SCL Clock Frequency fscl μs Bus Free Time Between Transmissions μs Start Condition Hold Time (prior to first clock pulse) hdst μs...
Page 8: Typical Connection Diagram
CS8420 TYPICAL CONNECTION DIAGRAM Ferrite * Bead Analog μ Digital 0.1 F Supply * Supply μ 0.1 F AES3/ AES3/ Cable Cable SPDIF SPDIF Termination Interface Source Equipment CS8420 ILRCK OLRCK 3-wire Serial 3-wire Serial Audio Input ISCLK OSCLK Audio Source...
Page 9: General Description
On the input side of the CS8420, AES3 or 3-wire serial format can be chosen. The output side produces both AES3 and 3-wire serial format. An I²C/SPI-compatible microcontroller interface allows full block processing of channel sta- tus and user data via block reads from the incoming AES3 data stream and block writes to the outgoing AES3 data stream.
Page 10: Data I/O Flow And Clocking Options
CS8420 DATA I/O FLOW AND CLOCKING OPTIONS The CS8420 can be configured for nine connectivity alternatives, referred to as data flows. Each data flow has an associated clocking set-up. Figure 6 shows the data flow switching, along with the control register bits which control the switches.
Page 11 By studying the following drawings, and appropriately setting the Data Flow Control and Clock Source Control reg- ister bits, the CS8420 can be configured to fit a variety of application requirements. The following drawings illustrate the possible valid data flows. The audio data flow is indicated by the thin lines; the clock routing is indicated by the bold lines.
Page 12 CS8420 Serial OLRCK Serial OLRCK Audio Audio OSCLK OSCLK Output Output SDOUT SDOUT SDIN SDIN Serial Sample Serial Sample ISCLK ISCLK Audio Rate Audio Rate ILRCK Input Converter ILRCK Input Converter AES3 AES3 Encoder Encoder & Driver & Driver RMCK...
Page 13 CS8420 SDOUT OSCLK OLRCK SDIN ISCLK ILRCK Serial Serial Audio Audio AES3 Serial OLRCK Output Input Rx & Audio OSCLK Decode Output SDOUT AES3 AES3 Rx & Encoder Decode & Driver RMCK RMCK Data Flow Control Bits Clock Source Control Bits...
Page 14: Sample Rate Converter (Src)
When using the AES3 input, and when using the serial audio input port in Left-Justified and I²S modes, all input data is treated as 24 bits wide. Any truncation that has been done prior to the CS8420 to less than 24 bits should have been done using an appropriate dither process.
Page 15: Three-Wire Serial Audio Ports
The clocking of the input section of the CS8420 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. The PLL operation is described in the AES receiver description on page 22.
Page 16 CS8420 ILRCK Channel A Channel B Left Justified ISCLK (In) SDIN ILRCK Channel A Channel B I²S ISCLK (In) SDIN ILRCK Channel A Channel B Right Justified ISCLK (In) SDIN SIMS SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL Left-Justified I²S Right-Justified X = don’t care to match format, but does need to be set to the desired setting...
Page 17 CS8420 OLRCK Channel A Channel B Left Justified OSCLK (Out) SDOUT OLRCK Channel A Channel B I²S OSCLK (Out) SDOUT OLRCK Channel A Channel B Right Justified OSCLK (Out) SDOUT MSB Extended MSB Extended OLRCK Channel A Channel B Channel A...
Page 18: Aes3 Transmitter And Receiver
CS8420 AES3 TRANSMITTER AND RECEIVER The CS8420 includes an AES3-type digital audio receiver and an AES3-type digital audio transmitter. A compre- hensive buffering scheme provides read/write access to the channel status and user data. This buffering scheme is described in “Channel Status and User Data Buffer Management”...
Page 19 CS8420 7.1.4 Channel Status Data Handling The first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register. The setting of the CHS bit in the Channel Status Data Buffer Control register determines whether the channel status decodes are from the A channel (CHS = 0) or B channel (CHS = 1).
Page 20 MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8420 AES3 receiver can detect such non-audio data. This is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync code is detected, an internal AUTODETECT signal will be asserted.
Page 21 (RST = low), when no AES3 transmit clock is provided, and option- ally under the control of a register bit. The CS8420 also allows immediate mute of the AES3 transmitter audio data via a control register bit.
Page 22 CS8420 TCBL In or Out VLRCK Tsetup Thold VCU[0] VCU[1] VCU[2] VCU[3] VCU[4] Input SDIN Data [4] Data [5] Data [6] Data [7] Data [8] Input TXP(N) Data [0] Data [1] Data [2] Data [3] Data [4] AES3 Transmitter in Stereo Mode Tsetup = >...
Page 23 CS8420 RECEIVER TRANSMITTER STEREO MODE STEREO MODE 96kHz 96kHz 96kHz stereo 96kHz stereo 96kHz frame rate 96kHz frame rate AES3 AES3 Receiver Transmitter 256x96kHz OMCK (256, 384, or 512x 96kHz) RECEIVER TRANSMITTER MONO MODE MONO MODE 96kHz 96kHz 96kHz mono...
Page 24: Sample Rate Converter
To start the parts simultaneously, set up each one so that the PLL will lock, with the active input port driving both output ports. Then simultaneously enable the RUN bits in all of the parts. TCBL on one of the CS8420 parts should be set as an output, while the remaining TCBL pins should be set as inputs.
Page 25 CS8420 Non-SRC Delay The unit of delay depends on the frame rate (sample rate) F . The AES receiver has a interface delay of two frames. The AES transmitter, the serial input port, and the serial output port each have an interface delay of 1 frame.
Page 26: Control Port Description And Timing
The control port has two modes: SPI and I²C, with the CS8420 acting as a slave device. SPI mode is selected if there is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. I²C mode is selected by connecting the AD0/CS pin to VD+ or DGND, thereby permanently selecting the desired AD0 bit address state.
Page 27 VD+ or DGND as desired. The EMPH pin is used to set the AD2 bit, by connecting a resistor from the EMPH pin to VD+ or to DGND. The state of the pin is sensed while the CS8420 is being reset. The upper four bits of the 7-bit address field are fixed at 0010b.
Page 28: Control Port Register Bit Definitions
56 to 126 - Reserved 127 - Chip ID and version register Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8420. DS245F4...
Page 29 CS8420 Addr Function (HEX) Control 1 SWCLK VSET MUTESAO MUTEAES DITH INT1 INT0 TCBLD Control 2 TRUNC HOLD1 HOLD0 RMCKF MMTCS MMTLR Data Flow Control AMLL TXOFF AESBP TXD1 TXD0 SPD1 SPD0 SRCD Clock Source Control CLK1 CLK0 OUTC RXD1...
Page 30 CS8420 10.2 Miscellaneous Control 1 (01h) SWCLK VSET MUTESAO MUTEAES DITH INT1 INT0 TCBLD SWCLK Causes OMCK to be output through the RMCK pin when the PLL is unlocked 0 - RMCK is driven by the PLL VCO (default) 1 - OMCK is switched to output through the RMCK pin when the PLL is unlocked. Circuitry driv- en by the PLL is driven by OMCK.
Page 31 CS8420 10.3 Miscellaneous Control 2 (02h) TRUNC HOLD1 HOLD0 RMCKF MMTCS MMTLR TRUNC Determines whether the word length is set according to the incoming Channel Status data 0 - Data to the SRC is not truncated (default) 1 - Data to the SRC is set according to the AUX field in the incoming data stream...
Page 32 CS8420 10.4 Data Flow Control (03h) AMLL TXOFF AESBP TXD1 TXD0 SPD1 SPD0 SRCD The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audio Input Port, Serial Audio Output Port, AES3 receiver, AES3 transmitter, and Sample Rate Converter.
Page 33 U and C data buffers is not possible. Power consumption is low (default). 1 - Normal part operation. This bit must be written to the 1 state to allow the CS8420 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1.
Page 34 CS8420 10.6 Serial Audio Input Port Data Format (05h) SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL SIMS Master/Slave Mode Selector 0 - Serial audio input port is in Slave mode (default) 1 - Serial audio input port is in Master mode...
Page 35 CS8420 10.7 Serial Audio Output Port Data Format (06h) SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL SOMS Master/Slave Mode Selector 0 - Serial audio output port is in Slave mode (default) 1 - Serial audio output port is in Master mode...
Page 36 OVRGL Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale. OVRGR Over-range indicator for right (B) channel SRC output. Occurs on internal over-range for right channel data.
Page 37 CS8420 10.9 Interrupt Register 2 Status (08h) (Read Only) VFIFO REUNLOCK DETU EFTU UOVW For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A”0” means the associated interrupt condition has NOT occurred since the last reading of the register.
Page 38 CS8420 10.12 Interrupt 2 Register Mask (0Ch) VFIFOM REUNLOCKM DETUM EFTUM QCHM UOVWM The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the status register.
Page 39 CS8420 10.14 Receiver Channel Status (0Fh) (Read Only) AUX3 AUX2 AUX1 AUX0 AUDIO COPY ORIG The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control Regis- ter.
Page 40 CS8420 10.15 Receiver Error (10h) (Read Only) QCRC CCRC UNLOCK CONF This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still true.
Page 41 CS8420 10.16 Receiver Error Mask (11h) QCRCM CCRCM UNLOCKM CONFM BIPM PARM The bits in this register serve as masks for the corresponding bits of the Receiver Error Regis- ter. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit.
Page 42 CS8420 10.18 User Data Buffer Control (13h) UBM1 UBM0 DETUI EFTUI User data pin (U) direction specifier 0 - The U pin is an input. The U data is latched in on both rising and falling edges of OLRCK. This setting also chooses the U pin as the source for transmitted U data (default).
Page 43 10.20 C-Bit or U-Bit Data Buffer (20h - 37h) Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is ac- cessible via these register addresses. 10.21 CS8420 I.D. and Version Register (7Fh) (Read Only) VER3 VER2...
Page 44: System And Applications Issues
The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8420 by connecting a 47 kΩ resistor between the pin and either VD+ (High) or DGND (Low).
Page 45 SRC Invalid State Occasionally the CS8420 SRC will enter an invalid state. This can happen after the RUN bit has been set when an AES3 stream is first plugged into the part or when a source device interrupts the SRC input stream.
Page 46 ID Code and Revision Code The CS8420 has a register that contains a 4-bit code to indicate that the addressed device is a CS8420. This is useful when other CS84xx family members are resident in the same system, allowing common soft- ware modules.
Page 47: Software Mode - Pin Description
CS8420 12. SOFTWARE MODE - PIN DESCRIPTION The above diagram and the following pin descriptions apply to Software mode. In Hardware mode, some pins change their function as described in subsequent sections of this data sheet. Fixed function pins are marked with a *, and will be described once in this section.
Page 48 RST - Reset Input * When RST is low, the CS8420 enters a low-power mode and all internal states are reset. On initial power-up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in Hardware mode with multiple CS8420 devices, where synchronization between devices is impor- tant.
Page 49 AD0/CS - Address Bit 0 (I²C) / Control Port Chip Select (SPI) A falling edge on this pin puts the CS8420 into SPI Control Port mode. With no falling edge, the CS8420 defaults to I²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8420.
Page 50 CS8420 Miscellaneous Pins: U - User Data The U pin may optionally be used to input User data for transmission by the AES3 transmitter (see Figure 20 timing information). Alternatively, the U pin may be set to output User data from the AES3 receiver (see Figure 19 for timing information).
Page 51: Hardware Modes
The CS8420 has six Hardware modes, which allow use of the device without using a micro-controller to ac- cess the device control registers and CS & U data. The flexibility of the CS8420 is necessarily limited in Hardware mode. Various pins change function in Hardware mode, and various data paths are also possible.
Page 52 CS8420 13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input) Hardware Mode 1 data flow is shown in Figure 24. Audio data is input via the AES3 receiver, and rate con- verted. The audio data at the new rate is then output both via the serial audio output port and via the AES3 transmitter.
Page 53 CS8420 13.2.1 Pin Description - Hardware Mode 1 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, as shown in Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to ground in Hardware mode 1 in order to select the AES3 input.
Page 54 Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input. TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state.
Page 55 CS8420 13.3 Hardware Mode 2 Description (DEFAULT Data Flow, Serial Input) Hardware Mode 2 data flow is shown in Figure 25. Audio data is input via the serial audio input port, and rate converted. The audio data at the new rate is then output both via the serial audio output port and via the AES3 transmitter.
Page 56 CS8420 COPY/C ORIG/U Function PRO=0, COPY=0, L=0 PRO=0, COPY=0, L=1 PRO=0, COPY=1, L=0 PRO=1 Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function SFMT1 SFMT0 Function Serial Input & Output Format IF1&OF1 Serial Input & Output Format IF2&OF2 Serial Input & Output Format IF3&OF3 Serial Input &...
Page 57 CS8420 13.3.1 Pin Description - Hardware Mode 2 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to VD+ in Hardware mode 2, in order to select the serial audio input.
Page 58 Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times.
Page 59 CS8420 13.4 Hardware Mode 3 Description (Transceive Data Flow, with SRC) Hardware Mode 3 data flow is shown in Figure 26. Audio data is input via the AES3 receiver, and rate con- verted. The audio data at the new rate is then output via the serial audio output port. Different audio data, synchronous to OMCK, may be input into the serial audio input port, and output via the AES3 transmitter.
Page 60 CS8420 SDOUT RMCK RERR ORIG COPY Function Serial Output Port is Slave Serial Output Port is Master Mode 3A: C transmitted data is copied from received data, U & V =0, received PRO, EMPH, AUDIO is visible Mode 3B: CUV transmitted data is input serially on pins, received PRO, EMPH and AUDIO is not visible Serial Input &...
Page 61 CS8420 13.4.1 Pin Description - Hardware Mode 3 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table OMCK - Output Section Master Clock Input Output section master clock input.
Page 62 Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times.
Page 63 CS8420 13.5 Hardware Mode 4 Description (Transceive Data Flow, No SRC) Hardware mode 4 data flow is shown in Figure 27. Audio data is input via the AES3 receiver, and routed to the serial audio output port. Different audio data synchronous to RMCK may be input into the serial audio input port, and output via the AES3 transmitter.
Page 64 CS8420 SDOUT RMCK RERR ORIG COPY Function Serial Output Port is Slave Serial Output Port is Master Mode 4A: C transmitted data is copied from received data, U & V =0, received PRO, EMPH, AUDIO is visible Mode 4B: CUV transmitted data is input serially on pins, received PRO, EMPH and AUDIO is not visible Serial Input &...
Page 65 CS8420 13.5.1 Pin Description - Hardware Mode 4 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin.
Page 66 Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times.
Page 67 CS8420 13.6 Hardware Mode 5 Description (AES3 Receiver Only) Hardware Mode 5 data flow is shown in Figure 28. Audio data is input via the AES3 receiver, and routed to the serial audio output port. The PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on pins.
Page 68 CS8420 13.6.1 Pin Description - Hardware Mode 5 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table S/AES - Serial Audio or AES3 Input Select S/AES is connected to DGND in Hardware mode 5, in order to select the AES3 input.
Page 69 CS8420 AES3/SPDIF Receiver Interface: RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).
Page 70 CS8420 13.7 Hardware Mode 6 Description (AES3 Transmitter Only) Hardware Mode 6 data flow is shown in Figure 29. Audio data is input via the serial audio input port and routed to the AES3 transmitter. The transmitted channel status, user, and validity data may be input in two alternative methods, determined by the state of the CEN pin.
Page 71 CS8420 COPY/C ORIG Function PRO=0, COPY=0, L=0 PRO=0, COPY=0, L=1 PRO=0, COPY=1, L=0 PRO=1 Table 15. HW 6 COPY/C and ORIG Pin Function SFMT1 SFMT0 Function Serial Input Format IF1 Serial Input Format IF2 Serial Input Format IF3 Serial Input Format IF4 Table 16.
Page 72 CS8420 13.7.1 Pin Description - Hardware Mode 6 COPY/C ORIG DFC0 DFC1 EMPH SFMT0 SFMT1 AGND DGND FILT OMCK S/AES APMS AUDIO TCBLD ILRCK ISCLK SDIN TCBL * Pins which remain the same function in all modes. Overall Device Control:...
Page 73 AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times.
Page 74 14.1 AES3 Transmitter External Components The output drivers on the CS8420 are designed to drive both the professional and consumer interfaces. The AES3 specification for professional/broadcast use calls for a 110 Ω source impedance and a balanced drive capability. Since the transmitter output impedance is very low, a 110 Ω resistor should be placed in series with one of the transmit pins.
Page 75 14.2 AES3 Receiver External Components The CS8420 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig- ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with 110 Ω ±20% impedance. The XLR connector on the receiver should have female pins with a male shell. Since the receiver has a very high input impedance, a 110 Ω...
Page 76 μ 0.01 F Figure 35. Consumer Input Circuit The circuit shown in Figure 36 may be used when external RS422 receivers, optical receivers or other TTL/CMOS logic outputs drive the CS8420 receiver section. TTL/CMOS CS8420 μ Gate 0.01 F μ...
Page 77: Channel Status And User Data Buffer Management
AES3 Channel Status(C) Bit Management The CS8420 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these RAMs via the control port.
Page 78 If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calcu- lated by the CS8420, and does not have to be written into the last byte of the block by the host microcon- troller.
Page 79 In this case, the user would have to superimpose his settings on the E buffer after every D-to-E overwrite. To avoid this problem, the CS8420 has the capability of reserving the first 5 bytes of the E buffer for user writes only.
Page 80 E buffer. In this mode, a read will cause the CS8420 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8420's control port.
Page 81 CS8420 transmitted bit. The first byte read is the first byte received, and the first byte sent is the first byte trans- mitted. 15.2.3 IEC60958 Recommended U Data Format for Consumer Applications Modes (3) and (4) are intended for use in AES3 in, AES3 out situations, in which the input U data is for- matted as recommended in the “IEC60958 Digital Audio Interface, part 3: Consumer applications”...
Page 82 Example 2: Fsi/Fso = 1, N=4, IF=7: min proper padding is 9 bits. The CS8420 detects when an overwrite has occurred in the FIFO, and synchronously resets the entire FIFO structure to prevent corrupted U data from being merged into the transmitted AES3 data stream.
Page 83: Pll Filter
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 41 is a simplified diagram of the PLL in CS8420 devices. When the PLL is locked to an AES3 input stream, it is updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, F .
Page 84 CS8420 16.2.2 Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit.
Page 85 Also note that many factors can affect jitter performance in a system. Please follow the circuit and layout recommendations outlined previously. 16.3.3 Locking to the ILRCK Input CS8420 parts that are configured to lock to the ILRCK input should use the external PLL component val- ues listed in Table 20.
Page 86 Shown in Figure 43 is the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4 specification. CS8420 parts used with the appropriate external PLL component values (as noted in Table 19) have been tested to pass this template.
Page 87: Parameter Definitions
CS8420 17. PARAMETER DEFINITIONS Input Sample Rate (Fsi) The sample rate of the incoming digital audio. Input Frame Rate The frame rate of the received AES3 format data. Output Sample Rate (Fso) The sample rate of the outgoing digital audio.
Page 88: Package Dimensions
CS8420 18. PACKAGE DIMENSIONS 28L SOIC (300 MIL BODY) PACKAGE DRAWING ∝ SEATING PLANE INCHES MILLIMETERS 0.093 0.104 2.35 2.65 0.004 0.012 0.10 0.30 0.013 0.020 0.33 0.51 0.009 0.013 0.23 0.32 0.697 0.713 17.70 18.10 0.291 0.299 7.40 7.60 0.040...
Page 89: Ordering Information
19. ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order# Rail CS8420-CS Commercial -10º to +70ºC Tape and Reel CS8420-CSR Rail CS8420-CSZ Digital Audio Sample CS8420 28-SOIC Commercial -10º to +70ºC Rate Converter Tape and Reel CS8420-CSZR Rail CS8420-DSZ Automotive -40º...

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