Philips 70DCC600 Service Manual page 13

Signal name Signal flow Function Explanation
Signal name Signal flow Function Explanation
INO Head ~ read amp data lines Head signals of main data channels 0-7 LT-Bus ).lP~DAI LT-interface is used for the system control of the digital
IN1 ).lP ~ ADAS panel. The LT-interface consists of clock-, data-, control-
IN2 ).lP ~ DEQ and enable lines.
IN3 ).lP
~
DDSP
IN4
IN5 LTC-Bus ADAS ~ SBC LTC-interface is mainly used for transfer of allocation
IN6 LTCLKC information from ADAS to SBC. (Encoding mode) The
IN7 LTCNTOC LTC-interface consists of c1ock-, data-, control- and enable
LTCNT1C lines.
INAUX
Head ~ read amp data line Head signal of auxiliary data.
LTDATAC
LTSBC
INHERCO DDSP
~
ERCO
inhibit ERCO Control line output of DDSP to inhibit the ERCO for
LTCLK ).lP~DAI LT-c1ock Bit clock line for the LT-interface. Main microprocessor
settings transfer. These settings determine whether the
).lP ~ ADAS supplies the bit clock and acts as master whilst the other
ERCO should encode or decode (see also SETINH).
).lP
~
DEQ devices perform as slaves.
).lP
~
DDSP
INL Head
~ read amp analog data line Analog input signals from DCC head
LTCLKC
LTC-clock
Bit clock line for the LTC-interface. Main microprocessor
INMFL read amp
~ feedback line Magnetic feedback amplifier input left supplies the bit clock and acts as master whilst the other
devices perform as slaves.
INMFR read amp
~ feedback line Magnetic feedback amplifier input right
LTCNTO
).lP~
DAI LT control lines Control lines of the LT-interface output from main
LTCNT1 ).lP
~
ADAS
microprocessor. LTCNTn determine the type of transfer to
INR Head ~ read amp analog data line Analog input signals from DCC head ).lP ~ DEQ occur across the LTDATA serial data line tolfrom micropro-
).lP ~ DDSP cessor.
INTL DAC ~ L-ch integrator left Analog output of the DAC (ou1puts from the left positive LTDATA ).lP~DAI LT data Bidirectional serial data line of the LT-interface fromlto
and negative switched-capacitor integrator) to the left ).lP ~ADAS microprocessor. Direction of data transfer is dependant on
channel amplifier stage. ).lP ~ DEQ the information on LTCNTO and LTCNT1 .
).lP ~ DDSP
INTR DAC ~ R-ch integrator right
Analog output of the DAC (outputs from the right positive
and negative switched-capacitor integrator) to the right
LTEN ).lP ~ ADAS LTenable ADAS Activates the LT-interface of the ADAS in case LTENA =1.
channel amplifier stage. LT-ADAS
IOSC1 ERCO <- SBC input oscillator Oscillator input for ERCO coming from the sub-band coder LTEN ).lP~ DAI LTenable DAI Activates the LT-interface of the DAI in case LTEN (on
SBMCLK output. The nominal frequency is 6.144 MHz.
LT-DAI DAI) =1.
See also SBMCLK.
LTEN ).lP
~
DDSP LTenable DDSP Activates the LT-interface of the DDSP in case LTEN (on
IRQU DAI
~).lP information request Control line to indicate the main microprocessor infor-
LT-DDSP DDSP) =1.
microprocessor mation can be read.
LTENDEQ ).lP
~
DEQ LTenable DEQ Activates the LT-interface of the DEQ in case LTENDEQ
1
2
S-bus inter IC sound
3-line serial bus consisting of a line for two time-multip- •
LT-DEQ =1 .
lexed audio data channels, a word select line for indication
of the channel being transmitted (left or right) and a clock
MAG Main ).lP
~
solenoid control line Low output pulse switches the solenoid.
line. The lines are called SD, WS and SCK. The device
control circuit
which generates the SCK and WS is the master. See also
SCK, SWS and SDA. MCLK DDSP ~ ERCO master clock MCLK line of the DDSP provides the 6.144 MHz master
clock signal and is connected to the MCLK input of the
L-IN Relay 1307 ~ ADC signal line Analog signal input left channel for ADC from recording ERCO. This clock (128 x Fs) is used for the symbols
amplifier or dolby IC selected by relay 1307. transfer between DDSP and ERCO.
L-OUT DAC ~ line out amp signal line Analog signal output left channel of DAC. MFL1 read amp <- head feedback amplifier output left
MFL2
LABEL DEQ~ ).lP label Search mode label detection output of DEQ signals that a
label is found in the AUX-channel. When DCC player is in MFR1 read amp <- head feedback amplifier output right
search mode, the tape speed increases. LABEL infor- MFR2
mation is encoded throughout its length. To examine the
length of a label, the tape speed must be known. In search MODEO DAI <- gnd mode selection Control lines from to select the operation mode of the DAI.
mode DEQ assesses the speed of labelled tapes. The MODE1 input DAI operates in ).lP mode when both lines are at '0' level.
microprocessor obtains this information via the LT-inter-
face. MPCL DDSP
~
ERCO clock phase The MPCL output of the DDSP provides the 3.072 MHz
reference (64 x Fs) clock phase reference signal which is connected
LEVEL Main ).lP ~ silence control line Control signal to adapt the silence detection circuit to the to the MPCL input of the ERCO.
detection
tape speed. (High speed during search, Normal speed in
Rec mode.)
MSBF DAI
~
+5V control line 1 = Most Significant Bit First
o
= Least Significant Bit First
UR ADC <-
UR clock input Word clock input for the ADC
MSTCK DAI ..... 256Fs master clock Bidirectional master clock line. Dependant on CKSEL
LRCKPOL DAI
~
gnd control line
polarity of LRCK selection
settings the master clock is at 128Fs or 256Fs. See also
CS45918
18 19
CS45919