Page 1 TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide Literature Number: SPRU041C July 2003...
Page 2 TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...
Page 3: Read This First
Preface Read This First About This Manual This document describes the multichannel audio serial port (McASP) in the digital signal processors (DSPs) of the TMS320C6000t DSP family. The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications.
Page 4 Related Documentation From Texas Instruments Related Documentation From Texas Instruments / Trademarks Related Documentation From Texas Instruments The following documents describe the C6000 devices and related support tools. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
Page 5 Contents Contents Overview ............... . Provides an overview of the multichannel audio serial port (McASP).
Page 6 Contents Operation ............... Discusses the operation of the McASP.
Page 7 Contents 4.1.4 Pin Direction Register (PDIR) ........4-11 4.1.5 Pin Data Output Register (PDOUT)
Page 8 Figures Figures McASP as Digital Audio Decoder ..........McASP as Digital Audio Encoder .
Page 9 Figures Pin Direction Register (PDIR) ..........4-11 Pin Data Output Register (PDOUT) .
Page 10 Tables Tables Biphase-Mark Encoder ............1-17 Biphase-Mark Encoder .
Page 11 Tables 4-28 Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions ....4-53 4-29 Transmit Bit Stream Format Register (XFMT) Field Descriptions ....4-54 4-30 Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions...
Page 12 Chapter 1 Overview This chapter provides an overview of the multichannel audio serial port (McASP) in the digital signal processors (DSPs) of the TMS320C6000t DSP family. Included are the features of the McASP, protocols the McASP supports, and definitions of terms used within this document. The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications.
Page 13 Features 1.1 Features Features of the McASP include: Two independent clock generator modules for transmit and receive Clocking flexibility allows the McASP to receive and transmit at differ- ent rates. For example, the McASP can receive data at 48 kHz but out- put up-sampled data at 96 kHz or 192 kHz.
Page 14: Overview
Protocols Supported 1.2 Protocols Supported The McASP supports a wide variety of protocols. Transmit section supports Wide variety of I2S and similar bit-stream formats TDM streams from 2 to 32 time slots S/PDIF, IEC60958–1, AES-3 formats Receive section supports Wide variety of I2S and similar bit-stream formats TDM streams from 2 to 32 time slots TDM stream of 384 time slots specifically designed for easy interface to external digital interface receiver (DIR) device transmitting DIR...
Page 15: System Level Connections
System Level Connections Protocols Supported / System Level Connections On C6000 DSPS in I2S mode, the transmit and receive sections can support simultaneous transfers on up to all serial data pins operating as 192 kHz stereo channels. On C6000 DSPS in DIT mode, the transmitter can support a 192 kHz frame rate (stereo) on up to all serial data pins simultaneously (note that the internal bit clock for DIT runs two times faster than the equivalent bit clock for I2S mode, due to the need to generate Biphase Mark Encoded Data).
Page 16 System Level Connections Figure 1–1.McASP as Digital Audio Decoder (Continued) (b) McASP to 6-Channel DAC and 2-Channel DAC player Coaxial/ optical C6000 DSP S/PDIF encoded Stereo McASP 6-ch 2-ch (c) McASP to Digital Amplifier player Stereo I2S Digital Coaxial/ generator optical C6000 DSP S/PDIF...
Page 17: Mcasp As Digital Audio Encoder
System Level Connections Figure 1–2. McASP as Digital Audio Encoder Stereo I2S C6000 DSP LF, RF 2-ch ADC McASP C, LFE S/PDIF 2-ch ADC encoded LS, RS 2-ch ADC Figure 1–3. McASP as 16 Channel Digital Processor 2-ch ADC 2-ch ADC 2-ch ADC C6000 DSP 2-ch ADC...
Page 18: Considerations When Using A Mcasp
Considerations When Using a McASP 1.4 Considerations When Using a McASP The following is a list of things to be considered for systems using a McASP: 1.4.1 Clocks For each receive and transmit section: External or internal generated bit clock and high frequency clock? If internally generated, what is the bit clock speed and the high frequency clock speed? Clock polarity?
Page 19: Definition Of Terms
Definition of Terms 1.5 Definition of Terms The serial bit stream transmitted or received by the McASP is a long sequence of 1s and 0s, either output or input on one of the audio transmit/receive pins (AXR[n]). However, the sequence has a hierarchical organization that can be described in terms of frames of data, slots, words, and bits.
Page 20: Definition Of Bit, Word, And Slot
Definition of Terms Figure 1–4. Definition of Bit, Word, and Slot ACLK b7 b6 b5 b4 b3 b2 b1 b0 AXR[n] word slot Notes: 1) b7:b0 – bits. Bits b7 to b0 form a word 2) P – pad bits. Bits b7 to b0, together with the four pad bits, form a slot. 3) In this example, the data is transmitted MSB first, left aligned.
Page 21: Bit Order And Word Alignment Within A Slot Examples
Definition of Terms Figure 1–5. Bit Order and Word Alignment Within a Slot Examples Time 4 5 6 7 0 1 1 1 (a) 87h as 8-bit word, 12-bit slot, left align, MSB first, pad zeros 0 1 2 3 4 6 7 8 0 0 0 0 1 0 0 0 0...
Page 22: Definition Of Frame And Frame Sync Width
Definition of Terms The third basic element of a synchronous serial interface is the frame synchro- nization signal, also referred to as frame sync in this document. Frame A frame contains one or multiple slots, as determined by the desired protocol.
Page 23: Tdm Format
TDM Format Inter-Integrated Sound protocol, commonly used on audio inter- faces. The McASP supports the I2S protocol as part of the TDM mode (when configured as a 2-slot frame). Slot or For TDM format, the term time slot is interchangeable with the Time Slot term slot defined in this section.
Page 24: Tdm Format—6 Channel Tdm Example
TDM Format Figure 1–7 shows the TDM format. Figure 1–8 shows the different bit delays from the frame sync. Figure 1–7. TDM Format—6 Channel TDM Example FS † AXR[n] Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 0 Slot 1...
Page 25: Inter-Integrated Sound (I2S) Format
TDM Format 1.6.2 Inter-Integrated Sound (I2S) Format The inter-integrated sound (I2S) format is used extensively in audio interfaces. The TDM transfer mode of the McASP supports the I2S format when config- ured to 2 slots per frame. I2S format is specifically designed to transfer a stereo channel (left and right) over a single data pin AXR[n].
Page 26: S/Pdif Coding Format
S/PDIF Coding Format 1.7 S/PDIF Coding Format The McASP transmitter supports the S/PDIF format with 3.3V biphase-mark encoded output. The S/PDIF format is supported by the digital audio interface transmit (DIT) transfer mode of the McASP. This section briefly discusses the S/PDIF coding format.
Page 27: Subframe Format
S/PDIF Coding Format Table 1–1. Biphase-Mark Encoder Previous state at pin BMC-encoded cell out- Data (Unencoded) AXR[n] put at AXR[n] 1.7.2 Subframe Format Every audio sample transmitted in a subframe consists of 32 S/PDIF time inter- vals (or cells), numbered from 0 to 31. Figure 1–11 shows a subframe. Time intervals 0–3 carry one of the three permitted preambles to signify the type of audio sample in the current subframe.
Page 28: S/Pdif Subframe Format
S/PDIF Coding Format Figure 1–11.S/PDIF Subframe Format 27 28 Sync Auxiliary Audio sample word MSB V U C P preamble Validity flag User data Channel status Parity bit Table 1–2. Preamble Codes Previous Log- Logical States Preamble Code Description ical State on pin AXR[n] B (or Z) 1110 1000...
Page 29: Frame Format
S/PDIF Coding Format 1.7.3 Frame Format An S/PDIF frame is composed of two subframes (Figure 1–12). For linear coded audio applications, the rate of frame transmission normally corre- sponds exactly to the source sampling frequency f . The S/PDIF format clock rate is therefore 128 ×...
Page 30: Architecture
Chapter 2 Architecture This chapter discusses the architecture of the functional units of the McASP. Topic Page Overview ........... . . Clock and Frame Sync Generators .
Page 31: Transmit Clock
Overview 2.1 Overview Figure 2–1 shows the major blocks of the McASP. The McASP has independent receive/transmit clock generators and frame sync generators, error-checking logic, and up to 16 serial data pins. Refer to the device-specific datasheet for the number of data pins available on your device. All the McASP pins on the device may be individually programmed as general- purpose I/O (GPIO) if they are not used for serial port functions.
Page 32: Mcasp Block Diagram
Overview Figure 2–1. McASP Block Diagram Transmit format unit Serializer 0 AXR0 AXR1 Receive Serializer 1 format unit Control Serializer n AXRn Transmit state AUXCLK Transmit machine Clock generator Transmit ACLKX sequencer Frame sync generator AHCLKX Receive state AUXCLK Receive AFSX machine Clock...
Page 33 Clock and Frame Sync Generators 2.2 Clock and Frame Sync Generators The McASP clock generators are able to produce two independent clock zones: transmit and receive clock zones. The serial clock generators may be programmed independently for the transmit section and the receive section, and may be completely asynchronous to each other.
Page 34: Transmit Clock Generator Block Diagram
Clock and Frame Sync Generators The transmit clock configuration is controlled by the following registers: ACLKXCTL AHCLKXCTL Figure 2–2. Transmit Clock Generator Block Diagram XCLK (see Figure 2–3) XCLK ACLKX CLKXP (ACLKXCTL.7) (polarity) CLKXM (internal/external) (ACLKXCTL.5) Divider /1... /32 CLKXDIV AHCLKX (ACLKXCTL[4–0]) HCLKXP...
Page 35: Receive Clock Generator Block Diagram
Clock and Frame Sync Generators Figure 2–3. Receive Clock Generator Block Diagram Divider /1... /4096 AHCLKR AUXCLK HCLKRDIV (AHCLKRCTL[11–0]) Divider /1... /4096 CLKRDIV (ACLKRCTL[4–0]) HCLKRP HCLKRM (polarity) (internal/external) (AHCLKRCTL.14) (AHCLKRCTL.15) ACLKR RCLK CLKRM ASYNC (internal/external) (ACLKXCTL.6) XCLK (ACLKRCTL.5) CLKRP (from Figure 2–2) (polarity) (ACLKRCTL.7) 2.2.3...
Page 36: Clocking Examples
Clock and Frame Sync Generators Figure 2–4. Frame Sync Generator Block Diagram XCLK RCLK Transmit frame sync Receive frame sync generator generator XMOD (AFSXCTL[15–7]) RMOD (AFSRCTL[15–7]) FXWID (AFSXCTL.4) FRWID (AFSRCTL.4) FSXP (AFSXCTL.0) FSXP (AFSXCTL.0) Internal frame sync AFSX FSXM FSRP (internal/ (AFSRCTL.0) external)
Page 37: Serializers
Serializers 2.3 Serializers The serializers take care of shifting serial data in and out of the McASP. Each serializer consists of a shift register (XRSR), a data buffer (XRBUF), a control register (SRCTL), and logic to support the data alignment options of the McASP.
Page 38 Format Unit 2.4 Format Unit The McASP has two data formatting units, one for transmit and one for receive. These units automatically remap the data bits within the transmitted and re- ceived words between a natural format for the DSP (such as a Q31 representa- tion) and the required format for the external serial device (such as “I2S for- mat”).
Page 39: Receive Format Unit
Format Unit Figure 2–6. Receive Format Unit Bus (configuration bus or data port) Bit mask/pad RMASK RPBIT RPAD Programmable rotate by: RROT 0, 4, 8, 12, 16, 20, 24, 28 Bit reverse RRVRS Parallel read from XRBUF[n] Figure 2–7. Transmit Format Unit Bus (configuration bus or data port) Bit mask/pad XMASK...
Page 40 Format Unit The bit mask and pad stage includes a full 32-bit mask register, allowing se- lected individual bits to either pass through the stage unchanged, or be masked off. The bit mask and pad then pad the value of the masked off bits by inserting either a 0, a 1, or one of the original 32 bits as the pad value.
Page 41: State Machine
State Machine State Machine / TDM Sequencer / Clock Check Circuit 2.5 State Machine The receive and transmit sections have independent state machines. Each state machine controls the interactions between the various units in the re- spective section. In addition, the state machine keeps track of error conditions and serial port status.
Page 42: Pin Function Control
Pin Function Control 2.8 Pin Function Control All McASP pins except AMUTEIN are bidirectional input/output pins. In addition, these bidirectional pins function either as McASP or general-purpose I/O (GPIO) pins. The following registers control the pin functions: Pin function register (PFUNC): selects pin to function as McASP or GPIO Pin direction register (PDIR): selects pin to be input or output Pin data input register (PDIN): shows data input at the pin Pin data output register (PDOUT): data to be output at the pin if the pin is...
Page 43: Gpio Pin Control
Pin Function Control Clock inputs and serializers configured to receive must have PDIR[n] = 0. PFUNC and PDIR do not control the AMUTEIN signal, it is usually tied to a de- vice level interrupt pin (consult device datasheet). If used as a mute input, this pin needs to be configured as an input in the appropriate peripheral (GPIO).
Page 44: Mcasp I/O Pin Control Block Diagram
Pin Function Control Figure 2–8. McASP I/O Pin Control Block Diagram Disable path for McASP serializer, set to 1 when: a. Configured as transmitter PDIR[n] b. During inactive TDM slot c. DISMODE is 3-state PFUNC[n] McASP I/O pins: AXR[n] McASP serializer AHCLKR data out [n] ACLKR...
Page 45 Pin Function Control Example 2–1. General-Purpose Input Pin Because the PDIN register always reflects the state at the pin, you can read the PDIN register to obtain the pin input state. To explicitly set the pin as a gen- eral-purpose input pin, you can set the registers as follows: PDIR[n] = 0 (input) PFUNC[n] = 1 (GPIO function) Example 2–2.
Page 46: Operation
Chapter 3 Operation This chapter discusses the operation of the McASP. Topic Page Setup and Initialization ........Transfer Modes .
Page 47: Setup And Initialization
Setup and Initialization 3.1 Setup and Initialization This section discusses steps necessary to use the McASP module. 3.1.1 Transmit/Receive Section Initialization You must follow the following steps to properly configure the McASP. If external clocks are used, they should be present prior to the following initialization steps.
Page 48 Setup and Initialization 4) Start the respective serial clocks ACLKX and/or ACLKR. This step can be skipped if external serial clocks are used and they are running: a) Take the respective internal serial clock divider(s) out of reset by set- ting the RCLKRST bit for the receiver and/or the XCLKRST bit for the transmitter in GBLCTL.
Page 49 Setup and Initialization b) If CPU interrupt is used to service the McASP, interrupt service routine is entered upon the AXINT interrupt. The interrupt service routine should service the XBUF registers. Before proceeding in this step, you should verify that the XDATA bit in XSTAT is cleared to 0, indicating that all transmit buffers are already serviced by the CPU.
Page 50: Separate Transmit And Receive Initialization
Setup and Initialization 3.1.2 Separate Transmit and Receive Initialization In many cases, it is desirable to separately initialize the McASP transmitter and receiver. For example, you may delay the initialization of the transmitter until the type of data coming in on the receiver is recognized. Or a change in the incoming data stream on the receiver may necessitate a reinitialization of the transmitter.
Page 51: Synchronous Transmit And Receive Operation (Async = 0)
Setup and Initialization 3.1.4 Synchronous Transmit and Receive Operation (ASYNC = 0) When ASYNC = 0 in ACLKXCTL, the transmit and receive sections operate synchronously from the transmit section clock and transmit frame sync signals (Figure 2–2). The receive section may have a different (but compatible in terms of slot size) data format.
Page 52: Transfer Modes
Transfer Modes 3.2 Transfer Modes 3.2.1 Burst Transfer Mode The McASP supports a burst transfer mode, which is useful for nonaudio data such as passing control information between two DSPs. Burst transfer mode uses a synchronous serial format similar to the TDM mode. The frame sync generation is not periodic or time-driven as in TDM mode, but data driven, and the frame sync is generated for each data word transferred.
Page 53 Transfer Modes The control registers must be configured as follows for the burst transfer mode. The burst mode specific bit fields are in bold face: PFUNC: The clock, frame, data pins must be configured for McASP function. PDIR: The clock, frame, data pins must be configured to the direction desired. PDOUT, PDIN, PDSET, PDCLR: Not applicable.
Page 54: Time-Division Multiplexed (Tdm) Transfer Mode
Transfer Modes 3.2.2 Time-Division Multiplexed (TDM) Transfer Mode The McASP time-division multiplexed (TDM) transfer mode supports the TDM format discussed in section 1.6. Transmitting data in the TDM transfer mode requires a minimum set of pins: ACLKX– transmit bit clock AFSX–...
Page 55 Transfer Modes DITCTL: DITEN must be left at default 0 to select TDM mode. Leave the register at default. RMASK/XMASK: Mask desired bits according to sections 2.4 and 3.4. RFMT/XFMT: Program all fields according to data format desired. See section 3.4. AFSRCTL/AFSXCTL: Set RMOD/XMOD bits to 2–32 for TDM mode.
Page 56 Transfer Modes TDM Time Slots TDM mode on the McASP can extend to support multiprocessor applications, with up to 32 time slots per frame. For each of the time slots, the McASP may be configured to participate or to be inactive by configuring XTDM and/or RTDM (this allows multiple DSPs to communicate on the same TDM serial bus).
Page 57: Transmit Edma Event (Axevt) Generation In Tdm Time Slots
Transfer Modes Figure 3–2. Transmit EDMA Event (AXEVT) Generation in TDM Time Slots EDMA event EDMA event EDMA event EDMA event EDMA event for slot 0 for slot 1 for slot N – 1 for slot N for slot N + 1 EDMA event for slot N + 2 Slot 0...
Page 58: Digital Audio Interface Transmit (Dit) Transfer Mode
Transfer Modes 3.2.3 Digital Audio Interface Transmit (DIT) Transfer Mode In addition to the TDM and burst transfer modes, which are suitable for trans- mitting audio data between ICs inside the same system, the digital audio inter- face transmit (DIT) transfer mode of the McASP also supports transmission of audio data in the S/PDIF, AES-3, or IEC-60958 format.
Page 59 Transfer Modes XMASK = FFFF FF00h–FFFF 0000h (depending upon whether 24, 23, 22, 21, 20, 19, 18, 17, or 16 valid audio data bits are present) XPAD = 00 (pad extra bits with 0) For right-aligned data, the following transmit format unit settings process the data into right aligned 24-bit audio data ready for transmission: XROT = 000 (rotate right by 0 bits) XRVRS = 0 (no bit reversal, LSB first)
Page 60 Transfer Modes DLBCTL: Not applicable. Loopback is not supported for DIT mode. Leave at default. DITCTL: DITEN bit must be set to 1 to enable DIT mode. Configure other bits as desired. RMASK: Not applicable. Leave at default. RFMT: Not applicable. Leave at default. AFSRCTL: Not applicable.
Page 61 Transfer Modes DIT Channel Status and User Data Register Files The channel status registers (DITCSRAn and DITCSRBn) and user data registers (DITUDRAn and DITUDRBn) are not double buffered. Typically the programmer uses one of the synchronizing interrupts, such as last slot, to create an event at a safe time so the register may be updated.
Page 62: Channel Status And User Data For Each Dit Block
Transfer Modes Table 3–1. Channel Status and User Data for Each DIT Block Frame Subframe Preamble Channel Status defined in: User Data defined in: Defined by DITCSRA0, DITCSRB0, DITUDRA0, DITUDRB0 1 (L) DITCSRA0[0] DITUDRA0[0] 2 (R) DITCSRB0[0] DITUDRB0[0] 1 (L) DITCSRA0[1] DITUDRA0[1] 2 (R)
Page 63 Transfer Modes Table 3–1. Channel Status and User Data for Each DIT Block (Continued) Frame Subframe Preamble Channel Status defined in: User Data defined in: Defined by DITCSRA3, DITCSRB3, DITUDRA3, DITUDRB3 1 (L) DITCSRA3[0] DITUDRA3[0] 2 (R) DITCSRB3[0] DITUDRB3[0] … …...
Page 64: Data Transmission And Reception
Data Transmission and Reception 3.3 Data Transmission and Reception The DSP services the McASP by writing data to the XBUF register(s) for trans- mit operations, and by reading data from the RBUF register(s) for receive operations. The McASP sets status flag and notifies the DSP whenever data is ready to be serviced.
Page 65: Transfers Through The Data Port (Dat)
Data Transmission and Reception Receive Data Ready Similarly, the receive data ready flag RDATA bit in the RSTAT reflects the status of the RBUF register. The RDATA flag is set when data is transferred from the XRSR[n] shift registers to the XRBUF[n] buffers, indicating that the RBUF contains received data and is ready to have the DSP read the data.
Page 66: Transfers Through The Configuration Bus (Cfg)
Data Transmission and Reception When transmitting, the EDMA/CPU must write data to each serializer config- ured as “active” and “transmit” within each time slot. Failure to do so results in a buffer underrun condition (section 3.6.2). Similarly, when receiving, data must be read from each serializer configured as “active”...
Page 67: Using The Cpu For Mcasp Servicing
Data Transmission and Reception To perform internal transfers through the configuration bus, set XBUSEL/RBUSEL bit to 1 in the respective XFMT/RFMT registers. Failure to do so will result in software malfunction. 3.3.4 Using the CPU for McASP Servicing The CPU can be used to service the McASP through interrupt (upon AXINT/ ARINT interrupts) or through polling the XDATA bit in the XSTAT register.
Page 68: Edma Events In An Audio Example
Data Transmission and Reception Figure 3–3. EDMA Events in an Audio Example (a) Scenario 1: EDMA Events in an Audio Example (Two Events) Transmit AXEVT AXEVT AXEVT AXEVT AXEVT AREVT AREVT AREVT AREVT AREVT Receive AXR[4] AXR[5] AXR[6] LFE1 LFE2 (b) Scenario 2: EDMA Events in an Audio Example (Four Events) Transmit AXEVTO...
Page 69: Edma Event Triggered On Each Time Slot (Axevt/Arevt)
Data Transmission and Reception In scenario 1, an EDMA event AXEVT/AREVT is triggered on each time slot. In the example shown in Figure 3–3, AXEVT is triggered for each of the trans- mit audio channel time slot (Time slot for channels LF, LS, and C; and time slot for channels RF, RS, LFE).
Page 70: Two Alternating Edma Events Triggered For Each Time Slot
Data Transmission and Reception Each of the six events: AXEVT, AXEVTO, AXEVTE, AREVT, AREVTO, and AREVTE (for each McASP), can be configured to any EDMA channel by use of the EDMA selector control register (see the device-specific data- sheet for details). Figure 3–5.
Page 71: Audio Example Odd And Even
Data Transmission and Reception In Figure 3–3b, each transmit DMA request is for data in the next time slot, while each receive DMA request is for data in the previous time slot. For example, Figure 3–6 shows a circled AXEVTE event for an even time slot transmit DMA request.
Page 72: Formatter
Formatter 3.4 Formatter 3.4.1 Transmit Bit Stream Data Alignment The McASP transmitter supports serial formats of: Slot (or Time slot) size = 8, 12, 16, 20, 24, 28, 32 bits Word size <= Slot size Alignment: when more bits/slot than bits/words, then: Left aligned = word shifted first, remaining bits are pad Right aligned = pad bits are shifted first, word occupies the last bits in slot Order: order of bits shifted out:...
Page 73: Transmit Bitstream Data Alignment
Formatter Table 3–2. Transmit Bitstream Data Alignment XFMT Bit Bit Stream Bit Stream Bit Stream Bit Stream Internal N meric Internal Numeric † XROT XRVRS Figure 3–7 Order Alignment Representation ‡ MSB first Left aligned Q31 fraction MSB first Right aligned Q31 fraction SLOT –...
Page 74: Data Flow Through Transmit Format Unit, Illustrated
Formatter Figure 3–7. Data Flow Through Transmit Format Unit, Illustrated DSP REP: Q31 DSP REP: Integer M, M–1, P ... P M, M–1,... L XROT = 0 XROT = WORD M–1, M–1, ... L P ... P XRVRS = 1 (reverse) XRVRS = 1 (reverse) P ...
Page 75: Receive Bit Stream Data Alignment
Formatter 3.4.2 Receive Bit Stream Data Alignment The McASP receiver supports serial formats of: Slot or time slot size = 8, 12, 16, 20, 24, 28, 32 bits Word size <= Slot size Alignment when more bits/slot than bits/words, then: Left aligned = word shifted first, remaining bits are pad Right aligned = pad bits are shifted first, word occupies the last bits in slot Order of bits shifted out:...
Page 76: Receive Bitstream Data Alignment
Formatter Table 3–3. Receive Bitstream Data Alignment RFMT Bit Bit Stream Bit Stream Bit Stream Bit Stream Internal N meric Internal Numeric † RROT RRVRS Figure 3–8 Order Alignment Representation ‡ MSB first Left aligned Q31 fraction SLOT MSB first Right aligned Q31 fraction WORD...
Page 77: Data Flow Through Receive Format Unit, Illustrated
Formatter Figure 3–8. Data Flow Through Receive Format Unit, Illustrated DSP REP: Q31 DSP REP: Integer M–1, P ... P M, M–1, ... L RROT = SLOT RROT = SLOT – WORD P...P M–1, ... L P...P P...P M, M–1, ... L P...P RRVRS = 1 (reverse) RRVRS = 1 (reverse)
Page 78: Interrupts
Interrupts 3.5 Interrupts 3.5.1 Transmit Data Ready Interrupt The transmit data ready interrupt (XDATA) is generated if XDATA is 1 in the XSTAT register and XDATA is also enabled in XINTCTL. Section 3.3.1 provides details on when XDATA is set in the XSTAT register. A transmit start of frame interrupt (XSTAFRM) is triggered by the recognition of transmit frame sync.
Page 79: Audio Mute (Amute) Function
Interrupts Each interrupt source also has a corresponding enable bit in the receive inter- rupt control register (RINTCTL) and transmit interrupt control register (XINTCTL). If the enable bit is set in RINTCTL or XINTCTL, an interrupt is requested when the interrupt flag is set in RSTAT or XSTAT. If the enable bit is not set, no interrupt request is generated.
Page 80: Audio Mute (Amute) Block Diagram
Interrupts Figure 3–9. Audio Mute (AMUTE) Block Diagram INPOL bit (AMUTE.2) AMUTEIN AMUTEIN pin allows chaining of errors detected INEN (AMUTE.3) by external device ROVRN (AMUTE.5) (DIR) with ROVRN (RSTAT.0) internally detected XUNDRN (AMUTE.6) errors XUNDRN (XSTAT.0) RSYNCERR (AMUTE.7) RSYNCERR (RSTAT.1) XSYNCERR (AMUTE.8) XSYNCERR (XSTAT.1) RCKFAIL (AMUTE.9)
Page 81: Multiple Interrupts
Interrupts 3.5.5 Multiple Interrupts This only applies to interrupts and not to EDMA requests. The following terms are defined: Active Interrupt Request: a flag in RSTAT or XSTAT is set and the inter- rupt is enabled in RINTCTL or XINTCTL. Outstanding Interrupt Request: An interrupt request has been issued on one of the McASP transmit/receive interrupt ports, but that request has not yet been serviced.
Page 82: Error Handling And Management
Error Handling and Management 3.6 Error Handling and Management To support the design of a robust audio system, the McASP includes error- checking capability for the serial protocol, data underrun, and data overrun. In addition, the McASP includes a timer that continually measures the high- frequency master clock every 32 AHCLKX/AHCLKR clock cycles.
Page 83: Buffer Underrun Error - Transmitter
Error Handling and Management 2) Late: A late unexpected frame sync occurs when there is a gap or delay between the last bit of the previous frame and the first bit of the next frame. When a late unexpected frame sync occurs (as soon as the gap is detected): Error interrupt flag is set (XSYNCERR, if an unexpected transmit frame sync occurs;...
Page 84: Buffer Overrun Error - Receiver
Error Handling and Management 3.6.3 Buffer Overrun Error – Receiver A buffer overrun can only occur for serializers programmed to be receivers. A buffer overrun occurs when the serializer is instructed to transfer data from XRSR[n] to XRBUF[n], but XRBUF[n] has not yet been read by either the EDMA or the DSP.
Page 85: Clock Failure Detection
Error Handling and Management 3.6.6 Clock Failure Detection 3.6.6.1 Clock-Failure Check Startup It is expected, initially, that the clock-failure circuits will generate an error until at least one measurement has been taken. Therefore, the clock failure inter- rupts, clock switch, and mute functions should not immediately be enabled, but be enabled only after a specific startup procedure.
Page 86 Error Handling and Management 3.6.6.2 Transmit Clock Failure Check and Recovery The transmit clock failure check circuit (Figure 3–10) works off both the inter- nal McASP system clock and the external high-frequency serial clock (AHCLKX). It continually counts the number of system clocks for every 32 high rate serial clock (AHCLKX) periods, and stores the count in XCNT of the trans- mit clock check control register (XCLKCHK) every 32 high rate serial clock cycles.
Page 87: Transmit Clock Failure Detection Circuit Block Diagram
Error Handling and Management Figure 3–10. Transmit Clock Failure Detection Circuit Block Diagram External Sync to Count AHCLKX system to 32 pin input clock Clear McASP Prescale 8–bit system /1 to counter clock /256 Count XCLKCHK[3–0] Load XCLKCHK[31–24] XCNT XCLKCHK[15–8] True XCNT<XMIN? XMIN...
Page 88 Error Handling and Management The following actions are taken if a clock failure is detected: 1) Transmit clock failure flag (XCKFAIL) in XSTAT is set. This causes an interrupt if transmit clock failure interrupt enable bit (XCKFAIL) in XINTCTL is set. In addition (only supported for DIT mode), if the transmit clock failure detect autoswitch enable bit (XCKFAILSW) in XCLKCHK is set, the following addi- tional steps are taken to change the clock source from external to internal:...
Page 89: Receive Clock Failure Detection Circuit Block Diagram
Error Handling and Management The logic compares the count against a user-defined minimum allowable boundary (RMIN) and automatically flags an interrupt (RCKFAIL in RSTAT) when an out-of-range condition occurs. An out-of-range minimum condition occurs when the count is smaller than RMIN. The logic continually compares the current count (from the running system clock counter) against the maximum allowable boundary (RMAX).
Page 90: Loopback Modes
Loopback Modes 3.7 Loopback Modes The McASP features a digital loopback mode (DLB) that allows testing of the McASP code in TDM mode with a single DSP device. In loopback mode, out- put of the transmit serializers is connected internally to the input of the receive serializers.
Page 91: Loopback Mode Configurations
Loopback Modes Figure 3–12. Serializers in Loopback Mode Serializer 0 Receive Serializer 0 Transmit Serializer 1 Transmit Serializer 1 Receive Serializer 2 Receive Serializer 2 Transmit Serializer 3 Transmit Serializer 3 Receive Serializer 4 Receive Serializer 4 Transmit Serializer 5 Transmit Serializer 5 Receive...
Page 92: Registers
Chapter 4 Registers This chapter describes the registers of the McASP. Topic Page Registers ........... . .
Page 93: Registers
Registers 4.1 Registers Control registers for the McASP are summarized in Table 4–1. The control reg- isters are accessed through the configuration bus of the device. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be ac- cessed through the data port of the device, as listed in Table 4–2.
Page 94 Registers Table 4–1. McASP Registers Accessed Through Configuration Bus (Continued) Address Acronym Register Name Section Offset (hex) RINTCTL Receiver interrupt control register 007C 4.1.20 RSTAT Receiver status register 0080 4.1.21 RSLOT Current receive TDM time slot register 0084 4.1.22 RCLKCHK Receive clock check control register 0088 4.1.23...
Page 95 Registers Table 4–1. McASP Registers Accessed Through Configuration Bus (Continued) Address Acronym Register Name Section Offset (hex) DITCSRB1 Right (odd TDM time slot) channel status register (DIT mode) 1 011C 4.1.39 DITCSRB2 Right (odd TDM time slot) channel status register (DIT mode) 2 0120 4.1.39 DITCSRB3...
Page 96 Registers Table 4–1. McASP Registers Accessed Through Configuration Bus (Continued) Address Acronym Register Name Section Offset (hex) † SRCTL8 Serializer control register 8 01A0 4.1.37 † SRCTL9 Serializer control register 9 01A4 4.1.37 † SRCTL10 Serializer control register 10 01A8 4.1.37 †...
Page 97: Mcasp Registers Accessed Through Data Port
Registers Table 4–1. McASP Registers Accessed Through Configuration Bus (Continued) Address Acronym Register Name Section Offset (hex) § RBUF1 Receive buffer register for serializer 1 0284 4.1.43 § RBUF2 Receive buffer register for serializer 2 0288 4.1.43 § RBUF3 Receive buffer register for serializer 3 028C 4.1.43 §...
Page 98: Peripheral Identification Register (Pid)
Registers 4.1.1 Peripheral Identification Register (PID) The peripheral identification register (PID) is shown in Figure 4–1 and de- scribed in Table 4–3. Figure 4–1. Peripheral Identification Register (PID) [Offset 0000h] 24 23 ‡ Reserved TYPE R-0001 0000 CLASS † R-0000 0001 Legend: R = Read only;...
Page 99: Power Down And Emulation Management Register (Pwrdemu)
Registers 4.1.2 Power Down and Emulation Management Register (PWRDEMU) The power down and emulation management register (PWRDEMU) is shown in Figure 4–2 and described in Table 4–4. Figure 4–2. Power Down and Emulation Management Register (PWRDEMU) [Offset 0004h] † Reserved FREE R/W-0 Legend: R = Read only;...
Page 100: Pin Function Register (Pfunc)
Registers 4.1.3 Pin Function Register (PFUNC) The pin function register (PFUNC) specifies the function of AXR[n], ACLKX, AHCLKX, AFSX, ACLKR, AHCLKR, and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin. The PFUNC is shown in Figure 4–3 and described in Table 4–5.
Page 101: Pin Function Register (Pfunc) Field Descriptions
Registers Table 4–5. Pin Function Register (PFUNC) Field Descriptions † † field symval Value Description AFSR Determines if specified pin functions as McASP or GPIO. AHCLKR MCASP Pin functions as McASP pin. ACLKR GPIO Pin functions as GPIO pin. AFSX AHCLKX ACLKX AMUTE...
Page 102: Pin Direction Register (Pdir)
Registers 4.1.4 Pin Direction Register (PDIR) The pin direction register (PDIR) specifies the direction of AXR[n], ACLKX, AHCLKX, AFSX, ACLKR, AHCLKR, and AFSR pins as either an input or an output pin. The PDIR is shown in Figure 4–4 and described in Table 4–6. Regardless of the pin function register (PFUNC) setting, each PDIR bit must be set to 1 for the specified pin to be enabled as an output and each PDIR bit must be cleared to 0 for the specified pin to be an input.
Page 103: Pin Direction Register (Pdir) Field Descriptions
Registers Table 4–6. Pin Direction Register (PDIR) Field Descriptions † † field symval Value Description AFSR Determines if specified pin functions as an input or output. AHCLKR Pin functions as input. ACLKR Pin functions as output. AFSX AHCLKX ACLKX AMUTE 24–16 Reserved –...
Page 104: Pin Data Output Register (Pdout)
Registers 4.1.5 Pin Data Output Register (PDOUT) The pin data output register (PDOUT) holds a value for data out at all times, and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However, the data value in PDOUT is driven out onto the McASP pin only if the corresponding bit in PFUNC is set to 1 (GPIO function) and the corresponding bit in PDIR is set to 1 (output).
Page 105: Pin Data Output Register (Pdout)
Registers Figure 4–5. Pin Data Output Register (PDOUT) [Offset 0018h] † AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 † Reserved ‡ ‡ ‡ ‡ ‡ ‡ ‡ ‡ AXR15 AXR14 AXR13 AXR12 AXR11 AXR10 AXR9...
Page 106: Pin Data Output Register (Pdout) Field Descriptions
Registers Table 4–7. Pin Data Output Register (PDOUT) Field Descriptions † † field symval Value Description AFSR Determines drive on specified output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1. AHCLKR When reading data, returns the corresponding bit value in ACLKR PDOUT[n], does not return input from I/O pin.
Page 107: Pin Data Input Register (Pdin)
Registers 4.1.6 Pin Data Input Register (PDIN) The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read, regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through 31 depends on how the pins are being driven.
Page 108: Pin Data Input Register (Pdin) Field Descriptions
Registers Table 4–8. Pin Data Input Register (PDIN) Field Descriptions † † field symval Value Description AFSR Provides logic level of the specified pin. AHCLKR Pin is logic low. ACLKR Pin is logic high. AFSX AHCLKX ACLKX AMUTE 24–16 Reserved –...
Page 109: Pin Data Set Register (Pdset)
Registers 4.1.7 Pin Data Set Register (PDSET) The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic high on the pin.
Page 110: Pin Data Set Register (Pdset) Field Descriptions
Registers Table 4–9. Pin Data Set Register (PDSET) Field Descriptions † † field symval Value Description AFSR Allows the corresponding PDOUT[n] bit to be set to a logic high without affecting other I/O pins controlled by the same port. AHCLKR No effect.
Page 111: Pin Data Clear Register (Pdclr)
Registers 4.1.8 Pin Data Clear Register (PDCLR) The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and, if PFUNC = 1 (GPIO function) and PDIR = 1 (output), drives a logic low on the pin.
Page 112: Pin Data Clear Register (Pdclr) Field Descriptions
Registers Table 4–10. Pin Data Clear Register (PDCLR) Field Descriptions † † field symval Value Description AFSR Allows the corresponding PDOUT[n] bit to be cleared to a logic low without affecting other I/O pins controlled by the same port. AHCLKR No effect.
Page 113: Global Control Register (Gblctl)
Registers 4.1.9 Global Control Register (GBLCTL) The global control register (GBLCTL) provides initialization of the transmit and receive sections. The GBLCTL is shown in Figure 4–9 and described in Table 4–11. The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12–8 and ACLKR for bits 4–0).
Page 114 Registers Table 4–11. Global Control Register (GBLCTL) Field Descriptions (Continued) † † field symval Value Description XSMRST Transmit state machine reset enable bit. RESET Transmit state machine is held in reset. AXR[n] pin state: If PFUNC[n] = 0 and PDIR[n] = 1; then the serializer drives the AXR[n] pin to the state specified for inactive time slot (as deter- mined by DISMOD bits in SRCTL).
Page 115 Registers Table 4–11. Global Control Register (GBLCTL) Field Descriptions (Continued) † † field symval Value Description RFRST Receive frame sync generator reset enable bit. RESET Receive frame sync generator is reset. ACTIVE Receive frame sync generator is active. When released from reset, the receive frame sync generator begins counting serial clocks and generating frame sync as programmed.
Page 116: Audio Mute Control Register (Amute)
Registers 4.1.10 Audio Mute Control Register (AMUTE) The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin. The value after reset for register 4 depends on how the pins are being driven. The AMUTE is shown in Figure 4–10 and described in Table 4–12.
Page 117 Registers Table 4–12. Audio Mute Control Register (AMUTE) Field Descriptions (Continued) † † field symval Value Description XCKFAIL If transmit clock failure (XCKFAIL), drive AMUTE active enable bit. DISABLE Drive is disabled. Detection of transmit clock failure is ignored by AMUTE.
Page 118 Registers Table 4–12. Audio Mute Control Register (AMUTE) Field Descriptions (Continued) † † field symval Value Description ROVRN If receiver overrun error (ROVRN), drive AMUTE active enable bit. DISABLE Drive is disabled. Detection of receiver overrun error is ignored by AMUTE. ENABLE Drive is enabled (active).
Page 119: Digital Loopback Control Register (Dlbctl)
Registers 4.1.11 Digital Loopback Control Register (DLBCTL) The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode. The DLBCTL is shown in Figure 4–11 and described in Table 4–13. See section 3.7 for details on digital loopback modes.
Page 120: Dit Mode Control Register (Ditctl)
Registers 4.1.12 DIT Mode Control Register (DITCTL) The DIT mode control register (DITCTL) controls DIT operations of the McASP. The DITCTL is shown in Figure 4–12 and described in Table 4–14. Figure 4–12. DIT Mode Control Register (DITCTL) [Offset 0050h] †...
Page 121: Receiver Global Control Register (Rgblctl)
Registers 4.1.13 Receiver Global Control Register (RGBLCTL) Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4–0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the re- ceiver to be reset independently from the transmitter.
Page 122 Registers Table 4–15. Receiver Global Control Register (RGBLCTL) Field Descriptions (Continued) † † field symval Value Description XHCLKRST – Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect. XCLKRST –...
Page 123: Receive Format Unit Bit Mask Register (Rmask)
Registers 4.1.14 Receive Format Unit Bit Mask Register (RMASK The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or EDMA. The RMASK is shown in Figure 4–14 and de- scribed in Table 4–16.
Page 124: Receive Bit Stream Format Register (Rfmt)
Registers 4.1.15 Receive Bit Stream Format Register (RFMT) The receive bit stream format register (RFMT) configures the receive data for- mat. The RFMT is shown in Figure 4–15 and described in Table 4–17. See section 2.4 for a detailed description of the McASP format unit. Figure 4–15.
Page 125 Registers Table 4–17. Receive Bit Stream Format Register (RFMT) Field Descriptions (Continued) † † field symval Value Description 14–13 RPAD Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0. ZERO Pad extra bits with 0.
Page 126 Registers Table 4–17. Receive Bit Stream Format Register (RFMT) Field Descriptions (Continued) † † field symval Value Description RBUSEL Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port. Reads from XRBUF[n] originate on data port. Reads from XRBUF[n] on configuration bus are ignored.
Page 127: Receive Frame Sync Control Register (Afsrctl)
Registers 4.1.16 Receive Frame Sync Control Register (AFSRCTL) The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR). The AFSRCTL is shown in Figure 4–16 and described in Table 4–18. Figure 4–16. Receive Frame Sync Control Register (AFSRCTL) [Offset 006Ch] †...
Page 128: Receive Clock Control Register (Aclkrctl)
Registers Table 4–18. Receive Frame Sync Control Register (AFSRCTL) Field Descriptions (Continued) † † field symval Value Description FSRM Receive frame sync generation select bit. EXTERNAL Externally-generated receive frame sync INTERNAL Internally-generated receive frame sync FSRP Receive frame sync polarity select bit. ACTIVEHIGH A rising edge on receive frame sync (AFSR) indicates the beginning of a frame.
Page 129: Receive Clock Control Register (Aclkrctl) Field Descriptions
Registers Table 4–19. Receive Clock Control Register (ACLKRCTL) Field Descriptions † field symval Value Description 31–8 Reserved – Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.
Page 130: Receive High-Frequency Clock Control Register (Ahclkrctl)
Registers 4.1.18 Receive High-Frequency Clock Control Register (AHCLKRCTL) The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock gen- erator. The AHCLKRCTL is shown in Figure 4–18 and described in Table 4–20. See section 2.2.2 for details on the receive clock generator. Figure 4–18.
Page 131 Registers Table 4–20. Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions (Continued) † field symval Value Description HCLKRP Receive bitstream high-frequency clock polarity select bit. RISING Rising edge. AHCLKR is not inverted before programmable bit clock divider. In the special case where the receive bit clock (ACLKR) is internally generated and the programmable bit clock divider is set to divide-by-1 (CLKRDIV = 0 in ACLKRCTL), AHCLKR is directly passed through to the...
Page 132: Receive Tdm Time Slot Register (Rtdm)
Registers 4.1.19 Receive TDM Time Slot Register (RTDM) The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active. The RTDM is shown in Figure 4–19 and described in Table 4–21. Figure 4–19. Receive TDM Time Slot Register (RTDM) [Offset 0078h] RTDMS31 RTDMS30 RTDMS29...
Page 133: Receiver Interrupt Control Register (Rintctl)
Registers 4.1.20 Receiver Interrupt Control Register (RINTCTL) The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1, the occur- rence of the enabled McASP condition(s) generates RINT. The RINTCTL is shown in Figure 4–20 and described in Table 4–22.
Page 134 Registers Table 4–22. Receiver Interrupt Control Register (RINTCTL) Field Descriptions (Continued) † † field symval Value Description RDATA Receive data ready interrupt enable bit. DISABLE Interrupt is disabled. A receive data ready interrupt does not generate a McASP receive interrupt (RINT). ENABLE Interrupt is enabled.
Page 135: Receiver Status Register (Rstat)
Registers 4.1.21 Receiver Status Register (RSTAT) The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set.
Page 136 Registers Table 4–23. Receiver Status Register (RSTAT) Field Descriptions (Continued) † † field symval Value Description RDMAERR OF(value) Receive EDMA error flag. RDMAERR is set when the CPU or EDMA reads more serializers through the data port in a given time slot than were programmed as receivers.
Page 137 Registers Table 4–23. Receiver Status Register (RSTAT) Field Descriptions (Continued) † † field symval Value Description RCKFAIL Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error (see sec- tion 3.6.6). Causes a receive interrupt (RINT), if this bit is set and RCKFAIL in RINTCTL is set.
Page 138: Current Receive Tdm Time Slot Registers (Rslot)
Registers 4.1.22 Current Receive TDM Time Slot Registers (RSLOT) The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame. The RSLOT is shown in Figure 4–22 and de- scribed in Table 4–24. Figure 4–22.
Page 139: Receive Clock Check Control Register (Rclkchk)
Registers 4.1.23 Receive Clock Check Control Register (RCLKCHK) The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit. The RCLKCHK is shown in Figure 4–23 and de- scribed in Table 4–25. Figure 4–23. Receive Clock Check Control Register (RCLKCHK) [Offset 0088h] RCNT RMAX R/W-0...
Page 140 Registers Table 4–25. Receive Clock Check Control Register (RCLKCHK) Field Descriptions (Continued) † † field symval Value Description 7–4 Reserved – Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.
Page 141: Receiver Dma Event Control Register (Revtctl)
Registers 4.1.24 Receiver DMA Event Control Register (REVTCTL) The receiver DMA event control register (REVTCTL) contains a disable bit for the receiver DMA event. The REVTCTL is shown in Figure 4–24 and de- scribed in Table 4–26. DSP specific registers Accessing REVTCTL not implemented on a specific DSP may cause improper device operation.
Page 142: Transmitter Global Control Register (Xgblctl)
Registers 4.1.25 Transmitter Global Control Register (XGBLCTL) Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12–8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to be reset independently from the receiver.
Page 143 Registers Table 4–27. Transmitter Global Control Register (XGBLCTL) Field Descriptions (Continued) † † field symval Value Description XSRCLR Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL. CLEAR Transmit serializers are cleared. ACTIVE Transmit serializers are active.
Page 144: Transmit Format Unit Bit Mask Register (Xmask)
Registers 4.1.26 Transmit Format Unit Bit Mask Register (XMASK) The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before be- ing shifted out the McASP. The XMASK is shown in Figure 4–26 and described in Table 4–28.
Page 145: Transmit Bit Stream Format Register (Xfmt)
Registers 4.1.27 Transmit Bit Stream Format Register (XFMT) The transmit bit stream format register (XFMT) configures the transmit data format. The XFMT is shown in Figure 4–27 and described in Table 4–29. See section 2.4 for a detailed description of the McASP format unit. Figure 4–27.
Page 146 Registers Table 4–29. Transmit Bit Stream Format Register (XFMT) Field Descriptions (Continued) † † field symval Value Description 14–13 XPAD Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0. ZERO Pad extra bits with 0.
Page 147 Registers Table 4–29. Transmit Bit Stream Format Register (XFMT) Field Descriptions (Continued) † † field symval Value Description XBUSEL Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port. Writes to XRBUF[n] originate from the data port. Writes to XRBUF[n] from the configuration bus are ignored with no effect to the McASP.
Page 148: Transmit Frame Sync Control Register (Afsxctl)
Registers 4.1.28 Transmit Frame Sync Control Register (AFSXCTL) The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX). The AFSXCTL is shown in Figure 4–28 and described in Table 4–30. Figure 4–28. Transmit Frame Sync Control Register (AFSXCTL) [Offset 00ACh] †...
Page 149: Transmit Clock Control Register (Aclkxctl)
Registers Table 4–30. Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions † † field symval Value Description FXWID Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period. Single bit WORD Single word 3–2 Reserved –...
Page 150: Transmit Clock Control Register (Aclkxctl) Field Descriptions
Registers Table 4–31. Transmit Clock Control Register (ACLKXCTL) Field Descriptions † field symval Value Description 31–8 Reserved – Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.
Page 151: Transmit High-Frequency Clock Control Register (Ahclkxctl)
Registers 4.1.30 Transmit High-Frequency Clock Control Register (AHCLKXCTL) The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator. The AHCLKXCTL is shown in Figure 4–30 and described in Table 4–32. See section 2.2.1 for details on the transmit clock generator. Figure 4–30.
Page 152 Registers Table 4–32. Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions (Continued) † field symval Value Description HCLKXP Transmit bitstream high-frequency clock polarity select bit. RISING Rising edge. AHCLKX is not inverted before programmable bit clock divider. In the special case where the transmit bit clock (ACLKX) is internally generated and the programmable bit clock divider is set to divide-by-1 (CLKXDIV = 0 in ACLKXCTL), AHCLKX is directly passed through to the...
Page 153: Transmit Tdm Time Slot Register (Xtdm)
Registers 4.1.31 Transmit TDM Time Slot Register (XTDM) The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32, that is, XTDMS specifies the TDM activity for time slots 0, 32, 64, 96, 128, etc.
Page 154: Transmitter Interrupt Control Register (Xintctl)
Registers 4.1.32 Transmitter Interrupt Control Register (XINTCTL) The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occur- rence of the enabled McASP condition(s) generates XINT. The XINTCTL is shown in Figure 4–32 and described in Table 4–34.
Page 155 Registers Table 4–34. Transmitter Interrupt Control Register (XINTCTL) Field Descriptions (Continued) † † field symval Value Description XDATA Transmit data ready interrupt enable bit. DISABLE Interrupt is disabled. A transmit data ready interrupt does not generate a McASP transmit interrupt (XINT). ENABLE Interrupt is enabled.
Page 156: Transmitter Status Register (Xstat)
Registers 4.1.33 Transmitter Status Register (XSTAT) The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set.
Page 157 Registers Table 4–35. Transmitter Status Register (XSTAT) Field Descriptions (Continued) † † field symval Value Description XDMAERR OF(value) Transmit EDMA error flag. XDMAERR is set when the CPU or EDMA writes more serializers through the data port in a given time slot than were programmed as transmitters.
Page 158 Registers Table 4–35. Transmitter Status Register (XSTAT) Field Descriptions (Continued) † † field symval Value Description XCKFAIL Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error (see sec- tion 3.6.6). Causes a transmit interrupt (XINT), if this bit is set and XCKFAIL in XINTCTL is set.
Page 159: Current Transmit Tdm Time Slot Register (Xslot)
Registers 4.1.34 Current Transmit TDM Time Slot Register (XSLOT) The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame. The XSLOT is shown in Figure 4–34 and de- scribed in Table 4–36. Figure 4–34.
Page 160: Transmit Clock Check Control Register (Xclkchk)
Registers 4.1.35 Transmit Clock Check Control Register (XCLKCHK) The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit. The XCLKCHK is shown in Figure 4–35 and de- scribed in Table 4–37. Figure 4–35. Transmit Clock Check Control Register (XCLKCHK) [Offset 00C8h] XCNT XMAX R/W-0...
Page 161 Registers Table 4–37. Transmit Clock Check Control Register (XCLKCHK) Field Descriptions (Continued) † † field symval Value Description XCKFAILSW Transmit clock failure detect autoswitch enable bit. DISABLE Transmit clock failure detect autoswitch is disabled. ENABLE Transmit clock failure detect autoswitch is enabled. 6–4 Reserved –...
Page 162: Transmitter Dma Event Control Register (Xevtctl)
Registers 4.1.36 Transmitter DMA Event Control Register (XEVTCTL) The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. The XEVTCTL is shown in Figure 4–36 and de- scribed in Table 4–38. DSP specific registers Accessing XEVTCTL not implemented on a specific DSP may cause improper device operation.
Page 163: Serializer Control Registers (Srctln)
Registers 4.1.37 Serializer Control Registers (SRCTLn) Each serializer on the McASP has a serializer control register (SRCTL). There are up to 16 serializers per McASP. The SRCTL is shown in Figure 4–37 and described in Table 4–39. DSP specific registers Accessing SRCTLn not implemented on a specific DSP may cause improper device operation.
Page 164 Registers Table 4–39. Serializer Control Registers (SRCTLn) Field Descriptions (Continued) † field symval Value Description XRDY OF(value) Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter.
Page 165: Dit Left Channel Status Registers (Ditcsra0-Ditcsra5)
Registers 4.1.38 DIT Left Channel Status Registers (DITCSRA0–DITCSRA5) The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot). Each of the six 32-bit registers (Figure 4–38) can store 192 bits of channel status data for a complete block of transmission.
Page 166: Dit Left Channel User Data Registers (Ditudra0-Ditudra5)
Registers 4.1.40 DIT Left Channel User Data Registers (DITUDRA0–DITUDRA5) The DIT left channel user data registers (DITUDRA) provides the user data of each left channel (even TDM time slot). Each of the six 32-bit registers (Figure 4–40) can store 192 bits of user data for a complete block of transmis- sion.
Page 167: Transmit Buffer Registers (Xbufn)
Registers 4.1.42 Transmit Buffer Registers (XBUFn) The transmit buffers for the serializers (XBUF) hold data from the transmit for- mat unit. For transmit operations, the XBUF (Figure 4–42) is an alias of the XRBUF in the serializer. The XBUF can be accessed through the configuration bus (Table 4–1) or through the data port (Table 4–2).
Page 168: A Register Bit Restrictions
Appendix A Appendix A Register Bit Restrictions Some bit fields (see Table A–1) have restrictions on when they may be changed. These restrictions take the form of certain registers that must be as- serted in GBLCTL. Once these registers have been asserted, the user may then, and only then, change the desired bit field.
Page 169: A-1 Bits With Restrictions On When They May Be Changed
Table A–1. Bits With Restrictions on When They May be Changed ...these registers must be asserted in GBLCTL. To change... To change... To change... To change... HCLKRRST RGRST RSRCLR RSMRST RFRST HCLKXRST XGRST XSRCLR XSMRST XFRST Register Bit Field DITCTL DITEN XFMT XSSZ...
Page 170 Table A–1. Bits With Restrictions on When They May be Changed (Continued) ...these registers must be asserted in GBLCTL. To change... To change... To change... To change... HCLKRRST RGRST RSRCLR RSMRST RFRST HCLKXRST XGRST XSRCLR XSMRST XFRST Register Register Bit Field Bit Field ACLKRCTL CLKRP...
Page 171 Index Index AHCLKR bit in PDCLR 4-20 in PDIN 4-16 in PDIR 4-11 ACLKR bit in PDOUT 4-14 in PDCLR 4-20 in PDSET 4-18 in PDIN 4-16 in PFUNC 4-9 in PDIR 4-11 in PDOUT 4-14 AHCLKRCTL 4-39 in PDSET 4-18 AHCLKX bit in PFUNC 4-9 in PDCLR 4-20...
Page 172 Index considerations when using a McASP clocks 1-7 data format 1-7 bit stream data alignment data pins 1-7 receive 3-30 data transfers 1-7 transmit 3-27 current receive TDM time slot register block diagrams (RSLOT) 4-47 audio mute (AMUTE) 3-35 current transmit TDM time slot register EDMA event generation in TDM time slots 3-12 (XSLOT) 4-68 frame sync generator 2-7...
Page 173 Index INSTAT bit 4-25 interrupts 3-33 audio mute function 3-34 error conditions 3-33 error conditions 3-33 error handling and management 3-37 multiple interrupts 3-36 buffer overrun 3-39 receive data ready (RDATA) 3-33 buffer underrun 3-38 transmit data ready (XDATA) 3-33 clock failure detection 3-40 unexpected frame sync 3-37 loopback modes 3-45...
Page 174 Index pin function register (PFUNC) 4-9 receiver status register (RSTAT) 4-44 power down and emulation management register registers 4-2 (PWRDEMU) 4-8 audio mute control register (AMUTE) 4-25 protocols supported 1-3 bit restrictions A-1 PWRDEMU 4-8 current receive TDM time slot register (RSLOT) 4-47 current transmit TDM time slot register (XSLOT) 4-68...
Page 175 RGBLCTL 4-30 (XINTCTL) 4-63 in XGBLCTL 4-51 transmitter status register (XSTAT) 4-65 RSSZ bits 4-33 related documentation from Texas Instruments iv RSTAFRM bit RERR bit 4-44 in RINTCTL 4-42 REV bits 4-7 in RSTAT 4-44...
Page 176 Index XBUFn 4-76 TDM format 1-12 XBUFn bits 4-76 TDM sequencer 2-12 XBUSEL bit 4-54 terms 1-8 XCKFAIL bit 4-25 time-division multiplexed (TDM) transfer mode 3-9 in XINTCTL 4-63 trademarks iv in XSTAT 4-65 transfer modes 3-7 XCKFAILSW bit 4-69 burst mode 3-7 XCLKCHK 4-69 digital audio interface receive (DIR) 3-12...
Page 177 Index XRDY bit 4-72 XSTAFRM bit in XINTCTL 4-63 XROT bits 4-54 in XSTAT 4-65 XRVRS bit 4-54 XSTAT 4-65 XSLOT 4-68 XSLOTCNT bits 4-68 XSYNCERR bit 4-25 in XINTCTL 4-63 XSMRST bit in XSTAT 4-65 in GBLCTL 4-22 in RGBLCTL 4-30 XTDM 4-62 in XGBLCTL 4-51 XTDMSLOT bit 4-65...

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