Lvds Transmitter I/O Termination Schemes; Emulated Lvds External Termination; Sub-Lvds Transmitter External Termination - Altera MAX 10 User Manual

UG-M10LVDS
2016.10.31
You can statically adjust the V
Prime software Assignment Editor.
Table 3-2: Quartus Prime Software Assignment Editor—Programmable V
To
Assignment name
Allowed values

LVDS Transmitter I/O Termination Schemes

For transmitter applications in MAX 10 devices, you must implement external termination for some I/O
standards.

Emulated LVDS External Termination

The emulated LVDS transmitter requires a three-resistor external termination scheme.
Figure 3-3: External Termination for Emulated LVDS Transmitter
In this figure, R
Emulated LVDS on FPGA

Sub-LVDS Transmitter External Termination

The Sub-LVDS transmitter requires a three-resistor external termination scheme.
MAX 10 LVDS Transmitter Design
Send Feedback
of the differential signal by changing the V
OD
Field
= 120 Ω and R = 170 Ω.
S P
R S
R P
R S
LVDS Transmitter I/O Termination Schemes
tx_out
Programmable Differential Output Voltage (V
0 (low), 1 (medium), 2 (high). Default is 2.
50 Ω
50 Ω
settings in the Quartus
OD
OD
Assignment
)
OD
100 Ω
Altera Corporation
3-3
LVDS peer