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ARM L2C-310 Technical Reference Manual

Corelink level 2 mbist controller revision: r3p2
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CoreLink
Level 2 MBIST Controller
™
L2C-310
Revision: r3p2
Technical Reference Manual
Copyright © 2007-2010 ARM. All rights reserved.
ARM DDI 0402F (ID011711)

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  • Page 1 CoreLink Level 2 MBIST Controller ™ L2C-310 Revision: r3p2 Technical Reference Manual Copyright © 2007-2010 ARM. All rights reserved. ARM DDI 0402F (ID011711)
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Table Of Contents

    Contents CoreLink Level 2 MBIST Controller L2C-310 Technical Reference Manual Preface About this book ......................v Feedback ........................viii Chapter 1 Introduction About the MBIST controller ..................1-2 MBIST controller interface ..................1-3 RTL configuration ....................1-6 Product revisions ..................... 1-7...

  • Page 4: Preface

    Preface This preface introduces the CoreLink Level 2 MBIST Controller L2C-310 Technical Reference Manual. It contains the following sections: • About this book on page v • Feedback on page viii. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved.

  • Page 5: About This Book

    Identifies the minor revision or modification status of the product. Intended audience This book is written for hardware engineers who are familiar with ARM technology and want to use the MBIST controller to test the RAM blocks used by the cache controller. The AXI protocol is not specified but some familiarity with AXI is assumed.
  • Page 6 Key to timing diagram conventions. If a timing diagram shows a single-bit signal in this way then its value does not affect the accompanying description. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 7 AMBA AXI Protocol Specification (ARM IHI 0022) • ARM Architecture Reference Manual (ARM DDI 0406) • CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual (ARM DDI 0246) • CoreLink Level 2 Cache Controller L2C-310 Implementation Guide (ARM DII 0045).

  • Page 8: Feedback

    Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version.

  • Page 9: Introduction

    This chapter introduces the MBIST controller. It contains the following sections: • About the MBIST controller on page 1-2 • MBIST controller interface on page 1-3 • Product revisions on page 1-7. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...

  • Page 10: About The Mbist Controller

    MBIST block Data parity RAM (1) MBIST Dispatch controller unit Cache Data RAM (1) controller Tag RAMs (16) Figure 1-1 Cache controller MBIST configuration without data banking ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...

  • Page 11: Mbist Controller Interface

    Instead, the MBIST controller uses an additional input to the existing functional multiplexors without reducing maximum operating frequency. Figure 1-4 on page 1-4 shows the five pipeline stages used to access the cache RAM arrays. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 12 RAM arrays for test. When asserted, MTESTON takes priority over all other select inputs to the multiplexors. MBISTCE[17:0] Input One-hot chip enables to select cache RAM arrays for test. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 13 See Appendix A Signal Descriptions for descriptions of the MBIST controller interface signals. See the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual for more information about the MBIST interface. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved.

  • Page 14: Rtl Configuration

    If you want to use the banked RAM organization both of these 'defines have to be uncommented. The banked RAM structure splits both the Data RAM and Data parity RAM into four arrays. Two dedicated L2C-310 MBIST Yaddr bits select one of the four arrays.See Y-address and...

  • Page 15: Product Revisions

    There is no functional difference between these two revisions. r2p0-r3p0 Added support for data banking. r3p0-r3p1 There is no functional difference between these two revisions. r3p1-r3p2 There is no functional difference between these two revisions. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...

  • Page 16: Chapter 2 Functional Description

    MBIST engine, detecting failures, and retrieving the data log. It contains the following sections: • Functional overview on page 2-2 • Functional operation on page 2-11. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...

  • Page 17: Functional Overview

    AXI clock enables to 0, INCLKENS0, OUTCLKENS0, INCLKENS1, OUTCLKENS1, INCLKENM0, OUTCLKENM0, INCLKENM1, and OUTCLKENM1. Figure 2-1 on page 2-3 shows the interfaces between the MBIST controller and the RAMs that MBIST tests. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 18 MBIST testing can begin. The latency of the current RAM being tested is passed to the MBIST controller in the MBIST instruction. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 19 MBISTADDR[1:0] signal as a doubleword select for each index of the data RAM for writes. For reads from a previous MBIST transaction you use the MBISTDCTL[1:0] signal. You require separate pins because the MBIST transactions are pipelined. The MBIST controller ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 20 The signal MBISTCE[0] is for the chip enable to the data RAM. The signal MBISTDCTL[2:0] is for reads from previous MBIST transactions. Figure 2-3 on page 2-6 shows the cache controller MBIST paths for data RAM testing. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 21 1,024 TAGADDR[9:0]=MBISTADDR[11:2] TAGWD[20:1]=MBISTDIN[20:1] 512KB 64KB 2,048 TAGADDR[10:0]=MBISTADDR[12:2] TAGWD[20:2]=MBISTDIN[20:2] 128KB 4,096 TAGADDR[11:0]=MBISTADDR[13:2] TAGWD[20:3]=MBISTDIN[20:3] 256KB 8,192 TAGADDR[12:0]=MBISTADDR[14:2] TAGWD[20:4]=MBISTDIN[20:4] 512KB 16,384 TAGADDR[13:0]=MBISTADDR[15:2] TAGWD[20:5]=MBISTDIN[20:5] For all cases: • lockdown by line TAGLWD=MBISTDIN[21] ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 22 Figure 2-4 Cache controller MBIST paths for tag RAM testing Note • MBISTCE[16:1] corresponds to TAGCS[15:0] • MDBISTDCL[18:3] corresponds to TAG[15:0] • Only bits [22:0] of MBISTDIN and MBISTDOUT are used. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 23 When the instruction shift is enabled, data shifts between the two parts of the BIST engine are on bit 3. In run test mode, this bit is used as invert data information. The MBISTTX[11:0] interface is ARM-specific and intended for use only with the MBIST controller.
  • Page 24 This signal is an output of the dispatch unit that goes to the MBIST controller. The behavior of MBISTRX[2:0] is ARM-specific and is intended for use only with the MBIST controller. The address expire signal is set when both the row and column address counters expire.
  • Page 25 At the completion of the test, the MBISTRESULT[2] signal goes HIGH. The MBISTRESULT[0] signal indicates that an address expire has occurred and enables you to measure sequential progress through the test algorithms. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 2-10 ID011711 Non-Confidential...

  • Page 26: Functional Operation

    CLK. With CLK disabled, drive MBISTRUN HIGH and, after an MBISTRUN setup time, start the PLL at the test frequency as shown in Figure 2-7. MBISTRUN MBISTSHIFT Figure 2-7 Starting the MBIST test ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 2-11 ID011711 Non-Confidential...
  • Page 27 (data log shift out) MBISTRUN Figure 2-9 Start of data log retrieval When the last data log bit shifts out, drive MBISTDSHIFT LOW as Figure 2-10 on page 2-13 shows. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 2-12 ID011711 Non-Confidential...
  • Page 28 Y-address and X-address fields, MBIR[36:33] and MBIR[40:37] on page 3-7 for more information on the doubleword select value. Contact ARM if you require more information. 2.2.2 Bitmap mode In bitmap mode, you can identify all failing locations in a RAM. Each time a failure occurs, the...
  • Page 29 Functional Description MBISTRESULT[1] MBISTDSHIFT D[83] D[84] D[85] MBISTRESULT[0] MBISTRUN Figure 2-12 End of bitmap data log retrieval Loading a new instruction resets bitmap mode. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 2-14 ID011711 Non-Confidential...

  • Page 30: Chapter 3 Mbist Instruction Register

    This chapter describes how to use the MBIST Instruction Register (MBIR) to configure the mode of operation of the MBIST controller. It contains the following sections: • About the MBIST Instruction Register on page 3-2 • Field descriptions on page 3-3. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...

  • Page 31: About The Mbist Instruction Register

    Lockdown by line support Specifies if lockdown by line is supported. Way configuration Specifies an 8-way or 16-way configuration. Field descriptions on page 3-3 describes the MBIR fields in more detail. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...

  • Page 32: Field Descriptions

    Read write read march pattern, incrementing X-address first 0b001000 Read Write Read March (y-fast) Read write read march pattern, incrementing Y-address first 0b001001 Bang Bit-line stress pattern 0b001010 Go/No-Go Table 3-2 on page 3-5 0b111111 ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 33 (w0) (r0, w0, w0(row 0) × 6) (r0 × 5, w0(row 0), r0) (r0) ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 34 Read Write Read March (y-fast) Bang This test suite provides a comprehensive test of the arrays. The series of tests in Go/No-Go are the result of the experience in memory testing by ARM memory test engineers. 3.2.2 Control field, MBIR[54:49] The control field specifies the MBIST function.
  • Page 35 Table 3-5 shows the latency settings for write operations. Table 3-5 Write latency field encoding Write latency Number of cycles MBIR[48:45] per write operation 0b0000 0b0001 0b0010 0b0011 0b0100 ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 36 Y-address and used for the block select. Figure 3-2 on page 3-8 shows an example topology for the Data RAM in a 256K level-2 cache. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 37 Y-address counter is the least significant bit of the column address for physical addressing of the columns. This is followed by the row address from the X-address counter and, if required, the block address. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 38 ..Block Column Bank address address address select MBISTADDR[19:0] Double- word select Figure 3-4 MBIST address scrambling for banked mode data and data parity RAM ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 39 X address settings. Table 3-7 X-address field encoding X-address Number of MBIR[40:37] counter bits < Unsupported 0b0010 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 > Reserved 0b1010 ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 3-10 ID011711 Non-Confidential...
  • Page 40 X-address and Y-address fields for testing of data parity RAM. Table 3-10 Required sums of X-address and Y-address fields for data parity RAM Cache size Data parity RAM 128KB 256KB 512KB ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 3-11 ID011711 Non-Confidential...
  • Page 41 Tag 8 0b000000001000000000 Tag 9 0b000000010000000000 Tag 10 0b000000100000000000 Tag 11 0b000001000000000000 Tag 12 0b000010000000000000 Tag 13 0b000100000000000000 Tag 14 0b001000000000000000 Tag 15 0b010000000000000000 Data parity RAM 0b100000000000000000 ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 3-12 ID011711 Non-Confidential...
  • Page 42 Table 3-13 Cache size field encoding Cache size MBIR[8:6] Cache size Reserved 0b000 128KB 0b001 256KB 0b010 512KB 0b011 0b100 0b101 0b110 0b111 ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 3-13 ID011711 Non-Confidential...
  • Page 43 Way configuration field, MBIR[0] The way configuration field specifies an 8-way or 16-way configuration in your implementation. Set to 0 for an 8-way configuration or 1 for a 16-way configuration. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. 3-14 ID011711 Non-Confidential...
  • Page 44 Signal Descriptions This appendix describes the MBIST controller signals. It contains the following sections: • MBIST controller interface signals on page A-2 • Miscellaneous signals on page A-4. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...

  • Page 45: Mbist Controller Interface Signals

    MBISTCE[13] = Tag RAM 12 chip enable MBISTCE[14] = Tag RAM 13 chip enable MBISTCE[15] = Tag RAM 14 chip enable MBISTCE[16] = Tag RAM 15 chip enable MBISTCE[17] = Data parity chip enable ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 46 16-way or 8-way. For a16-way configuration, connect MBISTCE[17] from the MBIST controller to MBISTCE[17] on the cache controller. For an 8-way configuration, connect MBISTCE[17] from the MBIST controller to MBISTCE[9] on the cache controller. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...

  • Page 47: Miscellaneous Signals

    MBISTDSHIFT Input Data log shift MBISTRESETN Input MBIST reset MBISTRESULT[2:0] Output Output status bus MBISTRUN Input Run MBIST test MBISTSHIFT Input Instruction shift MTESTON Input MBIST Mode Enable ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 48 Affects MBIST controller interface description updated MBIST controller interface on page 2-2 r3p1 Table B-3 Differences between issue E and issue F Change Location Affects No technical changes ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. ID011711 Non-Confidential...
  • Page 49 Advanced Microcontroller Bus Architecture (AMBA) A family of protocol specifications that describe a strategy for the interconnect. AMBA is the ARM open standard for on-chip buses. It is an on-chip bus specification that describes a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
  • Page 50 This is done to greatly reduce the average time for memory accesses and so to increase processor performance. ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. Glossary-2 ID011711...
  • Page 51 See also Fast Context Switch Extension. Reads are defined as memory operations that have the semantics of a load. That is, the ARM Read...
  • Page 52 See Write-back. A 32-bit data item. Word Writes are defined as operations that have the semantics of a store. That is, the ARM instructions Write SRS, STM, STRD, STC, STRT, STRH, STRB, STRBT, STREX, SWP, and SWPB, and the Thumb instructions STM, STR, STRH, STRB, and PUSH. Java instructions that are accelerated by hardware can cause a number of writes to occur, according to the state of the Java stack and the implementation of the Java hardware acceleration.
  • Page 53 Block address Index Word Byte Cache way Cache set Cache line Word number Line number Cache tag RAM Cache data RAM Read data (way number) (way that corresponds) ARM DDI 0402F Copyright © 2007-2010 ARM. All rights reserved. Glossary-5 ID011711 Non-Confidential...

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