COBHAM GR740 User Manual
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COBHAM GR740 User Manual

COBHAM GR740 User Manual

Quad core leon4 sparc v8 processor
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GR740
Quad Core LEON4 SPARC V8 Processor
2017 Preliminary Data Sheet and User's Manual
The most important thing we build is trust
Features
• Fault-tolerant quad-processor
with 7-stage pipeline, 8 register windows, 4x4 KiB
instruction and 4x4 KiB data caches.
• Double-precision IEEE-754 floating point units
• 2 MiB Level-2 cache
• 64-bit PC100 SDRAM memory interface with Reed-
Solomon EDAC*
• 8/16-bit PROM/IO interface with EDAC*
• SpaceWire router with eight SpaceWire links
• 2x 10/100/1000 Mbit Ethernet interfaces*
• PCI Initiator/Target interface*
• MIL-STD-1553B interface*
• 2x CAN 2.0 controller interface*
• 2x UART, SPI, Timers and watchdog, 16+22 GPIO*
• CPU and I/O memory management units
• SpaceWire Time Distribution Protocol controller and
support for time synchronisation
• JTAG, Ethernet* and SpaceWire* debug links
* Interfaces have shared pins
32-bit APB
IRQ(A)MP
Memory
Scrubber
S M
96-bit
SDRAM
S
PC100
CTRL w.
SDRAM
EDAC
S
PROM
PROM
& IO
IO
S
CTRL w.
8/16-bit
EDAC
S
AHB
Pad / PLL
controller
Status
Clock gating
S
unit
S
Temperature
Timer unit 0
sensor
watchdog
Applications
The GR740 device is targeted at high-performance general purpose 
processing. The architecture is suitable for both symmetric and 
asymmetric multiprocessing. Shared resources can be monitored to 
support mixed-criticality applications.
GR740-UM-DS, Nov 2017, Version 1.7
SPARC
V8 integer unit
S
S
S
Statistics
LEON4
STAT.UNIT
LEON4
Caches
Caches
L2
MX
S
Memory bus
Cache
128-bit AHB
S
AHB/APB
Bridges
M
M
Slave IO bus
S
32-bit AHB
X
PCI
Timer units
Master
1 - 4
S
S
S
S
S
S
GPIO port
Bootstrap
UART
0 - 1
GP register
Description
The GR740 device is a radiation-hard system-on-
chip featuring a quad-core fault-tolerant LEON4
SPARC V8 processor, eight port SpaceWire router,
PCI initiator/target interface, MIL-STD-1553B
interface, CAN 2.0 interfaces and 10/100/1000
Mbit Ethernet interfaces.
Specification
• System frequency: 250 MHz
• Main memory interface: PC100 SDRAM
• SpaceWire router with SpaceWire links: 300
Mbit/s
• 33 MHz PCI 2.3 initiator/target 
interface
• Ethernet 10/100/1000 Mbit MACs
• CCGA625 / LGA625 package
FPU
FPU
FPU
LEON4
Caches
MMU
MMU
MMU
MX
MX
MX
Processor bus
S
S
128-bit AHB
AHB/AHB
Bridge
M
M
AHB Bridge
M
IOMMU
S
S
S
M
M
M
PCI
PCI
SpW router
Target
DMA
S
S
S
S
S
SPI
TDP
controller
controller
32-bit APB
M
X
AHB/APB
SpW RMAP
DSU4
Bridge
S
S
Debug bus
S
AHB/AHB
Bridge
32-bit AHB
M
S
X
AHBTRACE
AHB
X
Status
S
Master IO bus
32-bit AHB
M
M
M
M
CAN
MIL-STD
Ethernet
Controller
1553B
S S
S
S S
www.cobham.com/gaisler
S
DCL
M
M
JTAG
DCL

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Summary of Contents for COBHAM GR740

  • Page 1 0 - 1 GP register Applications The GR740 device is targeted at high-performance general purpose  processing. The architecture is suitable for both symmetric and  asymmetric multiprocessing. Shared resources can be monitored to  support mixed-criticality applications. GR740-UM-DS, Nov 2017, Version 1.7...

  • Page 2: Table Of Contents

    System integrity and debug communication links ................43 Separation and ASMP configurations ....................43 Clock gating ............................44 Software portability..........................45 Level-2 cache ............................45 Time synchronisation ..........................46 5.10 Bridges, posted-writes and ERROR response propagation..............47 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 3 Access Protection Vector........................125 12.5 IO Memory Management Unit (IOMMU) functionality..............127 12.6 Fault-tolerance............................. 130 12.7 Statistics............................... 131 12.8 ASMP support ............................. 131 12.9 Registers .............................. 132 SpaceWire router........................142 13.1 Overview ............................. 142 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 4 Interrupt ............................... 270 17.9 Registers .............................. 271 17.10 Memory mapping ..........................281 Bridge connecting Slave I/O AHB bus to Processor AHB bus..........282 18.1 Overview ............................. 282 18.2 Operation ............................. 282 18.3 Registers .............................. 285 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 5 LEON4 Statistics Unit (Performance Counters)..............342 26.1 Overview ............................. 342 26.2 Multiple APB interfaces ........................344 26.3 Registers .............................. 345 AHB Status Registers ......................349 27.1 Overview ............................. 349 27.2 Operation ............................. 349 27.3 Registers .............................. 350 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 6 35.7 RMAP..............................418 35.8 AMBA interface ..........................422 35.9 Registers .............................. 423 AHB Trace buffer tracing Master I/O AHB bus ..............429 36.1 Overview ............................. 429 36.2 Operation ............................. 429 36.3 Registers .............................. 431 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 7 Package placement diagram ........................ 459 40.3 Pin assignment............................. 460 40.4 Package drawing..........................475 Temperature and thermal resistance..................479 Ordering information ......................480 Silicon Revisions and Errata ....................481 43.1 Overview ............................. 481 43.2 Change and errata descriptions......................482 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 8: Introduction

    GR740 Introduction Scope This document is the preliminary data sheet for the GR740 device. The GR740 was developed in an activity funded by the European Space Agency. Preliminary data sheet limitations Note that this document is a preliminary data sheet: •...

  • Page 9: Reference Documents

    Yuriy Sheynin, Distributed Interrupts in SpaceWire Interconnections, International SpaceWire Conference, Nara, November 2008 (out- dated) [SPWPNP] Space Engineering: SpaceWire Plug-and-Play protocol, ECSS-E-ST- 50-54C, Draft, March 2013 [V8E] SPARC-V8 Supplement, SPARC-V8 Embedded (V8E) Architecture Specification, SPARC-V8E, Version 1.0, SPARC International Inc. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 10: Document Revision History

    Version Date Note 2015 April First public release of GR740 document. 2015 November Fix typo of CE/NE bit in AHBSTAT section. Clarify that Level-2 cache is unified. Correct L4STAT section 26.1 to state that the unit has sixteen counters. Correct GRSPWROUTER documentation: Error in the description of the ICODEGEN regis- ter.
  • Page 11 Note that TESTEN should be connected to ground in section 3.4 Correct PCI_HOSTN signal name typo in table 27. Correct PCIMODE_ENABLE heading in table 27. Effect of bootstrap signal GPIO[15] was inverted. LOW enables full PROM/IO interface, corrected in table 23 and section 3.3.1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 12 Add GRLIB-TN-0013 issue in section 43.2.27. Clarify that WDOGN and ERRORN are open-drain in tables 28 and 597.  Updated Absolute Maximum Ratings and recommended operating conditions, adding over- shoot specifications, in section 39. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 13: Acronyms

    IEEE 1541-2002 Operating System Peripheral Component Interconnect PROM Programmable Read Only Memory. In this document used to signify boot-PROM. Random Access Memory RMAP Remote Memory Access Protocol Single Event Effects SEL/SEU/SET Single Event Latchup/Upset/Transient GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 14: Definitions

    1.10.3 Data types Byte (BYTE) 8 bits of data Halfword (HWORD) 16 bits of data Word (WORD) 32 bits of data Double word (DWORD) 64 bits of data Quad word (4WORD) 128-bits of data GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 15: Register Descriptions

    Readable and writable. Special condition for write, described in textual description of field. Write-clear. Readable, and cleared when written with a 1 Readable, and writable through compare-and-swap. Only applies to SpaceWire Plug-and-Play regis- ters. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 16: Architecture

    The chapters in this document have been grouped after the bus topology. The first chapters describe components connected to the Processor AHB bus, followed by the Memory AHB bus, Master I/O AHB bus and finally Slave I/O AHB bus, APB buses and Debug AHB bus. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 17 GR740 The GR740 has the following on-chip functions: • 4x LEON4 SPARC V8 processor cores with MMU and GRFPU floating-point unit • Level-2 cache, 4-ways, BCH protection, supports locking of 1-4 ways • Debug Support Unit (DSU) with instruction (512 lines) and AHB trace (256 lines) buffers •...

  • Page 18: Cores

    GR740 Temperature sensor controller 0x01 0x099 The information in the last two columns is available via plug’n’play information in the system and is used by software to detect units and to initialize software drivers. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 19: Memory Map

    GRETH_GBIT1 Gigabit Ethernet MAC 1 registers Processor 0xFF980000 - 0xFF9800FF APBBRIDGE0 Unused Processor 0xFF990000 - 0xFF9FFEFF APBBRIDGE0 APB bus 0 plug&play area Processor 0xFF9FF000 - 0xFF9FFFFF APBBRIDGE1 APB bridge 1 Processor 0xFFA00000 - 0xFFAFFFFF GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 20 "Unused" in the table above. No AMBA ERROR response will be given for memory allocated to one of the APB bridges. See also the AMBA ERROR propagation description in section 5.10. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 21 Debug APB bus plug&play area 0xE40FFF00 - 0xE40FFFFF 0xE4100000 - 0xEEFFFFFF Unused AHBTRACE 0xEFF00000 - 0xEFF1FFFF AHB trace buffer, tracing master I/O AHB bus 0xEFF20000 - 0xEFFFEFFF Unused Debug AHB bus plug&play area 0xEFFFF000 - 0xEFFFFFFF GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 22: Interrupts

    Plug & play and bus index information The format of GRLIB AMBA Plug&play information is given in sections 37 and 38. The address ranges of the plug&play configuration areas are given in the preceding section and is also replicated GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 23 The plug & play memory map and bus indexes for AMBA AHB slaves on the Processor AHB bus are shown in table 13. Table 13. Plug & play information for slaves on Memory AHB bus Slave Index Function Address range MMCTRL SDRAM controller 0xFFEFF800 - 0xFFEFF81F MEMSCRUB Memory scrubber 0xFFEFF820 - 0xFFEFF83F GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 24 Slave Index Function Address range FTMCTRL PROM/IO controller 0xFF8FF800 - 0xFF8FF81F GRPCI2 PCI master interface 0xFF8FF820 - 0xFF8FF83F GRIOMMU IOMMU register interface 0xFF8FF840 - 0xFF8FF85F GRSPWROUTER SpaceWire router AMBA configuration interface 0xFF8FF860 - 0xFF8FF87F GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 25 GRSPWROUTER SpaceWire router AMBA interface 2 0xFF9FF060 - 0xFF9FF067 GRSPWROUTER SpaceWire router AMBA interface 3 0xFF9FF068 - 0xFF9FF06F GRETH_GBIT 10/100/1000 Mbit Ethernet MAC 0xFF9FF070 - 0xFF9FF077 GRETH_GBIT 10/100/1000 Mbit Ethernet MAC 0xFF9FF078 - 0xFF9FF07F GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 26 Table 22. Plug & play information for APB slaves connected via APB bridge on Debug AHB bus Slave Index Function Address range GRSPW2 SpaceWire codec AMBA interface with RMAP target 0xE40FF000 - 0xE40FF007 L4STAT LEON4 Statistics Unit 0xE40FF008 - 0xE40FF00F GRPCI2 GRPCI2 trace buffer secondary interface 0xE40FF010 - 0xE40FF017 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 27: Signals

    GPIO[0] is connected to the set elapsed time input, see section 31.3.11. GPIO[1] is connected to the increment elapsed time input, see section 31.3.3. Note: The TDP connections are only available in silicon revision 1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 28: Configuration For Flight

    (peripheral) mode, enough dedicated PROM/IO pins are still available to access an 8-bit, 64 KiB boot PROM for bootstrapping the system. Note that it is the top part of the data bus (PRO- MIO_DATA[15:8]) that is used for the PROM in 8-bit mode. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 29 (as pin name) GR1553_BUSBRXP GPIO2[3] PROMIO_DATA[0] (as pin name) GR1553_BUSBRXN GPIO2[2] PROMIO_CEN[1] (as pin name) CAN_TX0 GPIO2[1] IO_SN (as pin name) CAN_TX1 GPIO2[0] * See section 40.3 for pin assignments ** See section 30 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 30 (as pin name) ETH1_TXEN PCI_AD[23] MEM_DQ[86] (as pin name) ETH1_TXER PCI_AD[22] MEM_DQ[85] (as pin name) (none) PCI_AD[21] MEM_DQ[84] (as pin name) (none) PCI_AD[20] MEM_DQ[83] (as pin name) (none) PCI_AD[19] MEM_DQ[82] (as pin name) (none) PCI_AD[18] GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 31 MEM_DQM[10] (as pin name) ETH1_TXCLK PCI_HOSTN MEM_DQM[7] (as pin name) ETH1_RXCLK PCI_IDSEL MEM_DQM[6] (as pin name) (none) PCI_CLK MEM_DQM[5] (as pin name) (none) PCI_INTC MEM_DQM[4] (as pin name) (none) PCI_INTD * See section 40.3 for pin assignments GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 32: Complete Signal List

    JTAG_TDO JTAG Data out JTAG_TRST JTAG Reset ETH0_TXER Ethernet port 0, Transmit error High ETH0_TXD[7:0] Ethernet port 0, Transmitter output data ETH0_TXEN Ethernet port 0, Transmitter enable High ETH0_GTXCLK Ethernet port 0, Gigabit clock GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 33 SpaceWire router ports 1 - 8, transmit strobe, negative SPW_RXD_P[7:0] SpaceWire router ports 1 - 8, receive data, positive SPW_RXD_N[7:0] SpaceWire router ports 1 - 8, receive data, negative SPW_RXS_P[7:0] SpaceWire router ports 1 - 8, receive strobe, positive GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 34 See 3.3.1 UART1_RXD UART 1, receive data See 3.3.1 UART1_RTSN UART 1, request to sent See 3.3.1 UART1_CTSN UART 1, clear to send See 3.3.1 GR1553_BUSARXEN MIL-STD-1553 Bus A receiver enable See 3.3.1 High GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 35: Pin Driver Configuration

    SpaceWire links in this device, so this must be managed by the application software. Applications not using the SpaceWire router at all are recommended to disable all Spacewire LVDS drivers during boot. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 36: Clocking And Reset

    Other ways of generating the SDRAM clocks such as external PLL:s are also possible. Note: The external feedback loop is always required, no matter which clock source that is selected. The memory controller SDRAM domain is never clocked internally, only through MEM_CLK_IN. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 37: Reset Scheme

    GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 38: Clock Multiplexing For Main System Clock, Sdram And Spacewire

    SPW codec pll_locked[5:4] mem_ifwidth AND pcimode_enable Neg clk & to PCI core mem_dqm[11] & to GRETH1 mem_dqm[6] to GRETH1 & mem_dqm[10] & to GRETH1 mem_dqm[7] mem_ifwidth AND (NOT pcimode_enable) Figure 1. GR740 clock multiplexing GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 39: Pll Control And Configuration

    25-53 MHz 2 x MEM_EXTCLK Default configuration Table 32. Supported SPWPLL configurations SPWPLL SPW_CLK SpaceWire clock Comment Config word Input range 000010000 25-53 MHz 8 x SPW_CLK Default configuration 000001100 33.3-70 MHz 6 x SPW_CLK GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 40: Pll Watchdog

    FPU operations by setting the %psr.ef bit to zero, or when the processor has entered power-down/halt mode. After reset, processors 1 to 3 will be in power-down mode. Processor 0 will start executing if the BREAK bootstrap signal is LOW. If the BREAK bootstrap signal is HIGH GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 41: Debug Ahb Bus Clocking

    100 and 1000 Mbit mode the corresponding TXCLK must be present. Ethernet PHYs may disable the TXCLK when entering 1000 Mbit mode and this may cause the internal register value in the GR740 to remain at the 10/100 Mbit value after the PHY has entered 1000 Mbit operation. When this happens the system will not be able to transmit Ethernet traffic.

  • Page 42: Technical Notes

    0xEFFFF000 should be specified to the monitor. In the case where the monitor detects that it is connected to a GR740 design, it may be necessary to force the monitor to start scanning at the default address 0xFFFFF000 when connecting with a debug monitor through the Master I/O bus, from which the Debug AHB bus cannot be accessed (this is not required for GRMON2).

  • Page 43: System Integrity And Debug Communication Links

    Each processor now runs supervisor code that sets up it's MMU page tables so that it can not access peripherals and memory belonging to other partitions, and also so that it can only access GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 44: Clock Gating

    The GRMON debugger has support for enabling all clocks when con- necting to the device and clocks for specific peripherals can also be enabled via the command line interface. Please see the GRMON user manual and operating system documentation for more infor- mation. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 45: Software Portability

    5.7.4 below. 5.7.2 Peripherals All peripherals in the design are IP cores from Cobham Gaisler’s GRLIB IP library. Standard GRLIB software drivers can be used. For software driver development, this document describes the capabilities offered by the GR740 sys- tem.

  • Page 46: Time Synchronisation

    All external datation services share the same event inputs. The event on which time stamp must occur is configurable individually (using mask registers) for all the external datation services GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 47: Bridges, Posted-Writes And Error Response Propagation

    Bridges, posted-writes and ERROR response propagation The GR740 system consists of several AHB buses connected via bridges. The bridges in the system make use of posted writes. Write operations on the slave side of a bridge will complete and then the write operation on the master side of the bridge will be started.

  • Page 48: Leon4 - Fault-Tolerant High-Performance Sparc V8 32-Bit Processor

    The floating-point controller and floating-point unit are further describes in sections 7 and 8. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 49 6.1.9 Multi-processor support LEON4 is designed to be used in multi-processor systems. Each processor has a unique index to allow processor enumeration. The write-through caches and snooping mechanism guarantees memory coherency in shared-memory systems. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 50: Leon4 Integer Unit

    Execute mul/div alu/shift e pc dcache address m_inst m_pc result D-cache Memory dcache read data x_inst x_pc xres Exception w_inst w_pc wres Write-back tbr, wim, psr Figure 3. LEON4 integer unit datapath diagram GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 51 For instance on a load cache miss followed by a data-dependent instruction, both hold cycles and load delay will be incurred. FPU: The floating-point unit or coprocessor may need to hold the pipeline or extend a specific instruction. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 52 6.2.3 SPARC Implementor’s ID Cobham Gaisler is assigned number 15 (0xF) as SPARC implementor’s identification. This value is hard-coded into bits 31:28 in the %psr register. The version number for LEON4 is 3 (same as for LEON3 to provide software compatibility), which is hard-coded in to bits 27:24 of the %psr.
  • Page 53 When PSR (processor status register) bit ET=0, an exception trap causes the processor to halt execution and enter error mode. When processor 0 enters error mode, the external PROC_ERRORN signal will be asserted. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 54 When enabled, any taken trap will always jump to the reset trap handler (%tbr.tba + 0). The trap type will be indicated in %tbr.tt, and must be decoded by the shared trap handler. SVT is enabled by setting bit 13 in %asr17. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 55 %PSR.ET field. If the WRPSR instruction’s rd field is non-zero, then the WRPSR write will only update ET. Partial WRPSR should only be used on silicon revision 1 of the GR740 device, see section 43.2.4. 6.2.17 Power-down The processor has a power-down feature to minimize power consumption during idle periods. The...

  • Page 56: Cache System

    If the processor needs extra pipeline cycles to stretch a multi-cycle instruction or due to an inter- lock condition (see section 6.2), or if the processor jumps/branches away, then the instruction cache will hold the pipe, fetch the remainder of the cache line, and the pipeline will then proceed normally. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 57 Since the processor executes in parallel with the write buffer, a write error will not cause an exception to the store instruction. Depending on memory and cache activity, the write cycle may not occur until several clock cycles after the store instructions has completed. If a write error occurs, the currently GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 58 If a cache has been frozen by an interrupt, it can only be enabled again by GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 59: Memory Management Unit

    Both the tag address and context field must match to generate a cache hit. If cache snooping is used, physical tags must be enabled for it to work when address translation is used, see section 6.3.7. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 60: Floating-Point Unit

    All instructions except FDIV and FSQRT has a latency of three cycles, but to improve timing, the LEON4 FPU controller inserts an extra pipeline stage in the result forwarding path. This results in a GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 61: Co-Processor Interface

    6.7.2 Cachability The processor treats the memory areas 0x00000000 - 0x7FFFFFFF and 0xC0000000 - 0xCFFFFFFF as cacheable. The test of the physical address space is treated as uncached. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 62 : "r"(addr) return tmp; In the GR740 device, this may primarily be of interest when accessing the PROM area (base address at 0xC0000000) and possibly also for using the processor to test word and sub-word accesses to the Level-2 cache and memory controller (memory area 0x00000000 - 0x7FFFFFFF).

  • Page 63: Multi-Processor System Support

    FIFO if they are not to the same address as the stores. Loaded data from other addresses may therefore be either older or newer, with respect to the global memory order, than the stores that have been performed by the same CPU. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 64: Asi Assignments

    0x19 MMU only: MMU registers 0x1C MMU only: MMU and cache bypass 0x1D MMU only: MMU diagnostic access (deprecated, do not use in new SW applications) 0x1E MMU only: MMU snoop tags diagnostic access GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 65 For situations where you want to guarantee that the cache is not modified by the access, the MMU and cache bypass ASI, 0x1C, can be used instead. However this is only available when MMU is imple- mented. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 66 The parity to be written is calculated based on the supply write-value and the context ID in the MMU control register. The parity bits can be modified via the TB field in the cache control register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 67 Writing to ASI 0x18, which is available only if MMU is implemented, will flush both the MMU TLB, the I-cache, and the D-cache. This will block execution for a few cycles while the TLB is flushed and then continue asynchronously with the cache flushes continuing in the background. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 68 Parity. The odd parity over the data tag. Only used when processor is implemented with fault-tolerance features. [0]: Invalid. When set, the cache line is not valid and will cause a cache miss if accessed by the processor. Only present if fast snooping is enabled. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 69: Configuration Registers

    Taken from interrupt controller. Default is 0xC0000 31: 12 Trap base address (TBA) - Top 20 bits used for trap table address 11: 4 Trap type (TT) - Last taken trap type. 3: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 70 1: 0 IU register file correctable error (IUCE) - Flag set when a correctable error has been detected in the IU register file. Bit 1 flags uneven registers and bit 0 flags even registers. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 71 SPARC V8 (V8) - Set to 1, to signify that the SPARC V8 multiply and divide instructions are avail- able. 7: 5 Number of implemented watchpoints (NWP) - Value is 4. 4: 0 Number of register windows (NWIN) - Number of implemented registers windows corresponds to NWIN+1. Field has value 7. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 72 UPCNT(31:0) 31: 0 Counter value (UPCNT(31:0)) - Least significant bits of internal up-counter. Counter is reset to 0 at reset but may start counting due to conditions described for the DUCNT field in %asr22. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 73 When there is a hardware watchpoint match and DL or DS is set then trap 0x0B will be generated. Hardware watchpoints can be used with or without the LEON4 debug support unit (DSU) enabled. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 74 Data Cache state (DCS) - Indicates the current data cache state according to the following: X0= dis- abled, 01 = frozen, 11 = enabled. Instruction Cache state (ICS) - Indicates the current data cache state according to the following: X0= disabled, 01 = frozen, 11 = enabled. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 75 Line size (LSIZE) - Indicated the size (words) of each cache line. Set to 2. Line size = 2 words = 32 bytes. 15: 4 RESERVED MMU present (M) - This bit is set to ‘1’ to signify that an MMU is present. 2: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 76 RESERVED TLB disable (TD) - When set to 1, the TLB will be disabled and each data access will generate an MMU page table walk. The TLB should not be disabled on GR740 silicon revision 0, see section 43.2.9. Separate TLB (ST) - This bit is set to 1 to signify that separate instruction and data TLBs are imple-...
  • Page 77 In the LEON4, the context bits are OR:ed with the lower MMU context pointer bits when calculating the address, so one can use less context bits to reduce the size/alignment requirements for the context table. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 78: Software Considerations

    After reset, the caches are disabled and the cache control register (CCR) is 0. Before the caches may be enabled, a flush operation must be performed to initialized (clear) the tags and valid bits. A suitable assembly sequence could be: flush set 0x81000f, %g1 sta %g1, [%g0] 2 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 79 In such cases, executing a cache flush instruction periodically (e.g. once per minute) is sufficient to refresh the cache contents. 6.11.4 Other considerations Please see the application note Handling of External Memory EDAC Errors in LEON/GRLIB systems [GR-AN-0004]. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 80: Floating-Point Control Unit

    GRFPC). When the trap is taken the floating-point deferred-queue (FQ) contains the trap-inducing instruction and up to seven FPop instructions that were dispatched in the GRFPC but did not com- plete. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 81 Execution or emulation of instructions in the FQ by the supervisor software gives therefore the same FPU state as if the instructions were executed in the program order. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 82: High-Performance Ieee-754 Floating-Point Unit

    GRFPU supports four types of floating-point operations: arithmetic, compare, convert and move. The operations implement all FP instructions specified by SPARC V8 instruction set, and most of the operations defined in IEEE-754. All operations are summarized in table 62. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 83 16 - 25 clock cycles and latency of 16 - 25 clock cycles (see GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 84 If the infinitely precise result of an operation is a tiny number (smaller than minimum value representable in normal format) the result is flushed to zero (with underflow and inexact flags set). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 85 0x7fff0000 for single precision results. Table 64. : Operations on NaNs Operand 2  QNaN2 SNaN2  none QNaN2 QNaN_GEN  QNaN2 QNaN_GEN Operand 1 QNaN1 QNaN1 QNaN2 QNaN_GEN SNaN1 QNaN_GEN QNaN_GEN QNaN_GEN GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 86: Level 2 Cache Controller

    (to write back dirty cache lines to memory). This can be done by setting the Cache disable bit when issue a flush all command. The GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 87 16 bytes sub-block (with offset 1) in the cache line and valid bit 1 corre- sponds to the upper 16 bytes sub-block (with offset 0) in the cache line. 7 : 6 Dirty bits When set, this sub-block contains modified data. RESERVED 4 : 0 LRU bits GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 88 Cache-line is invalidated, Error status is Uncorrectable Data tus is updated with a correctable error. AHB updated with a uncorrectable error. AHB error access is not affected. access write data and cache data is lost. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 89: Operation

    Instead the write access is issued towards the memory as well. A new cache line is allocated on a miss for a cacheable write access independent of write policy (copy-back or write-through). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 90 The tag check bit manipulation is only done if the tag-check-bit register is not zero. The xor-check-bit is reset on the next tag replacement or data write. Errors can also be injected GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 91 The cache controller has a status register that provides information on the cache configuration (multi- way configuration and set size). The cache also provides access, hit and error correction counters via the LEON4 statistics unit (see section 26). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 92: Registers

    = RESERVED bit[22:16] = check-bits for data word at offset 0x4. bit[15] = RESERVED bit[14:8] = check-bits for data word at offset 0x8. bit[7] = RESERVED bit[6:0] = check-bits for data word at offset 0xc. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 93 Memory Type Range Registers (MTRR) - Number of MTRR registers implemented (16) 15: 13 Backend bus width (BBUS-W) Set to 1 = 128-bit. 12: 2 Cache way size (WAY-SIZE) - Size in kBytes 1: 0 Multi-Way configuration (WAY) Set to “11“: 4-way GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 94 “01“: Update Valid/Dirty bits according to register bit[8:7] and TAG according to register bits[31:10] “10”: Write-back dirty lines to memory “11“: Update Valid/Dirty bits according to register bits [8:7] and TAG according to register bits[31:10], and Write-back dirty lines to memory. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 95 Resets (RST) - clear the status register to be able to store a new error. After power up the status reg- ister needs to be cleared before any valid data can be read out. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 96 Scrub Pending (PEN) - Indicates when a line scrub operation is pending. When the scrubber is dis- abled, writing ‘1’ to this bit scrubs one line. Scrub Enable (EN) - Enables / disables the automatic scrub functionality. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 97 Error injection register Table 79. 0x38 - L2CEINJ - L2C Error injection register ADDR R INJ 31: 2 Error Inject address (ADDR) RESERVED Inject error (INJ) - Set to ‘1’ to inject a error at “address”. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 98 Enabled SPLIT response (SPLIT) - When set the cache will issue a AMBA SPLIT response on cache miss RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 99 Access field (ACC) - 00: uncached, 01: write-through 15: 2 Address mask (MASK) - Only bits set to 1 will be used during address comparison Write-protection (WP) - 0: disabled, 1: enabled Access control field (AC) -. 0: disabled, 1: enabled GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 100: Sdram Memory Controller With Reed-Solomon Edac

    RMW cycle in the write case, and a read cycle in the read case. In this device, this case only happens when the Level-2 cache is disabled or set to write-through mode. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 101: Sdram Back-End Operation

    Table 84. SDRAM example programming SDRAM settings 100 MHz, CL=2; TRP=0, TCAS=0, TRFC=4 100 MHz, CL=3; TRP=0, TCAS=1, TRFC=4 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 102 TER command should be generated at the same time to update the mode register. The mode register is programmed as shown in table 86. Table 86. SDRAM controller mode register programming Mode register bit 12 .. 10 (reserved) Op Mode CAS Latency Burst length Controller setting EN2T 0 EN2T GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 103 Bank WRITE Bank Col+2 (WRITE) 0 Bank (Col+2) WRITE Bank Col+3 WRITE Bank Col+2 WRITE Bank Col+4 (WRITE) 0 Bank (Col+4) Bank Col+5 (PCH) Bank (Col+4) (Bank) Col+6 Bank Col+6 (Bank) (Col+6) Bank Col+6 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 104: Fault-Tolerant Operation

    Table 91. Mode Ax4 interleaving pattern (32-bit data width) 95:80 79:76 75:72 71:68 67:64 63:32 31:28 27:24 23:20 19:16 15:12 11:8 Table 92. Mode Bx2 interleaving pattern (32-bit data width) 95:80 79:76 75:72 71:68 67:64 63:32 31:28 27:24 23:20 19:16 15:12 11:8 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 105 When code B is used instead of code A, the upper half of the checkbits become unused. The controller supports switching in this part of the data bus to replace another faulty part of the bus. To do this, one GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 106 Note that during this sequence, it is possible for the system to operate and other masters can both read and write to memory while the regeneration is ongoing. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 107: Registers

    0x08 - 0x1C Reserved 0x20 Mux Configuration Register (MUXCFG) 0x24 Mux Diagnostic Address register (FTDA) 0x28 FT Diagnostic Checkbit register (FTDC) 0x2C FT Diagnostic Data register (FTDD) 0x30 FT Code Boundary Register (FTBND) 0x34 - 0xFF Reserved GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 108: Sdram Configuration Register

    Read-only. Affected by value of MEM_IFWIDTH bootstrap signal. 14: 0 Refresh counted reload value (RFLOAD) - The period between each AUTO-REFRESH command - Calculated as follows: tREFRESH = ((reload value) + 1) / SYSCLK GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 109 SDRAM bus. Bus parking is used to guarantee defined levels on the data bus that would otherwise be left floating and avoids the need of external pull-ups on the data bus. This functionality is only available in GR740 silicon revision 1. In revision 0 the field is read-only and tied to ’0’.
  • Page 110 10.6.4 FT diagnostic address register Table 98. 0x24 - FTDA - FT diagnostic address register FTDA 31: 2 Address to memory location for checkbit read/write (FTDA) - 64/32-bit aligned for checkbits/data 1: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 111 10.6.7 FT boundary address register Table 101.0x30 - FTBND - FT boundary address register FTBND(31:3) RESERVED 31: 3 Code boundary address (FTBND) - 64-bit aligned. Field contains address bits 31:3. Bits 2:0 are always zero. 2: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 112: Memory Scrubber And Ahb Status Register

    When the CE bit is set, the interrupt routine can acquire the address containing the correctable error from the failing address register and correct it. When it is finished it resets the CE bit and the monitor- ing becomes active again. Interrupt handling is described in detail hereunder. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 113 Before running the initialization, the pattern to be written to memory should be written into the scrub- ber initialization data register. The pattern has the same size as the burst length, so the corresponding number of writes to the initialization data register must be made. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 114 The scrubber can work over two non-overlapping memory ranges. This feature is enabled by writing the start/end addresses of the second range into the scrubber’s second range start/end registers and set- ting the SERA bit in the configuration register. The two address ranges should not overlap. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 115: Registers

    Configuration register 0x18 Range low address register 0x1C Range high address register 0x20 Position register 0x24 Error threshold register 0x28 Initialization data register 0x2C Second range start address register 0x30 Second range end address register GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 116 11.3.2 AHB failing address register Table 104.0x04 - AHBFAR - AHB Failing Address Register AHB FAILING ADDRESS 31: 0 AHB failing address (AHB FAILING ADDRESS) - The HADDR signal of the AHB transaction that caused the error. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 117 Needs to be cleared (by writing zero) before a new task completed interrupt can occur. 12: 5 RESERVED 4: 1 Burst length (BURSTLEN) - 2-log of AHB bus cycles; “0001”=2 Current state (ACTIVE) - 0=Idle, 1=Running GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 118: Configuration Register

    Table 109.0x1C - RANGEH - Range high address register RHADDR 0b11111 31: 0 Scrubber range high address (RHADDR) - The highest address in the range to be scrubbed The address bits below the burst size alignment are constant ‘1’ GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 119 Initialisation data (DATA) - Part of data pattern to be written in initialisation mode. A write opera- tion assigns the first part of the buffer and moves the rest of the words in the buffer one step. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 120 RHADDR 0b11111 31: 0 Scrubber range high address (RHADDR) - The highest address in the range to be scrubbed (if CONFIG.SERA = 1) The address bits below the burst size alignment are constant ‘1’ GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 121: Iommu - Bridge Connecting Master I/O Ahb Bus

    IOPTE when IOMMU protection is enabled. Otherwise the Master configuration register for a master selects which bus accesses from the master will be propagated to. The bus selection is valid even if the IOMUU is disabled via the control register’s EN bit. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 122 Incremental read burst of same access size as on slave interface, the length is the to non-prefetchable area same as the length of the incoming burst. The master interface will insert BUSY cycles between the sequential accesses. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 123 However, the core must complete the write operation on the master side before it can handle a new access on the slave side. If the core has not GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 124: General Access Protection And Address Translation

    It is possible for masters to access the bridge’s register interface through the bridge. In this case the bridge will perform an access to itself over the Processor and Slave I/O AHB buses. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 125: Access Protection Vector

    4WORD (128-bit) accesses, the lowest page is protected by bit 127 in the accessed word. This allows the same bit vector layout regardless of access size used by the IOMMU to fetch bit vector data. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 126 This may not be wanted in systems where interference between groups of masters should be minimized. In order to minimize inter-group interference, the core can use the group ID in the set address, this functionality is called group-set- addressing: GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 127: Io Memory Management Unit (Iommu) Functionality

    TMASK[31:26] will be inhibited. The table also shows the number of pages within the decoded range and the memory required to hold the translation information (page tables) in main memory. The pgsz value is the value of the PGSZ field in the control register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 128 ERROR response (not applicable when the access is a posted write). If the incoming access is within the range specified by ITR/TMASK, the core will use the incoming IO address to index the page table containing the address translation information for the master/IO GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 129 Bits of physical address needed to identify one position depending on page size size in size in bits IOPTEs 4 KiB 8 KiB 16 KiB 32 KiB 64 KiB 128 KiB 256 KiB 512 KiB GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 130: Fault-Tolerance

    A detected error will also be reported via the core’s status register and the core also signals errors via its statistic output. Errors can be injected in the Access Protection Vector cache and IOMMU TLB via the Data and Tag RAM Error Injection registers. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 131: Statistics

    OS B. Note that since an OS is able to flush the TLB/cache it is able to impact the I/O performance of masters assigned to other OS instances. Also note that care must be taken when clearing status bits and setting the mask register that controls interrupt generation. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 132: Registers

    * Register is duplicated in ASMP register block at offset 0x1000 + register offset. The number of ASMP register blocks is four. ASMP register block n starts at offset n*0x1000. Register is only writable if allowed by the corresponding ASMP access control register field. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 133 Value of GRPS is 7, the core supports eight groups. Numbers of masters (MSTS) - Number of masters that the core has been implemented to support - 1. Value of MSTS is 9, the core supports ten masters. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 134 This is also the line size for the TLB. TLB entries (TLBENT) - Read-only 5. Number of entries in the TLB. The number of entries is 2 BENT = 32. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 135 After writing this bit software should read back the value. The change has not taken effect before the value of this bit has changed. The bit transition may be blocked if the core is in diagnostic access mode or otherwise occupied. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 136 Flush (F) - When this bit is written to ‘1’ the core’s internal cache will be flushed. This bit will be reset to ‘0’ when a flush operation has completed. A flush operation also affects the FL and FC fields in the Status register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 137: Interrupt Mask Register

    Status register transitions from ‘0’ to ‘1’. Translation Error Interrupt (TEI) - If this bit is set to ‘1’ an interrupt will be generated when the TE bit in the Status register transitions from ‘0’ to ‘1’. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 138 Memory AHB bus. Note that the value in this field affects bus selection even if the IOMMU is dis- abled. Group assignment for master - Master n’s group assignment field is located at register address offset 0x40 + n*0x4. This field specifies the group to which a master is assigned. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 139 Diagnostic cache access data and tag registers. Changing this field invalidates the contents of the data and tag registers. * This register can only be accessed if STATUS.DE bit in is set to 1 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 140 Table 144.0xEC - TERRI - Tag RAM error injection register TPERRINJ 31:0 Tag RAM Parity Error Injection (TPERRINJ) - Bit TPERRINJ[n] in this register is XOR:ed with the parity bit for tag bits [7+8*n:8*n] in the tag RAM. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 141 Group control registers that are writable from an ASMP register block. If GRPACCSZCTRL[i] in the ASMP access control register at offset 0x100 + n*0x4 is set to ‘1’ then Group control register i is writable from ASMP register block n. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 142: Spacewire Router

    SpaceWire link interfaces using on-chip LVDS. The AMBA ports transfer characters from and to an AHB bus using DMA. The different port types are described in further detail in sections 13.3, 13.4 and 13.5. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 143 Group adaptive routing can be used to map specific addresses to a group of output ports. Incoming packets with such addresses are automatically routed to the first port in the group that is not busy. It GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 144 Note that it is not possible to access the configuration port of the router from a port that has static rout- ing enabled. 13.2.10 Spill-if-not-ready The spill-if-not-ready feature can be enabled individually for each physical and logical address by configuring the corresponding RTR.RTACTRL.SR bit. When enabled, an incoming packet is spilled GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 145 1. The link interface is not already trying to start (RTR.PCTRL.LS = 0). 2. The link is not disabled (RTR.PCTRL.LD = 0). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 146 The timeout period depends on the system clock frequency and is calculated as follows: <timeout period> = (<clock period> x (RTR.PRESCALER+1)) x RTR.PTIMER Sub-sections 13.2.15.1 through 13.2.15.4 clarifies the behaviour of the timers for different scenarios that can occur when a packet arrives. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 147 RTR.TC value plus one (modulo 64), the time-code is forwarded to all the other ports. The time- code is not sent out on the port on which it arrived. More details about the sending and receiving of time-codes through the AMBA ports are given in section 13.4.3. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 148 2. If the received code is an interrupt code, the RTR.PCTRL2.IR bit for the port must be set to 1. If the received code is an interrupt acknowledgment code or extended interrupt code, the RTR.PCTRL2.AR bit for the port must be set to 1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 149 RTR.ISR0 / RTR.ISR1 bit is started and reloaded with the value from the RTR.ISRC- TIMER register every time a received distributed interrupt code makes the RTR.ISR0 / RTR.ISR1 bit change its value. Until the timer has expired, the corresponding RTR.ISR0 / RTR.ISR1 bit is not GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 150 Just as the router ports, the auxiliary interface has enable / disable bits for time-codes (RTR.RTRCFG.AT) and interrupt codes (RTR.RTRCFG.AI), which must be set to 1 in order to trans- mit / receive codes. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 151 There is also an option of having automatic scrub- bing (see section 13.2.22.1). For the FIFOs within the AMBA ports there is an option to spill the ongoing packet when an error occurs. This is controlled by the RTR.AMBACTRL.ME bit. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 152: Spacewire Ports

    This is done based on the maximum value of 56 outstanding credits and the currently free space in the receive FIFO. FCTs are sent out as long as GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 153 <link-rate in Mbits/s> = <frequency in MHz of internal SpaceWire clock> / (RTR.PCTRL.RD+1) The value in RTR.PCTRL.RD only affects the link-rate in run-state and does not affect the 6.4 us or 12.8 us timeouts values. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 154: Amba Ports

    13.4 AMBA ports The AMBA ports are Cobham Gaisler’s GRSPW2 controller with the SpaceWire codec removed. Thus, the same drivers that are provided for the GRSPW2 can also be used for an AMBA port of the router. Only one additional driver is needed, which handles the setup of the registers within the con- figuration port.
  • Page 155 Distributed interrupt codes that are received by an AMBA port can be programmed to generate AMBA interrupts as well as tick out-pulses that are routed to the GPTIMER units for time latching (see section 5.9). See section 13.4.8 for details about these features. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 156 A control bit in the DMA channel control register determines whether the channel should use default address and mask registers for address comparison or the channel’s own registers. Using the default register, the same GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 157 If all channels use the default registers they will accept the same address range and the enabled channel with the lowest number will receive the packet. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 158 24: 0 Packet length (PACKETLENGTH) - The number of bytes received to this buffer. Only valid after EN has been set to 0 by the GRSPW. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 159 CRC error. This means that the port can indicate a data CRC error even if the data field was correct but the header CRC was incorrect. Thus, a CRC data error is only determinate when the HC bit is zero. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 160 The number of bytes to be transmitted and a pointer to the data has to be set. There are two different length and address fields in the transmit descriptors because there are separate pointers GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 161 7: 0 Header length (HEADERLEN) - Header Length in bytes. If set to zero, the header is skipped. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 162 The DMA control register contains a bit called Abort TX, which if set causes the current transmission to be aborted, that is, the packet is truncated and an EEP is inserted. This is only useful if the packet GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 163 If there is a mismatch and a reply has been requested, the error code in the reply is set to 3. Replies are sent if and only if the ack field is set to ‘1’. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 164 “Authorization failure” error code will be sent in the reply if a violation was detected even if the length field was zero. Also note that no data is sent in the reply if an error was detected, i.e. if the sta- tus field is non-zero. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 165 Executed normally. No restric- menting tions. Reply is sent. address. Not used Does nothing. No reply is sent. Not used Does nothing. No reply is sent. Not used Does nothing. Reply is sent with error code 2. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 166 Write, single Executed normally. Length must address, ver- be 4 or less. Otherwise nothing is ify before done. Same alignment restric- writing, no tions apply as for rmw. No reply acknowledge is sent. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 167 As mentioned above, the APB interface provides access to the user registers, which are 32-bits wide. Accesses to this interface are required to be aligned word accesses. The result is undefined if this restriction is violated. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 168 7 in section 2.3. An identical set of registers described in this section exists for each AMBA port. The used register layout is explained in section 1.11. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 169 * One identical register per DMA channel. Register is only described once ** Each AMBA port is allocated a 4 KiB memory area in the GR740 memory map. The router registers are aliased within this memory range which means that an access to offset 0x104 or 0x204 .. 0xF04 all access the same register. To ensure software should only access GR740-UM-DS, Nov 2017, Version 1.7...
  • Page 170 A tick can also be generated by assert- ing the tick_in signal. Interrupt Enable (IE) - If set, an interrupt is generated when bit 8 is set and its corresponding event occurs. 2: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 171 Default address (DEFADDR) - Default address used for node identification on the SpaceWire network. Reset value: 254. Table 158. 0x10 - RTR.AMBADKEY - AMBA port Destination key RESERVED DESTKEY 0x00 31: 8 RESERVED 7: 0 Destination key (DESTKEY) - RMAP destination key. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 172 Time counter (TIMECNT) - The current value of the system time counter. It is incremented for each tick-in and the incremented value is transmitted. The register can also be written directly but the written value will not be transmitted. Received time-counter values are also stored in this register GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 173 SW-node to read a new descriptor and try to transmit the packet it points to. This bit is automatically cleared when the SW-node encounters a descriptor which is disabled. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 174 MASK before the address check. 7: 0 Address (ADDR) - Address used for node identification on the SpaceWire network for the corresponding dma channel when the EN bit in the DMA control register is set. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 175 ‘0’. Writing a ‘0’ has no effect. 5: 0 Transmit distributed interrupt code (TXINT) - The distributed interrupt code that will be sent when the reg- ister RTR.AMBAINTCTRL.II is written with 1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 176 This bit is set to 1 when an extended interrupt code that was sent by software time out, i.e after the dura- tion of a timeout period (specified in the RTR.ISRTIMER register), and if the corresponding bit in the RTR.AMBAINTMSK1 register is set. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 177: Configuration Port

    For write commands the Verify Data Before Write bit in the Instruction field must be set to 1. How the RMAP target handles commands that does not meet the above requirement is detailed in sec- tions 13.5.1.2 and 13.5.1.4. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 178 Error code is also saved in the RTR.PCTRLCFG.EC field. don’t verify before write, send reply Write, single Write operation performed if the requirements in section address, verify 13.5.1.1 are met. before writing, no reply GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 179 “11” then the bit RTR.PSTSCFG.PT is set. For the value “00” (indicat- ing a reply), no bit in RTR.PSTSCFG is set, since the RMAP standard [RMAP] does not specify that such an event should be recorded. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 180 AHB slave, RMAP target. Note that since the AHB slave has higher priority than the RMAP target, it is possible to read and write to GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 181 RTR.PCTRL2CFG 0x00000984 - Port control 2, ports 1-12 (SpaceWire ports and AMBA ports) RTR.PCTRL2 0x00000930 0x000009D0 - RESERVED 0x000009FC 0x00000A00 Router configuration / status RTR.RTRCFG 0x00000A04 Time-code RTR.TC 0x00000A08 Version / instance ID RTR.VER GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 182 * Physical address 0 (configuration port), and physical addresses 13-31 (non existing ports) does not have an RTR.RTP- MAP or RTR.RTACTRL register, and are therefore RESERVED. ** Physical address 0 (configuration port), and physical addresses 13-31 (non existing ports) does not have an RTR.RTCOMB register, and are therefore RESERVED. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 183 Header deletion (HD) - Enables / disabled header deletion for the corresponding logical address. For physical addresses, header deletion is always enabled, and this bit is constant 1. Reset value for logical addresses is N/R. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 184 1 for distributed interrupt codes to be sent / received. See section 13.2.18 for a description of distributed interrupt code distribution. Reset value depends on bootstrap signals, as described in section 3.1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 185 Link start (LS) - Start the link interface FSM. This bit is only available for the SpaceWire ports. Link disabled (LD) - Disable the link interface FSM. This bit is only available for the SpaceWire ports. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 186 0. Writing 0 has no effect. 3: 0 SpaceWire Plug-and-Play Error code (PC) - Shows the four least significant bits of the latest non-zero Space- Wire Plug-and-Play status code. If zero, no error has occurred. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 187 Disconnect error (DE) - Set to 1 when a disconnect error has occurred. This bit is only available for the Space- Wire ports. Parity error (PE) - Set to 1 when a parity error has occurred on. This bit is only available for the SpaceWire ports. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 188 RTR.PCTRL2CFG.SM field when checking if a received time-code / distributed interrupt code should spill an ongoing RMAP / SpaceWire Plug-and-Play reply. Overrun timeout enable (OR) - Enables spilling due to overrun timeouts for RMAP / SpaceWire Plug-and-Play replies. See section 13.2.15 for details. 14: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 189 ISR bit. If set to 0, the ISR change timers are not used, and an ISR bit is allowed to change value again as soon as the previous interrupt code / interrupt acknowledgement code has been distributed. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 190 7: 6 Time-control flags (CF) - The current value of the router’s time-code control flags (bits 7:6 of the latest valid time-code received). 5: 0 Time-counter (TC) - Current value of the router’s time counter. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 191 The prescaler runs on the system clock, and a tick is generated every RTR.PRESCALER.RL+1 CLK cycle. The minimum value of this field is 250. Trying to write a value less than that will result in 250 being written. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 192 A bit in this field will only be set to 1 for a generated interrupt if the port’s corresponding bit in RTR.IPMASK is set, as well as the error types corresponding bit in RTR.IMASK, are set. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 193 A bit value of 0 indicates either that no interrupt code with the corresponding interrupt number has been received, or that the previous interrupt code was either acknowledged or timed out. This regis- ter should be normally only be used for diagnostics and / or FDIR. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 194 Each time an ISR bit change value, the corresponding ISR change timer is started and reloaded with the value of this field. See section 13.2.18 for details on interrupt code distribution. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 195 Constant value of 0x00 = no packet counters. 4: 0 Port character counter bits (CC) - Specifies the number of bits in the port’s incoming / outgoing character count- ers. Constant value of 0x00 = no character counters. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 196 Maximum packet length (ML) - Maximum length of packets for which the corresponding port is the input port. This field is only used when the RTR.PCTRL.PL bit (RTR.PCTRLCFG.PL for port 0) is set to 1. See section 13.2.16 for details. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 197 NOTE: This register is not available via on-chip AHB slave interface. Only available through RMAP. Packet distribution (PD) - This field is a double mapping of the RTR.RTPMAP.PD field. See table 175. NOTE: See note for RTR.RTPMAP (table 175). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 198 Status field set to 0xF1. An access (read, write, or compare-and-swap) to an undefined or unsupported field in one of the defined field sets, within the Device Information service, is not GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 199 PROD 0x0003 0x0740 31: 16 Vendor ID (VEND) - SpaceWire vendor ID assigned to Cobham Gaisler. Constant value of 0x0003. 15: 0 Product ID (PROD) - Product ID assigned to GR740. Constant value of 0x0740 GR740-UM-DS, Nov 2017, Version 1.7...
  • Page 200 For the SpaceWire ports (ports 1-8), the corresponding bit will be set to 1 if the link interface is in run-state and the port is not disabled through the Port Control register (RTR.PCTRL.DI = 0). For the AMBA ports, the bit is set to 1 if RTR.PCTRL.DI = 0. RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 201 Reply address (RA) - Shows byte 8-11 of the Reply Address from the last successful compare-and-swap com- mand that set to the Device ID field. If the Reply Address was eight bytes or less, then this field is zero. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 202 Table 221. 0x00004000 - RTR.PNPVSTRL - SpaceWire Plug-and-Play - Vendor String Length 15 14 RESERVED 0x00000 0x0000 31: 15 RESERVED 14: 0 Vendor string length (LEN) - Constant value of 0, indicating that no vendor string is present. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 203 Table 224. 0x0000C000 - RTR.PNPACNT - SpaceWire Plug-and-Play - Application Count RESERVED 0x000000 0x00 31: 8 RESERVED 7: 0 Application count (AC) - Constant value of 0, indicating that no applications can be managed by using Space- Wire Plug-and-Play. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 204: Gigabit Ethernet Media Access Controller (Mac)

    14.1 Overview Cobham Gaisler’s Gigabit Ethernet Media Access Controller (GRETH_GBIT) provides an interface between an AMBA-AHB bus and an Ethernet network. It supports 10/100/1000 Mbit speed in both full- and half-duplex. The AMBA interface consists of an APB interface for configuration and control and an AHB master interface which handles the dataflow.

  • Page 205: Tx Dma Interface

    Late collision (LC) - A late collision occurred during the transmission (1000 Mbit mode only). Attempt limit error (AL) - The packet was not transmitted because the maximum number of attempts was reached. Underrun error (UE) - The packet was incorrectly transmitted due to a FIFO underrun error. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 206 The enable bit should be used as the indicator when a descriptor can be used again, which is when it has been cleared by the GRETH_GBIT. There are three bits in the GRETH_GBIT status register that GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 207: Rx Dma Interface

    (4 B) is never stored to memory so it is not included in this number. If the interrupt enable (IE) bit is set, an interrupt will be generated when a packet has been received to this buffer (this requires GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 208 GRETH_GBIT the pointer field is incre- mented by 8 to point at the next descriptor. The pointer will automatically wrap back to zero when the GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 209 The error bits are never set if the corre- sponding packet type is not detected. The core does not support checksum calculations for TCP and GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 210: Mdio Interface

    EDCL transmitter when the operation is finished. It shares the Ethernet transmitter with the transmitter DMA-engine but has higher priority. 14.6.2 EDCL protocols The EDCL accepts Ethernet frames containing IP or ARP data. ARP is handled according to the pro- tocol specification with no exceptions. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 211 The default value of the EDCL IP and MAC addresses are shown in the table below. The addresses can be changed by software: Table 232.EDCL addresses Core MAC address IP address GRETH_GBIT 0 00:50:C2:75:A3:30 to 3F 192.168.0.16 to 31 GRETH_GBIT 1 00:50:C2:75:A3:40 to 4F 192.168.0.32 to 47 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 212: Media Independent Interfaces

    Table 234.Signals in GMII and MII. MII and GMII GMII Only txd[3:0] txd[7:4] tx_en rxd[7:4] tx_er gtx_clk rx_col rx_crs rxd[3:0] rx_clk rx_er rx_dv GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 213: Registers

    MDIO Control/Status 0x14 Transmit descriptor pointer 0x18 Receiver descriptor pointer 0x1C EDCL IP 0x20 Hash table msb 0x24 Hash table lsb 0x28 EDCL MAC address MSB 0x2C EDCL MAC address LSB 0x30 - 0xFF RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 214 GRETH_GBIT will read new descriptors and as soon as it encounters a disabled descriptor it will stop until TE is set again. This bit should be written with a one after the new descriptors have been enabled. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 215 The two most significant bytes of the MAC Address. Not Reset. Table 239. 0xC - GRETH_GBIT MAC address LSB. Bit 31 downto 0 of the MAC Address 31: 0 The 4 least significant bytes of the MAC Address. Not Reset. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 216 Receiver descriptor table base address (BASEADDR) - Base address to the receiver descriptor table.Not Reset. 9: 3 Descriptor pointer (DESCPNT) - Pointer to individual descriptors. Automatically incremented by the Ethernet MAC. 2: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 217 The 4 least significant bytes of the EDCL MAC Address. Reset value:  31: 0 GRETH GBIT 0: 0x0075A330. GRETH GBIT 1: 0x0075A340 The four lowest bits of the EDCL IP address might be taken from GPIO inputs, see section 3.1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 218: 32-Bit Pci/Ahb Bridge

    APB slave interface. The implementation described by this datasheet has the following characteristics: • The PCI vendor 0x1AC8 and device ID 0x0740 • The PCI class code 0x0B4000 and revision ID 0x00 • 32-bit PCI initiator interface. • 32-bit PCI target interface • DMA controller GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 219 Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line Table 249.0x00 - Device ID and Vendor ID register 16 16 15 Device ID Vendor ID 0x0061 0x1AC8 31: 16 Device ID, 0x0740 15: 0 Vendor ID, 0x1AC8 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 220 SERR# Enable (SE) NOT IMPLEMENTED, Returns zero. Parity Error Response (PER) NOT IMPLEMENTED, Returns zero. Memory Write and Invalidate Enable (MWI) NOT IMPLEMENTED, Returns zero. Bus Master (BM) Memory Space (MS) NOT IMPLEMENTED, Returns zero. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 221 Prefetchable (PF) - zero indicating non-prefetchable. The two first BARs have the prefetchable bit set. The third BAR is not prefetchable and is suitable for mapping system registers. 2: 1 Type - Returns zero. Memory Space Indicator (MS) - Returns zero GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 222 Interrupt Pin Interrupt Line INTA 31: 24 ) - NOT IMPLEMENTED, Returns zero Max_Lat 23: 16 ) - NOT IMPLEMENTED, Returns zero Min_Gnt 15: 8 Interrupt Pin - Indicates INTA 7: 0 Interrupt Line GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 223 - Translates an access to the Extended PCI Con- Extended PCI Configuration Space to AHB address mapping figuration Space (excluding the address range for the internal register located in this configuration space) to a AHB address. 7: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 224: Operation

    PCI commands that are supported, see the PCI target section and for burst limitations see the Burst section. 15.3.2 FIFOs The core has separate FIFOs for each data path: PCI target read, PCI target write, PCI master read, PCI master write, DMA AHB-to-PCI, and DMA PCI-to-AHB. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 225 15.3.4 PCI configuration cycles Accesses to PCI Configuration Space are not altered by the endianess settings. The PCI Configuration Space is always defined as little-endian (as specified in the PCI Local Bus Specification). This means GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 226 An asserted PCI system host signal makes the PCI target respond to configuration cycles when no IDSEL signal is asserted (none of AD[31:11] are asserted). This is done for the PCI master to be able to configure its own PCI target. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 227: Pci Initiator Interface

    IDSEL: This field is decoded to drive PCI AD[IDSEL+10]. Each of the signals AD[31:11] are sup- pose to be connected (by the PCI back plane) to one corresponding IDSEL line. 10: 8 FUNC: Selects function on a multi-function device. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 228: Pci Target Interface

    Memory Write, Memory Write and Invalidate: These command are handled similarly and are transferred to the AMBA AHB bus as a single or burst access depending on the length of the PCI access (a single or burst access). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 229: Dma Controller

    This discard time out can be enabled via the “AHB IO base address and PCI bus config” register located in the core specific Extended PCI Configuration Space. 15.6 DMA Controller The DMA engine is descriptor based and uses two levels of descriptors. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 230 RESERVED Type RESERVED Data descriptor count Channel descriptor enable. This bit must be set to 1 in GR740 silicon revision 0. 30: 25 RESERVED 24: 22 Channel ID. Each DMA channel needs a ID to determine the source of a DMA interrupt.
  • Page 231 Each data descriptor has an interrupt enable bit which determine if the core should generate a interrupt when the descriptor has been executed. The DMA engine asserts the same interrupt as the PCI core. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 232: Pci Trace Buffer

    The core is capable of sampling the PCI INTA-D signals and forwarding the interrupt to the APB bus. The “host INT mask” field in the control register is used to only sample the valid PCI INT signal(s). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 233: Reset

    PCI trace buffer: AD mask 0x90 PCI trace buffer: Ctrl signal pattern 0x94 PCI trace buffer: Ctrl signal mask 0x98 PCI trace buffer: AD state 0x9C PCI trace buffer: Ctrl signal state 0xA0 - 0xFF RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 234 Device interrupt mask - When bit[n] is set dirq[n] is unmasked 3: 0 Host interrupt mask - bit[3] = 1: unmask INTD. bit[2] = 1: unmask INTC. bit[1] = 1: unmask INTB. bit[0] = 1: unmask INTA. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 235 = 0: indicates that INTB is asserted. bit[0] = 0: indicates that INTA is asserted. 7: 5 RESERVED 4: 2 (FIFO depth) FIFO depth (FDEPTH) - Words in each FIFO = 2 1: 0 Number of FIFOs (FNUM) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 236 DMA active (ACTIVE) DMA disable/stop (DIS) - Writing ‘1’ to this bit disables the DMA. Interrupt enable (IE) - (Guarded by bit[31], safety guard). DMA enable/start (EN) - Writing ‘1’ to this bit enables the DMA GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 237 31) are implemented. Bits not implemented returns zero. The mapping register for AHB master 0 is located at offset 0x40, AHB master 1 at offset 0x44, and so on up to AHB master 15 at offset 0x7C. Mapping registers are only implemented for existing AHB masters. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 238 - 2). 15.10.12 PCI trace AD pattern register Table 283.0x88 - TADP - PCI trace AD pattern register PCI AD pattern 31: 0 PCI AD pattern to trig on GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 239 31: 20 RESERVED 19: 3 Mask for the Ctrl signal pattern. When mask bit[n] = 0 pattern bit[n] will always be a match. 2: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 240 Table 288.0x9C - TCS - PCI trace PCI Ctrl signal state register 20 19 16 15 14 13 12 11 10 RESERVED CBE[3:0] 31: 20 RESERVED 19: 3 The state of the PCI Ctrl signals 2: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 241: Mil-Std-1553B / As15531 Interface

    Bus A txenA txA_P txA_N rxA_P rxA_N rxenA GR1553B Bus B txenB txB_P txB_N rxB_P rxB_N rxenB Terminal boundary Figure 19. Interface between core and MIL-STD-1553B bus (dual-redundant, transformer coupled) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 242: Operation

    Loop-back checking logic checks that each transmitted word is also seen on the receive inputs. If the transmitted word is not echoed back, the transmitter stops and signals an error condition, which is then reported back to the user. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 243: Bus Controller Operation

    ‘0’, if it succeeds on bus B, the swap register bit is set to ‘1’. If the trans- fer fails, the bus swap register is set to the opposite value. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 244 This can be used for RT-to-RT transfers where the BC is not interested in the data transferred. 0x0C Result word, written by core (see table 292) Unused GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 245 Second RT Subaddress for RT-to-RT transfer (RTSA2) for different transfer types. 15:11 RT Address (RTAD1) Note that bits 15:0 correspond to the (first) Transmit/receive (TR) command word on the 1553 bus RT Subaddress (RTSA1) Word count/Mode code (WCMC) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 246 (1, 3-8) Read  Broadcast 0 or 31 (*) Don’t care Don’t care Mode code Mode, BC-to-RT (17/20/21) (2 bytes) (*) The standard allows using either of subaddress 0 or 31 for mode commands. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 247 Status Condition Code (STCC) - Mask with bits corresponding to status value of last transfer Note that you can get a constant true condition by setting MODE=0 and STCC=0xFF, and a constant false condition by setting STCC=0x00. 0x800000FF can thus be used as an end-of-list marker. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 248: Remote Terminal Operation

    Descriptor ctrl/stat SA N Receive descr. ptr Data buffer ptr. Receive buffer Next pointer Descriptor ctrl/stat SA N+1 Data buffer ptr. Receive buffer Next pointer Subaddress table Figure 20. RT subaddress data structure example diagram GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 249 Enabled always, can not be logged or disabled. 10011 Transmit BIT word Responds with BIT word from RT Status Words 15:14 Register 10100 Selected transmitter No built-in action shutdown 10101 Override selected No built-in action transmitter shutdown GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 250: Event Log

    Interrupt on transmit transfers (TXIRQ) - Each transmit transfer will cause an interrupt (only if TXEN,TXLOG=1) 4 : 0 Maximum legal transmit size (TXSZ) from this subaddress - in 16-bit words, 0 means 32 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 251 011 = Protocol error (improperly timed data words or decoder error) 100 = The busy bit or message error bit was set in the transmitted status word and no data was sent 101 = Transfer aborted due to loop back checker error GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 252: Bus Monitor Operation

    For the codec clock domain, a 20 MHz clock must be supplied. The AMBA clock can be at any frequency but must be at a minimum of 10 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 253: Registers

    BC Timer register 0x54 (Reserved) 0x58 BC Transfer-triggered IRQ ring position 0x5C BC Per-RT bus swap register 0x60...0x67 (Reserved) 0x68 BC Transfer list current slot pointer 0x6C BC Asynchronous list current slot pointer 0x70...0x7F (Reserved) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 254 15: 11 RESERVED RT Table access error (RTTE) RT DMA Error (RTD) RT transfer-triggered event interrupt (RTEV) 7: 3 RESERVED BC Wake-up timer interrupt (BCWK) BC DMA Error (BCD) BC Transfer-triggered event interrupt (BCEV) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 255 Schedule address low bits (SCADL) - Bit 8-4 of currently executing (if SCST=001) or next schedule descrip- tor address 2: 0 Schedule state (SCST) - 000=Stopped, 001=Executing command, 010=Waiting for time slot, 011=Sus- pended, 100=Waiting for external trigger GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 256 31 : 0 The current write pointer into the transfer-tirggered IRQ descriptor pointer ring. Bits 1:0 are constant zero (4-byte aligned) The ring wraps at the 64-byte boundary, so bits 31:6 are only changed by user GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 257 Bus B shutdown (SHDB) - Reads ‘1’ if bus B has been shut down by the BC (using the transmitter shutdown mode command on bus A) RT Running (RUN) - ‘1’ if the RT is listening to commands. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 258 Sync Data (SYD) - The value of the RT timer at the last sync or sync with data word mode command, if legal. 15 : 0 Sync Time (SYTM) - The data received with the last synchronize with data word mode command, if legal GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 259 0xFFFFFFFC 31 : 0 Mask determining size and alignment of the RT event log ring buffer. All bits “above” the size should be set to ‘1’, all bits below should be set to ‘0’ GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 260 Table 332. 0xC8 - BMRTAF - GR1553B BM RT Address filter register ADDRESS FILTER MASK 0xFFFFFFFF Enables logging of broadcast transfers 30 : 0 Each bit position set to ‘1’ enables logging of transfers with the corresponding RT address GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 261 Table 335. 0xD4 -BMLBS - GR1553B BM Log buffer start BM LOG BUFFER START 0x00000000 31 : 0 Pointer to the lowest address of the BM log buffer (8-byte aligned) Due to alignment, bits 2:0 are always 0. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 262 31 : 24 Time tag resolution (TRES) - Time unit of BM:s time tag counter in microseconds, minus 1 23 : 0 Time tag value (TVAL) - Current value of running time tag counter GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 263: Can 2.0 Controllers With Dma

    Figure 21. Block diagram of one CAN controller The controller implements the following functions: • CAN protocol • Message transmission, filtering and reception • SYNC message reception • Status and monitoring • Interrupt generation • Redundancy selection GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 264: Interface

    The transmit channel operates on a circular buffer located in memory external to the CAN controller. The circular buffer can also be used as a straight buffer. The buffer memory is accessed via the AMBA AHB master interface. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 265 CAN core. If there is at least one additional CAN message available in the circu- lar buffer, a prefetch of this CAN message from the circular buffer to a local prefetch-buffer in the GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 266 (CanTxCTRL.ENABLE is cleared automatically to 0 b). The read pointer can be used to determine which message caused the AHB error. Note that it could be any of the four word accesses required to read a message that caused the AHB error. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 267: Reception

    The Tx, TxEmpty and TxIrq interrupts are only generated as the result of a successful message trans- mission, after the CanTxRD.READ pointer has been incremented. 17.6 Reception The receive channel is defined by the following parameters: • base address • buffer size GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 268 17.6.3 Location The location of the circular buffer is defined by a base address (CanRxADDR.ADDR), which is an absolute address. The location of a circular buffer is aligned on a 1 KiB address boundary. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 269 AHB bus will not be aborted, and no new message storage will be started. Note that only complete messages can be received from the CAN core. If the message is stored success- fully, the write pointer (CanRxWR.WRITE) is automatically incremented. Any associated interrupts will be generated. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 270: Global Reset And Enable

    This can be caused either by no unit sending on the CAN bus, or by random bits in message transfers. 17.8 Interrupt Three interrupts are implemented by the CAN interface: Index:Name:Description: IRQ Common output from interrupt handler TxSYNCSynchronization message transmitted (optional) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 271: Registers

    Receive Channel Address Register 0x308 Receive Channel Size Register 0x30C Receive Channel Write Register 0x310 Receive Channel Read Register 0x314 Receive Channel Interrupt Register 0x318 Receive Channel Mask Register 0x31C Receive Channel Code Register GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 272 Note that RSJ defines the number of allowed re-synchronization jumps according to the CAN stan- dard, being in the range 1 to 4. For SAM = 0b (single), the bus is sampled once; recommended for high speed buses (SAE class C). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 273 Note that ENABLE should be cleared to 0b to while other settings are modified, ensuring that the CAN core is properly synchronized. Note that when ENABLE is cleared to 0b, the CAN interface is in sleep mode, only outputting reces- sive bits. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 274 At the time the ENABLE is cleared to 0b, any ongoing message transmission is not aborted, unless the CAN arbitration is lost or communication has failed. Note that the ONGOING bit being 1b indicates that message transmission is ongoing and that config- uration of the channel is not safe. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 275 Note that it is not possible to fill the buffer. There is always one message position in buffer unused. Software is responsible for not over-writing the buffer on wrap around (i.e. setting WRITE=READ). The field is implemented as relative to the buffer base address (scaled with the SIZE field). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 276 Note that in the case an AHB bus error occurs during an access while fetching transmit data, and the CanCONF.ABORT bit is 1b, then the ENALBE bit will be reset automatically. At the time the ENABLE is cleared to 0b, any ongoing message reception is not aborted GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 277 Note that the WRITE field can be used to read out the progress of a transfer. Note that the WRITE field can be written to in order to set up the starting point of a transfer. This should only be done while the receive channel is not enabled. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 278 Table 358.0x31C - CanRxCODE - Receive Channel Code Register 29 28 28: 0 Acceptance Code (AC) - Used in comparison with the received message Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 279 Pending Interrupt Status Register[CanPISR]R • Pending Interrupt Register[CanPIR]R/W • Interrupt Mask Register[CanIMR]R/W • Pending Interrupt Clear Register[CanPICR]W Table 359.Interrupt Registers 17 16 15 14 13 12 11 10 Tx Rx Tx OR Off Pa Full GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 280 CONF.ABORT field setting. Note that the RxAHBErr interrupt is generated in such way that the corresponding read and write pointers are valid for failure analysis. The interrupt generation is independent of the Can- CONF.ABORT field setting. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 281: 17.10 Memory Mapping

    AHBErr AHB interface blocked due to AHB Error when 1b Reception Over run when 1b Bus Off mode when 1b PASS Error Passive mode when 1b Byte 00 to 07 Transmit/Receive data, Byte 00 first Byte 07 last GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 282: Bridge Connecting Slave I/O Ahb Bus To Processor Ahb Bus

    NONSEQ type. Since the master interface can not decide whether the splitted burst will continue on the slave side or not, the master bus is held by performing BUSY transfers. On the slave side the split- GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 283 Single read access to any area Access size <= Single access of same size 32-bits Single read access to any area Access size > Burst of 32-bit accesses. Length of burst: (access size)/(32 bits) 32-bits GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 284 Core waits for master to return. Other masters receive SPLIT responses. Master has been allowed into arbitration and per- forms address phase. Core keeps HREADY high Access data phase. Core has returned to idle state. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 285: Registers

    A prefetch operation ends at the address boundary defined by the prefetch buffer’s size The core implements posted writes, the number of cycles taken by the master side can only affect the next access. 18.3 Registers The bridge does not implement any registers. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 286: Fault-Tolerant 8/16-Bit Prom/Io Memory Interface

    (zero waitstate). Waitstates are added by extending the data2 phase. This is shown in figure 25 and applies to both consecutive and non-consecutive cycles. Only an even number of waitstates can be assigned to the PROM area. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 287 Figure 23. Prom non-consecutive read cyclecs. data1 data2 data1 data2 data promio_addr prom_cen promio_oen promio_data Figure 24. Prom consecutive read cyclecs. data1 data2 data2 data2 data promio_addr prom_cen promio_oen promio_data Figure 25. Prom read access with two waitstates. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 288: Memory Mapped Io

    (PROMIO_OEN) signals are delayed one clock to provide stable address before IO_SN is asserted. All accesses are performed as non-consecutive accesses as shown in figure 28. The data2 phase is extended when waitstates are added. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 289: 8-Bit And 16-Bit Prom Access

    Figure 30 shows an interface example with 8-bit PROM. Figure 31 shows an example of a 16-bit memory interface. EDAC is not supported for 16-bit wide memories and therefore the EDAC enable bit corresponding to a 16-bit wide area must not be set. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 290: 8- And 16-Bit I/O Access

    Slave I/O AHB bus will split larger accesses into bursts of 32-bit accesses. Note that all accesses to this memory controller traverses over the bridge connecting the Processor AHB bus to the Slave I/O bus. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 291: Memory Edac

    PROMIO_OEN and PRO- MIO_BRDYN must be asserted for at least 1.5 clock cycle. The use of PROMIO_BRDYN can be enabled separately for the PROM and I/O areas. It is recommended that PROMIO_BRDYN is GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 292 BRDYN is first asserted until it is visible internally. In figure 33 one cycle is added to the data2 phase. data1 data2 data2 lead-out promio_addr prom_cen/io_sn promio_oen promio_data promio_brdyn Figure 33. BRDYN (asynchronous) sampling. Lead-out cycle is only applicable for I/O-accesses. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 293: Registers

    APB Address offset Register 0x00 Memory configuration register 1 (MCFG1) 0x04 RESERVED 0x08 Memory configuration register 3 (MCFG3). 0x0C RESERVED 0x10 Memory configuration register 5 (MCFG5). 0x14 RESERVED 0x18 Memory configuration register 7 (MCFG7) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 294 During reset, the prom width (bits [9:8]) are set with value on general purpose I/O inputs, see section 3.1. The prom waitstates fields are set to 15 (maximum). External bus ready is disabled. All other fields are undefined. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 295 IO lead out (IOHWS) - Lead out cycles added to IO accesses are IOHWS(3:0)*2 22 : 14 RESERVED 13:7 ROM lead out (ROMHWS) - Lead out cycles added to ROM accesses are ROMHWS(6:4) ROMHWS(3:0)*2 6 : 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 296 Bus ready count (BRDYNCOUNT) - Counter value. If this register is written then the counter shall be written with the same value as BRDYNRLD. 15: 0 Bus ready reload value (BRDYNRLD) - Reload value for BRDYNCNT GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 297: General Purpose Timer Units

    Each timer can be reloaded with the value in its reload register at any time by writing a ‘one’ to the load bit in the control register. The last timer on GPTIMER 0 acts as a watchdog, driving the watch- dog output signal WDOGN when expired. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 298: Registers

    16 15 RESERVED SCALER 0xFFFF 31: 16 RESERVED 15: 0 Scaler value (SCALER) Table 371.0x04 - SRELOAD- Scaler reload value register 16 15 RESERVED SRELOAD 0xFFFF 31: 16 RESERVED 15: 0 Scaler reload value (SRELOAD) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 299 Position 4: Connectef to SpaceWire router tick out 3 Table 374.0xn0 where n selects the timer - TCNTVALn - Timer n counter value register TCVAL 31: 0 Timer Counter value (TCVAL) - Decremented by 1 for each prescaler tick. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 300 DSU is enabled via external signal DSU_EN = HIGH. Table 377.0xnC where n selects the timer - TLATCHn - Timer n latch register LTCV 31: 0 Latched timer counter value (LTCV): Valued latched from corresponding timer. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 301: Multiprocessor Interrupt Controller With Extended Asmp Support

    After system reset, all processors are connected to the first interrupt controller accessible at the core’s base address. Software can then use the Interrupt Controller Select Registers to assign processors to other (internal) interrupt controllers. After assignments have been made, it is recommended to freeze GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 302 When an interrupt is signalled on the interrupt bus, the interrupt controller will priori- tize interrupts, perform interrupt masking for each processor according to the mask in the correspond- ing mask register and forward the interrupts to the processors. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 303 ‘1’ to its status field. After reset, all processors except processor 0 are halted (unless DSU_EN is low and BREAK is high, as described in section 3.1). When the system is properly initialized, processor 0 can start the remaining processors by writing to their STATUS bits. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 304 Adding a read of the timestamp counter before this status register read can give an accurate view of the latency during interrupt handling. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 305 The interrupt controller can be used to start processor execution from a specified start address. The interface to accomplish this is different between GR740 silicon revision 0 and silicon revision 1. In GR740 revision 0, the following registers are available: •...

  • Page 306: Registers

    Address registers are visible and writable from the register space of all internal controllers. GR740 revision 1: Registers are available to allow starting a halted processor from an arbitrary 8 byte aligned entry point. The processor can be started with the same register write as when the entry point is written, or the processor can be started later using the regular multiprocessor status register bit.
  • Page 307 Interrupt map register 7 21.3.1 Interrupt level register Table 379.0x000 - ILEVEL - Interrupt level register 16 15 RESERVED IL[15:1] 31:16 Reserved 15:1 Interrupt Level n (IL[n]) - Interrupt level for interrupt n Reserved GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 308 16 15 EIC[31:16] IC[15:1] 31:16 Extended Interrupt Clear n (EIC[n]) - Writing ‘1’ to EIC[n] will clear interrupt n 15:1 Interrupt Clear n (IC[n]) - Writing ‘1’ to IC[n] will clear interrupt n Reserved GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 309 Number of CPUs (NCPU) - Number of CPUs in the system - 1 Broadcast Available (BA) - Set to ‘1’ if NCPU > 0. Extended boot registers available (ER) - Set to ‘0’ in GR740 silicon revision 0 and set to ’1’ in GR740 silicon revision ’1’.
  • Page 310 20 19 16 15 ICSEL0 ICSEL1 ICSEL2 ICSEL3 RESERVED 31: 16 Interrupt controller select for processor n (ICSEL[n]) - The nibble ICSEL[n] selects the (internal) interrupt controller to connect to processor n. 15: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 311 Table 391.0x0C0, 0x0C4, 0x0C8, 0x0CC - PEXTACK0-3 - Processor 0, 1, 2, 3 extended interrupt acknowledge register RESERVED EID[4:0] 31: 5 RESERVED 4: 0 Extended interrupt ID (EID) - ID (16-31) of the most recent acknowledged extended interrupt. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 312 Timestamp of Assertion (TASSERTION) - The current Timestamp Counter value is saved in this register when timestamping is enabled and the interrupt line selected by TSISEL is asserted. The time value used for stamping is the DSU timer, which is also available as the processor internal. up-counter. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 313 21.3.18 Processor reset start address / boot address register Note: The registers at 0x200 - 0x20C are different between GR740 silicon revision 0 and silicon revi- sion 1. Silicon revision 0 have Processor reset start address registers. Silicon revision 1 has Processor boot address registers and also the Error mode status register (described in section 21.3.7).
  • Page 314 GR740 21.3.19 Processor boot register Note: This register is only present in GR740 silicon revision 0. Table 398.0x240 - PBOOT - Processor boot register 20 19 16 15 RESERVED RESET[n] RESERVED BOOT[n] 31: 20 RESERVED 19: 16 Processor reset (RESET): Writing bit n of this field to ‘1’ will reset, but not start, processor n. When the processor has been reset the bit will be reset to ‘0’.
  • Page 315 The bus interrupt line 4*n+x will be mapped to the interrupt controller interrupt line specified by the value of IRQMAP[n*4+x]. The interrupt map registers are only accessible from the first interrupt controller (starting at offset 0x300). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 316: General Purpose I/O Ports

    A GPIO pin can also be toggled when a pulse is detected on an internal signal. This is enabled via the Pulse register in the core. This functionality is only supported for the first GPIO port, GRGPIO0. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 317: Registers

    I/O port output register, logical-AND 0x68 I/O port direction register, logical-AND 0x6C Interrupt mask register, logical-AND 0x70 Reserved 0x74 I/O port output register, logical-XOR 0x78 I/O port direction register, logical-XOR 0x7C Interrupt mask register, logical-XOR GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 318 RESERVED nlin-1: 0 I/O port direction value (DIR) - 0=output disabled, 1=output enabled Note: This field has range 15:0 for the first GPIO port, GRGPIO0, and range 21:0 for the second GPIO port, GRGPIO1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 319 15: 0 Interrupt polarity (POL) - 0=low/falling, 1=high/rising 22.3.6 Interrupt edge register Table 406.0x14- IEDGE - Interrupt edge register 16 15 RESERVED EDGE 31: 16 RESERVED 15: 0 Interrupt edge (EDGE) - 0=level, 1=edge GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 320 Interrupt available bit field (IMASK) - If IMASK[n] is 1 then GPIO line n can generate interrupts. This field is read-only has has value 0xFFFF for both GPIO ports. This means that lines 15:0 can be used for interrupt generation. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 321 ’1’ to the corresponding bit position. Note that for GR740 silicon revision 0, the IFLAG register bit(s) will only be set while the inter- rupt(s) is asserted. In silicon revision 0 this register is only practically usable when using level inter- rupts.
  • Page 322 The logical-OR/AND/XOR registers will update the corresponding register (see table 400) accord- ing to: New value = <Old value> logical-op <Write data> Note: This field has range 15:0 for the first GPIO port, GRGPIO0, and range 21:0 for the second GPIO port, GRGPIO1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 323: Uart Serial Interfaces

    (TS) will be set in the UART status register. Transmission resumes and the TS is cleared when a new character is GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 324: Baud-Rate Generation

    8 times the desired baud-rate. If the EC bit is set, the ticks will be generated with the same frequency as the external clock input instead of at the scaler underflow rate. In this case, the frequency of external clock must be less than half the frequency of the system clock. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 325: Loop Back Mode

    An interrupt can also be enabled for the transmitter shift register. When enabled the core will generate an interrupt each time the shift register goes from a non-empty to an empty state. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 326: Registers

    Transmitter FIFO empty (TE) - indicates that the transmitter FIFO is empty. Transmitter shift register empty (TS) - indicates that the transmitter shift register is empty. Data ready (DR) - indicates that new data is available in the receiver holding register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 327 Scaler reload value 23.7.5 UART FIFO Debug Register Table 418. UART FIFO debug register RESERVED DATA 7: 0 Transmitter holding register or FIFO (read access) 7: 0 Receiver holding register or FIFO (write access) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 328: Spi Controller Supporting Master And Slave Operation

    SPI_MOSI signal. However, due to synchronization issues the SPI_MISO signal will be delayed when the core is operating in slave mode, please see sec- tion 24.2.5 for details. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 329 Event register bit Not empty (NE) will be asserted. The receive register will only contain valid data if the Not empty bit is asserted and software should not access the receive register GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 330 When the transmit queue is empty the core will drive SPI_SCK to its idle state. If the SPI_SEL input goes low during master operation the core will abort any active transmission and GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 331: Registers

    0x00 Capability register 0x04-0x1C Reserved 0x20 Mode register 0x24 Event register 0x28 Mask register 0x2C Command register 0x30 Transmit register 0x34 Receive register 0x38 Slave Select register 0x3C Automatic slave select register 0x3F-0xFF Reserved GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 332 Enable core (EN) - When this bit is set to ‘1’ the core is enabled. No fields in the mode register should be changed while the core is enabled. This can bit can be set to ‘0’ by software, or by the core if a multiple-master error occurs. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 333 TIP status bit, and automatic slave select toggling at the end of a transfer, when the clock phase (CP field) is ‘0’. RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 334 This field is only updated when the core is enabled (EN field of Mode register is set to ’1’). 7: 0 RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 335 Event register bit is set when the whole transfer has completed. This bit is automatically cleared when the Event register bit has been set and is always read as zero. 21: 0 RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 336 0b11 31: 2 RESERVED 1: 0 Slave select (SLVSEL) - The core’s slave select signals are mapped to this register on bits 1:0. Soft- ware is responsible for activating the correct slave select signals. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 337 ASEL field in the Mode register is set to ‘1’. After a transfer has been completed the core’s slave select signals are assigned the original value in the slave select register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 338: Clock Gating Unit

    Functional module GRETH 10/100/1000 Mbit Ethernet MAC 0 GRETH 10/100/1000 Mbit Ethernet MAC 1 SpaceWire router PCI master/target controller MIL-STD-1553B controller CAN controller LEON4 Statistics unit UART 0 UART 1 SPI Controller PROM/IO memory controller GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 339: Registers

    Table 430 shows the clock gating unit registers. Table 430.Clock gating unit registers APB address offset Register 0x00 Unlock register 0x04 Clock enable register 0x08 Core reset register 0x0C CPU/FPU override register 0x10-0xFF Reserved GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 340 Reset (RESET) - A reset will be generated as long as the corresponding bit is set to ‘1’. The reset value of this register is set by bootstrap signals. See table 429 and section 4.9. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 341 15: 4 RESERVED 3: 0 Override CPU clock gating (OVERRIDE) - If bit n of this field is set to ’1’ then the clock for proces- sor n and FPU n will always be active. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 342: Leon4 Statistics Unit (Performance Counters)

    0x47 AHB half-word accesses. Filtered on CPU/AHBM if SU(1) = ‘1 0x48 AHB word accesses. Filtered on CPU/AHBM if SU(1) = ‘1 0x49 AHB double word accesses. Filtered on CPU/AHBM if SU(1) = ‘1 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 343 AHB RETRY responses. Filtered on CPU/AHBM if SU(1) = ‘1 0x7E AHB SPLIT responses. Filtered on CPU/AHBM if SU(1) = ‘1 0x7F AHB SPLIT delay. Filtered on CPU/AHBM if SU(1) = ‘1 Events generated from REQ/GNT signals GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 344: Multiple Apb Interfaces

    The core has two AMBA APB interfaces, the first is connected via the Processor AHB bus and the second is connected via the Debug AHB bus. The first APB interface always has precedence when both interfaces handle write operations to the same address. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 345: Registers

    Counter 0 max/latch register 0x104 Counter 1 max/latch register 0x108 Counter 2 max/latch register 0x10C Counter 3 max/latch register 0x110 Counter 4 max/latch register 0x114 Counter 5 max/latch register 0x118 Counter 6 max/latch register GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 346 Writing to this register will write both to the counter and, if implemented, the hold register for the maximum counter value. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 347 CPU or AHB master to monitor.(CPU/AHBM) - The value of this field does not matter when select- ing one of the events coming from the Debug Support Unit or one of the external events. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 348 The same timer is available as the processor’s internal up-counter, for interrupt timestamping and in the time-tag of the trace buffers. The time value is saved whenever a write access is made to the core in address range 0x100 - 0x1FC. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 349: Ahb Status Registers

    An error event will only be recorded by the first status register that should react based on filter settings. If register set 1 has reacted then register 2 will not be set for the same error event. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 350: Registers

    GR740 The extra register set, filtering, and multiple error detection is available in GR740 silicon revision 1. The status register version in the AMBA plug&play information is also set to 1 in silicon revision 1. 27.3 Registers The core is programmed through registers mapped into APB address space.

  • Page 351: Register For Bootstrap Signals

    The peripheral provides one register mapped into APB address space. Table 444.General purpose register registers APB address offset Register 0x00 Bootstrap register 0x04 - 0xFF RESERVED (first register is aliased in all words in this area) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 352 Reset value of JTAG_TRST signal (B10) - The value in this register can be written but the changed value does not affect system operation. This field is only available in GR740 silicon revision 1. Reset value of DSU_EN bootstrap signal (B9) - The value in this register can be written but the changed value does not affect system operation.

  • Page 353: Temperature Sensor Controller

    Start-up time after SRSTN in control register is set to ’1’ Sensor clock cycles * Cobham Gaisler is currently not authorized to disclose these parameters in public data sheets. Please contact support@gais- ler.com for further information. The sensor shall be intialised using the following steps: 1.

  • Page 354: Registers

    Sensor reset (SRSTN) - The value of this register is connected to the active-low reset input of the temperature sensor. Clock/Core enable (CLKEN) - When this field is set to ’1’ then the temperature sensor clock will be generated based on the DIV value in this register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 355 ’1’ and a new DATA value is read from the sensor then the THRES value is compared with the DATA value. If THRES >= DATA then the status register bit ALACT will be set to ’1’. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 356: Register Bank For I/O And Pll Configuration Registers

    30.2.3 Pad drive strength control Register bits allow adjusting the drive strength of the non-differential pads in the design. The pads have been divided by function into 20 groups, as shown in table below. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 357 Locking can be revokable or permanent (until next full system reset). Note that the lockdown reg- ister is not reset when the PLL is reconfigured but only when the external reset signal is asserted. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 358: Registers

    Pinmux alternative function enable (ALTFN) - Bit mask corresponding to table 24, used in conjunc- tion with FTMCTLR function enable register to determine pin function. If set to 1, pin is used as FTMCTRL or alternative function, if 0 FTMCTRL or GPIO function GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 359 New SYSPLL configuration (SYSPLLCFG) - To be used when reprogramming, see table 30 30.3.5 PLL reconfigure command register Table 458.0x10 - PLLRECFG - PLL reconfigure command register RESERVED RECONF 31: 3 RESERVED 2: 0 Reconfigure PLL (RECONF) - Write "000" then "111" to initiate reconfiguration GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 360 Software tag (SWTAG) - Can be used freely as tag data. 26: 18 Current SPWPLL configuration (SPWPLLCFG) - See table 32 17: 9 Current MEMPLL configuration (MEMPLLCFG) - See table 31 8: 0 Current SYSPLL configuration (SYSPLLCFG) - See table 30 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 361 Drive strength setting for output group 13 (S13) 5: 4 Drive strength setting for output group 12 (S12) 3: 2 Drive strength setting for output group 11 (S11) 1: 0 Drive strength setting for output group 10 (S10) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 362 Bits that are set to 1 in this field can only be cleared with a full system reset. 15: 8 RESERVED 7: 0 Revocable lock bit mask (REVOCABLE) - Bit N for register at offset 4*N, 1=locked, 0=unlocked GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 363: Spacewire - Time Distribution Protocol Controller

    The system can act as initiator (time master) and target being able to send and receive SpaceWire Time-Codes. The initiator requires SpaceWire link interface implements an RMAP initiator. The Tar- get requires SpaceWire link interface implements an RMAP target. The SPWTDP component is a part GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 364 CUC T-Field. The number of bits representing coarse and fine time of a ET counter implemented in a design can be obtained by reading the DPF bits of Datation Pream- ble Field register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 365 A target is a SpaceWire node receiving CCSDS Time Codes and SpaceWire Time-Codes. A target is also an RMAP target, capable of receiving RMAP commands and transmitting RMAP replies. There can be one or more targets in a SpaceWire network. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 366 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Mapping Values If the Mapping value is 6 then the mapped SpaceWire Time-Codes is 32 to 37 32 33 34 35 36 37 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 367 Control register) to the local ET counter of the target SPWTDP component. The Time message quali- fied TCQ bit in the status register will enable itself, this bit will disable itself when the conditions for time message qualification is achieved (SPWTC of Control register matches with a received Space- GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 368 The Latency calculation can be started in initiator based on DIR (distributed interrupt received) inter- rupt available in Interrupt Status register (the interrupt should be enabled in the Interrupt Enable regis- ter). The latency is calculated form the time stamp registers based on the equation explained below GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 369 The ET counter can be set using an external enable signal (configurable rising or falling edge, see reg- ister SP in Configuration 0 register). To set the ET counter the SE bit in configuration register must be GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 370: Registers

    0x024 Command Elapsed Time 0 0x028 Command Elapsed Time 1 0x02C Command Elapsed Time 2 0x030 Command Elapsed Time 3 0x034 Command Elapsed Time 4 0x038 RESERVED 0x03C RESERVED 0x040 - 0x05F Datation Field GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 371 External Datation Field 0x100 External Datation 0 Mask 0x104 External Datation 1 Mask 0x108 External Datation 2 Mask 0x10C External Datation 3 Mask 0x110-0x12F External Datation 0 Time 0x110 External Datation 0 Preamble Field GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 372 External Datation 0 Elapsed Time 3 0x124 External Datation 0 Elapsed Time 4 0x128 RESERVED 0x12C RESERVED 0x130-0x14F External Datation 1 Time 0x150-0x16F External Datation 2 Time 0x170-0x18F External Datation 3 Time 0x190-0x1FF RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 373 The core can act only as an initiator or target, both TE and RE cannot be enabled at the same time. Reset (RS) - Reset core. Makes complete reset when enabled, self clears itself (to disable). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 374 (only for target) 9: 5 Interrupt Received (INRX) - The distributed interrupt number received by initiator or target. 4: 0 Interrupt Transmitted (INTX) - The distributed interrupt number transmitted by initiator or target. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 375 In Sync (INSYNC) - In Synchronization at Time code level, enabled when time values are Initialized or Synchronized. Table 474. 0x014 - STAT 1 - Status Register 1 31 30 29 31: 30 RESERVED 29: 0 Increment Variation (IV) - (not usable in this implementation) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 376 Command Elapsed Time 2 (CET2) - Initialize or Synchronise local ET counter value (64 to 95). Table 479.0x030 - CET0 - Command Elapsed Time 3 CET3 Command Elapsed Time 3 (CET3) - Initialize or Synchronise local ET counter value (96 to 127). 31: 0 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 377 All registers are only readable. Table 485.0x050 - DET3 - Datation Elapsed Time 3 DET3 31: 0 Datation Elapsed Time 3 (DET3) - CCSDS Time Code value (96 to 127) of local ET counter value. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 378 Table 491. 0x070 - TR3- Time Stamp Elapsed Time 3 Rx 31: 0 Time Stamp Elapsed Time 3 Rx (TR3) - Time stamped local ET value (96 to 127) when distributed interrupt received. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 379 Table 496. 0x08C - TT2 - Time Stamp Elapsed Time 2 Tx 31: 0 Time Stamp Elapsed Time 2 Tx (TT2) - Time stamped local ET value (64 to 95) when distributed interrupt transmitted. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 380 31: 0 Latency Elapsed Time Value 1 (LE1) - Latency Value (32 to 63) written by initiator.(only for target) Table 502. 0xAC - LE2 -Latency Elapsed Time 2 31: 0 Latency Elapsed Time Value 2 (LE2) - Latency Value (64 to 95) written by initiator.(only for target) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 381 Enable (only for initiator) Time Message transmit Interrupt Enable (TME) - (only for initiator) Time-Code Received Interrupt Enable (TRE) - SpaceWire Time-Code Received Interrupt Enable (only for target) Sync Interrupt Enable (SE) (only for target) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 382 (Latency calculation should be enabled) Distributed interrupt Received (DIR) - Generated when distributed interrupt is Received (Latency calculation should be enabled) Time-Codes Transmitted (TT) - Generated when SpaceWire Time-Codes is transmitted (only for initiator) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 383 Table 510. 0x110 - EDPF0 - External Datation 0 Preamble Field 16 15 EDPF0 0x2f00 31: 16 RESERVED 15: 0 External Datation Preamble Field (EDPF0) - The number of coarse and fine time implemented can be obtained from this Preamble Field. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 384 The Definition of External Datation 1 Time, External Datation 2 Time and External Datation 3 Time registers are exactly same as External Datation 0 Time Registers (i.e. External Datation 0 Preamble Field and External Datation 0 Elapsed Time 0,1,2,3,4). GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 385: Bridge Connecting Debug Ahb Bus To Processor Ahb Bus

    HREADY low. On the master side the next access is started by performing a SEQ transfer (and then holding the bus using BUSY transfers). This sequence is repeated until the transfer is ended on the slave side. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 386 (up to 128-bit) that it can use to empty the writebuffer. Read and write combining is disabled for accesses to the area 0xF0000000 - 0xFFFFFFFF to prevent accesses wider than 32 bits to register areas. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 387 Table 518.Access latencies Access Master acc. cycles Slave cycles Delay incurred by performing access over core Single read 6 * clk Burst read with prefetch (6 + burst length)* clk 2 + (burst length) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 388: Registers

    The core implements posted writes, the number of cycles taken by the master side can only affect the next access. 32.3 Registers The core does not implement any registers accessible over AMBA AHB or APB. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 389: Leon4 Hardware Debug Support Unit

    DSU control register • after a single-step operation • one of the processors in a multiprocessor system has entered the debug mode • DSU AHB breakpoint or watchpoint hit GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 390: Ahb Trace Buffer

    Trac- ing is stopped when the EN bit is reset, or when a AHB breakpoint is hit. Tracing is temporarily GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 391 Wait state Active when HREADY input to AHB slaves is low and AMBA response is OKAY. retry RETRY response Active when master receives RETRY response split SPLIT response Active when master receives SPLIT response GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 392: Instruction Trace Buffer

    During the instruc- tion tracing (processor in normal mode), the trace buffer cannot be written and trace buffer control register 0 can not be written. The traced instructions can optionally be filtered on instruction types. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 393: Dsu Memory Map

    Instruction Trace buffer control register 1 0x200000 - 0x210000 AHB trace buffer (..0: Trace bits 127 - 96, ..4: Trace bits 95 - 64, ..8: Trace bits 63 - 32, ..C : Trace bits 31 - 0) GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 394 ASI = 0xC : Instruction cache tags ASI = 0xD : Instruction cache data ASI = 0xE : Data cache tags ASI = 0xF : Data cache data ASI = 0x1E : Separate snoop tags GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 395: Dsu Registers

    Trace enable (TE) - Enables instruction tracing. If set the instructions will be stored in the trace buffer. Remains set when then processor enters debug or error mode. TE is reset to ’1’ when external signal BREAK=LOW, otherwise TE is reset to 0. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 396 Enter debug mode (EDx) - Force processor x into debug mode if any of processors in a multiproces- sor system enters the debug mode. If 0, the processor x will not enter the debug mode. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 397 ASI while the address is supplied from the DSU memory area when per- forming an access at offset 0x700000. Table 529. 0x400024 - DASI- DSU ASI diagnostic access register RESERVED 31: 8 RESERVED 7: 0 ASI (ASI) - ASI to be used on diagnostic ASI access GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 398 Table 531. 0x000044 - ATBI - AHB trace buffer index register 12 11 RESERVED INDEX RESERVED 31: 12 RESERVED 11: 4 Trace buffer index counter (INDEX) - Address of next trace line to be written. 3: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 399 A mask register is associated with each breakpoint, allowing breaking on a block of addresses. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 400 Table 535. 0x000054, 0x00005C - ATBBM - AHB trace buffer break mask registers BMASK[31:2] LD ST rw rw 31: 2 Breakpoint mask (BMASK) - See description above tables. Load (LD) - Break on data load address Store (ST) - Break on data store address GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 401 ICOUNT[28:0] rw rw rw Counter Enable (CE) - Counter enable Instruction Count (IC) - Instruction (1) or clock (0) counting Profiling Enable (PE) - Profiling enable 28: 0 Instruction count (ICOUNT) - Instruction count GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 402 NOT match the specified data pattern (typically only usable if the watchpoint has been cou- pled with an address by setting the CP field). Couple (CP) - Couple AHB watchpoint 1 with AHB breakpoint 1 Enable (EN) - Enable AHB watchpoint 1 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 403 AHB watchpoint. The lower part of the register address specifies with part of the bus that the register value will be compared against: Offset 0x0 specifies the data value for AHB bus bits 127:96, 0x4 for bits 95:64, 0x8 for 63:32 and offset 0xC for bits 31:0. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 404 Trace Limit (TLIM) - TLIM is compared with the top bits of ITBC0.ITPOINTER to generate the value in the TOV field below. Trace Overflow (TOV) - Gets set to ‘1’ when the DSU detects that TLIM equals the top three bits of ITPOINTER. 22: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 405: Jtag Debug Link With Ahb Master Interface

    ‘1’ if the AHB access has completed and ‘0’ otherwise. 31 30 AHB Data - AHB write/read data. For byte and half-word transfers data is aligned according to big- endian order where data with address offset 0 data is placed in MSB bits. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 406: Registers

    If bit 32 is ‘0’, the read data is not valid and the command just shifted in has been dropped by the core. 34.3 Registers The core does not implement any registers mapped in the AMBA AHB or APB address space. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 407: Spacewire Debug Link

    SpaceWire domains during reception and transmission. The RMAP target handles incoming packets which are determined to be RMAP commands instead of the receiver DMA engine. The RMAP command is decoded and if it is valid, the operation is per- GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 408: Link Interface

    The current state of the link interface determines which type of characters are allowed to be transmit- ted which together with the requests made from the host interfaces determine what character will be sent. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 409 PHY module which presents it as a data and data-valid signal. Both the receiver and PHY are located in a separate clock domain which runs on a clock generated by the PHY. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 410: Time-Code Distribution

    Note that the link interface must be in run-state in order to be able to send a Time-Code. 35.5 Receiver DMA channels The receiver DMA engine handles reception of data from the SpaceWire network to different DMA channels. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 411 RMAP target while the separate address provides the channel its own range. If all channels use the default registers they will GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 412 Channel enabled Last DMA channel Separate addressing RMAP enabled dma(n).addr* !dma(n).mask= defaddr*!defmask = rxaddr*!dma(n).mask rxaddr*!defmask Process RMAP Store packet to Discard packet DMA channel command Figure 50. Flow chart of packet reception. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 413 24: 0 Packet length (PACKETLENGTH) - The number of bytes received to this buffer. Only valid after EN has been set to 0 by the GRSPW. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 414 DC bit is unimportant in this case. When the header is not corrupted the CRC value will always be zero when the calculation continues with the data field and the behaviour will be as if the CRC calculation was restarted GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 415: Transmitter Dma Channels

    SpaceWire network. Transmission is based on the same type of descriptors as for the receiver and the descriptor table has the same alignment and size restrictions. When there are new descriptors enabled the core reads them and transfer the amount data indicated. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 416 The CRC covers all bytes from this pointer except a number of bytes in the beginning specified by the non-crc bytes field. The CRC will not be sent if the header length field is zero. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 417 DMA control register. If an interrupt was requested it will also be generated. Then a new descriptor is read and if enabled a new transmission starts, otherwise the transmit enable bit is cleared and nothing will happen until it is enabled again. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 418: Rmap

    The Remote Memory Access Protocol (RMAP) is used to implement access to resources in the node via the SpaceWire Link. Some common operations are reading and writing to memory, registers and FIFOs. This section describes the basics of the RMAP protocol and the target implementation. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 419 Read accesses are performed on the fly, that is they are not stored in a temporary buffer before trans- mitting. This means that the error code 1 will never be seen in a read reply since the header has GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 420 The last control option for the target is the possibility to set the destination key which is found in a separate register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 421 If alignment is before writ- violated nothing is done and ing, send error code is set to 10. If an AHB acknowledge error occurs error code is set to 1. Reply is sent. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 422: Amba Interface

    A burst is always started when the FIFO is half-empty or if it can hold the last data for the packet. The burst containing the last data might have shorter length if the packet is not an even number of bursts in size. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 423: Registers

    DMA control/status, channel 1 0x24 SPW2.DMAMAXLEN DMA RX maximum length, channel 1 0x28 SPW2.DMATXDESC DMA transmit descriptor table address, channel 1 0x2C SPW2.DMARXDESC DMA receive descriptor table address, channel 1 0x30 SPW2.DMAADDR DMA address, channel 1 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 424 Autostart (AS) - Automatically start the link when a NULL has been received. Link Start (LS) - Start the link, i.e. allow a transition from ready to started state. Link Disable (LD) - Disable the SpaceWire codec. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 425 (link-interface is in other states than run). The actual divisor value is Clock Divisor register + 1. 7: 0 Clock divisor run (CLKDIVRUN) - Clock divisor value used for the clock-divider when the link-interface is in the run-state. The actual divisor value is Clock Divisor register + 1. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 426 Time counter (TIMECNT) - The current value of the system time counter. It is incremented for each tick-in and the incremented value is transmitted. The register can also be written directly but the written value will not be transmitted. Received time-counter values are also stored in this register. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 427 SW-node to read a new descriptor and try to transmit the packet it points to. This bit is automatically cleared when the SW-node encounters a descriptor which is disabled. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 428 MASK before the address check. 7: 0 Address (ADDR) - Address used for node identification on the SpaceWire network for the corresponding dma channel when the EN bit in the DMA control register is set. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 429: Ahb Trace Buffer Tracing Master I/O Ahb Bus

    Tracing is stopped when the EN bit is reset, or when a AHB breakpoint is hit. An interrupt is generated when a breakpoint is hit. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 430 Wait state Active when HREADY input to AHB slaves is low and AMBA response is OKAY. retry RETRY response Active when master receives RETRY response split SPLIT response Active when master receives SPLIT response GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 431: Registers

    Delay counter mode (DM) - Indicates that the trace buffer is in delay counter mode. Trace enable (EN) - Enables the trace buffer This field has reset value 1 if the BREAK signal is LOW and has reset value 0 otherwise. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 432 Table 568.0x000004 - INDEX - Trace buffer index register 11 10 RESERVED INDEX RESERVED 31: 11 RESERVED 10: 4 Trace buffer index counter (INDEX) - Indicates the address of the next 128-bit line to be written. 3: 0 RESERVED GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 433 Slave Mask (SMASK) - If SMASK[n] is set to ‘1’, the trace buffer will not save accesses performed to slave n. 15: 0 Master Mask (MMASK) - If MMASK[n] is set to ‘1’, the trace buffer will not save accesses per- formed by master n. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 434 Table 572. 0x000014, 0x00001C - TBBM - Trace buffer break mask registers BMASK[31:2] LD ST rw rw 31: 2 Breakpoint mask (BMASK) - See description above tables. Load (LD) - Break on data load address Store (ST) - Break on data store address GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 435: Amba Ahb Controller With Plug&Play Support

    32 bytes, which means that the area has place for 64 masters and 64 slaves. The address of the plug&play information for a certain unit is defined by its bus index. The address for masters is thus 0xFFFFF000 + n*32, and 0xFFFFF800 + n*32 for slaves. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 436 20 19 18 17 16 15 TYPE P = Prefetchable 0001 = APB I/O space C = Cacheable 0010 = AHB Memory space 0011 = AHB I/O space Figure 52. AHB plug&play information record GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 437: Amba Ahb/Apb Bridge With Plug&Play Support

    0xF00FF000 + n*8. 24 23 12 11 10 9 APB Plug&play record Configuration word VENDOR ID DEVICE ID VERSION 0x00 ADDR MASK TYPE 0x04 20 19 16 15 Figure 54. APB plug&play information GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 438: Electrical Description

    = -300 mV with a maximum duration of 3 ns beyond the recommended limits can be tolerated per transi- SHOOT tion. Alternatively, if DC levels are limited to 3.4V then V = 500 mV and V IH OVERSHOOT IL UNDERSHOOT 500 mV with a maximum duration of 3 ns can be tolerated. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 439: Input And Output Signal Dc Characteristics

    The different grounds are provided for PCB design / power integrity purposes, all grounds supplied to the device must be connected and at the same DC potential. 39.4.1 Power sequence This section is provided as a design guideline. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 440 3.600 I/O level, LVDS pins 0.000 2.000 I/O leakage current -0.010 0.010 leak,LVCMOS (LVCMOS) I/O leakage current Not counting cur- leak,LVCMOS (LVDS) rent on inputs dur to R I,LVDS LVDS input resis- I,LVDS tance GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 441: Ac Characteristics

    AC parameter tests 39.5.2 Clocks Table 579 summarizes required/recommended conditions for some of the design input clocks that connect to on-chip PLLs. For the remaining clocks please see the interface-specific timing in the sub- sections below GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 442 The maximum given here is from static timing analysis in worst case PVT corner and includes margins for aging and jitter, and it is also used as clock rate during production tests. Supplied as design parameter, not tested Limit on rising edge only GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 443 Reference edge Unit clock to output tri-state delay rising clk edge LEON4_0 Notes: This parameter is guaranteed by design and is not tested This parameter is determined by static timing analysis and is not tested GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 444 2.76 SDRAM3 edge data input from clock hold rising mem_clk_in SDRAM4 edge Notes: This parameter is guaranteed by design and is not tested This parameter is determined by characterization and is not tested GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 445 AHBJTAG0 clock low/high period AHBJTAG1 data input to clock setup rising jtag_tck edge AHBJTAG2 data input from clock hold rising jtag_tck edge AHBJTAG3 clock to data output delay falling jtag_tck edge AHBJTAG4 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 446 This parameter is determined by static timing analysis and is not tested eth*_rxclk is used in both MII and GMII mode, with different frequencies. signals col, crs, mdint, mdio are resynchronized internally and do not have any setup/hold timing requirements GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 447 Figure 62. Timing waveforms Table 586.Timing parameters Name Parameter Reference edge Unit MDIO clock-to-output delay rising clk edge where mdc Tclk MDIO0 rises MDIO input sampling point rising clk edge where mdc Tclk MDIO1 falls GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 448 Assuming SpaceWire PLL used in nominal configuration Edge separation and skew limits refer to each pair of data/strobe signals separately. Global skew and separation over the entire set of eight pairs is not specified. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 449 SPWD5 data & strobe edge separation 1) 2) SPWD6 data & strobe output skew SPWD7 Assuming SpaceWire PLL used in nominal configuration Verified by static timing analysis only, not tested GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 450 6.44 PCI2 clock to output delay rising pci_clk edge 3.05 17.91 PCI3 input to clock hold rising pci_clk edge 1.03 PCI4 input to clock setup rising pci_clk edge 6.44 PCI5 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 451 1553BRM2 1) Guaranteed by design, not tested 2) Guaranteed by static timing analysis, not tested 3) The inputs are asynchronous to the clock and are internally resynchronized to gr1553_clk GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 452 FTMCTRL0 promio_addr[] FTMCTRL1 FTMCTRL1 prom_cen[] FTMCTRL2 FTMCTRL2 promio_wen FTMCTRL3, FTMCTRL4 promio_data[] (output) FTMCTRL5 internal sys_clk promio_addr[] prom_cen[] FTMCTRL6 FTMCTRL6 promio_oen FTMCTRL7 FTMCTRL8 promio_data[] (input) FTMCTRL10 FTMCTRL9 promio_brdyn - PROM accesses Figure 67. Timing waveforms GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 453 FTMCTRL10 Timing values are relative to the internal clock for the PROM/IO memory controller. 2) Guaranteed by design, not tested 3) Verified by static timing analysis, not tested GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 454 GRGPIO4 Guaranteed by design, not tested. Verified by static timing analysis, not tested The gpio inputs are re-synchronized internally. The signals do not have to meet any setup or hold requirements. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 455 APBUART2 Guaranteed by design, not tested. Verified by static timing analysis, not tested The _cstn and _rxd inputs are re-synchronized internally. These signals to not have to meet any setup or hold require- ments. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 456 Verified by static timing analysis, not tested The spi_sck/miso/mosi/spisel inputs are re-synchronized internally. The signals do not have to meet any setup or hold requirements. However, the input to clock setup value restricts the maximum SPI frequency. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 457 Verified by static timing analysis, not tested The can inputs are re-synchronized internally. The signals do not have to meet any setup or hold requirements. However, the input to clock setup value restricts the maximum SPI frequency. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 458: Mechanical Description

    Component and package The device is available as CCGA625 and LGA625. Please refer to section 40.4 for the package draw- ing. A placement diagram is available in section 40.2 and pin assignments in section 40.3. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 459: Package Placement Diagram

    GR740 40.2 Package placement diagram Figure 74. Placement, top view (through package) Figure 75. Placement, bottom view GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 460: Pin Assignment

    LVCMOS PROM PROMIO_ADDR[0] LVCMOS PROM PROMIO_READ LVCMOS High PROM PROMIO_DATA[12] LVCMOS PROM PROMIO_DATA[8] LVCMOS PROM PROMIO_DATA[4] LVCMOS PROM GR1553_CLK LVCMOS MIL-1553 SPI_MISO LVCMOS SPW_CLK LVCMOS Sys/spw CLK SYS_RESETN LVCMOS Sys/spw CLK JTAG_TMS LVCMOS JTAG GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 461 Power/ground pin VSS2V5 VSS2V5 Power/ground pin VSS2V5 VSS2V5 Power/ground pin VSS2V5 PROMIO_ADDR[14] LVCMOS PROM PROMIO_ADDR[16] LVCMOS PROM PROMIO_ADDR[11] LVCMOS PROM PROMIO_ADDR[5] LVCMOS PROM PROMIO_BRDYN LVCMOS PROM PROMIO_DATA[13] LVCMOS PROM PROMIO_DATA[11] LVCMOS PROM PROMIO_DATA[3] LVCMOS PROM GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 462 High Bootstrap PLL_LOCKED[5] LVCMOS High Bootstrap PLL_LOCKED[3] LVCMOS High Bootstrap PLL_LOCKED[0] LVCMOS High Bootstrap VSS2V5 Power/ground pin VSS2V5 SPW_RXS_P[7] LVDS DiffTerm SpaceWire SPW_RXS_N[7] LVDS DiffTerm SpaceWire SPW_RXD_P[7] LVDS DiffTerm SpaceWire SPW_RXD_N[7] LVDS DiffTerm SpaceWire GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 463 VSS3V3 VDIG3V3 Power/ground pin VDIG3V3 DVDDPLL1V2_SYSPLL Power/ground pin DVDDPLL1V2_MEMPLL Power/ground pin DVDDPLL1V2_SPWPLL Power/ground pin VDIG3V3 Power/ground pin VDIG3V3 VSS3V3 Power/ground pin VSS3V3 VDIG3V3 Power/ground pin VDIG3V3 VSS3V3 Power/ground pin VSS3V3 VDIG3V3 Power/ground pin VDIG3V3 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 464 VDIG3V3 Power/ground pin VDIG3V3 ETH0_MDINT LVCMOS Ethernet ETH0_CRS LVCMOS High Ethernet VSS3V3 Power/ground pin VSS3V3 VDIG3V3 Power/ground pin VDIG3V3 Power/ground pin VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 465 SPW_TXS_N[4] LVDS SpaceWire SPW_TXD_P[4] LVDS SpaceWire SPW_TXD_N[4] LVDS SpaceWire ETH0_RXD[4] LVCMOS Ethernet ETH0_RXD[6] LVCMOS Ethernet VDIG3V3 Power/ground pin VDIG3V3 ETH0_RXD[1] LVCMOS Ethernet ETH0_RXDV LVCMOS High Ethernet VSS3V3 Power/ground pin VSS3V3 VDIG3V3 Power/ground pin VDIG3V3 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 466 Power/ground pin Power/ground pin VDD1V2 Power/ground pin VSS3V3 Power/ground pin VSS3V3 VDIG3V3 Power/ground pin VDIG3V3 VSS2V5 Power/ground pin VSS2V5 SPW_TXS_P[3] LVDS SpaceWire SPW_TXS_N[3] LVDS SpaceWire SPW_TXD_P[3] LVDS SpaceWire SPW_TXD_N[3] LVDS SpaceWire ETH0_TXD[0] LVCMOS Ethernet GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 467 Power/ground pin Power/ground pin VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin VSS3V3 Power/ground pin VSS3V3 VDIG3V3 Power/ground pin VDIG3V3 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 468 LVCMOS SDRAM MEM_DQ[4] LVCMOS SDRAM MEM_DQ[0] LVCMOS SDRAM VDIG3V3 Power/ground pin VDIG3V3 VSS3V3 Power/ground pin VSS3V3 VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin Power/ground pin VDD1V2 Power/ground pin GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 469 LVDS DiffTerm SpaceWire SPW_RXD_N[1] LVDS DiffTerm SpaceWire MEM_DQ[9] LVCMOS SDRAM MEM_DQ[11] LVCMOS SDRAM VSS3V3 Power/ground pin VSS3V3 MEM_DQ[10] LVCMOS SDRAM MEM_DQ[8] LVCMOS SDRAM VDIG3V3 Power/ground pin VDIG3V3 VSS3V3 Power/ground pin VSS3V3 VDD1V2 Power/ground pin GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 470 VDIG3V3 Power/ground pin VDIG3V3 VSS3V3 Power/ground pin VSS3V3 VSS2V5 Power/ground pin VSS2V5 SPW_RXS_P[0] LVDS DiffTerm SpaceWire SPW_RXS_N[0] LVDS DiffTerm SpaceWire SPW_RXD_P[0] LVDS DiffTerm SpaceWire SPW_RXD_N[0] LVDS DiffTerm SpaceWire MEM_DQ[19] LVCMOS SDRAM MEM_DQ[17] LVCMOS SDRAM GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 471 LVCMOS SDRAM AA14 MEM_DQ[51] LVCMOS SDRAM AA15 MEM_DQ[53] LVCMOS SDRAM AA16 MEM_DQM[7] LVCMOS SDRAM AA17 MEM_DQ[65] LVCMOS SDRAM AA18 MEM_DQ[69] LVCMOS SDRAM AA19 MEM_DQ[73] LVCMOS SDRAM AA20 MEM_DQ[79] LVCMOS SDRAM AA21 MEM_DQ[88] LVCMOS SDRAM GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 472 SDRAM VDIG3V3 Power/ground pin VDIG3V3 VSS3V3 Power/ground pin VSS3V3 AC10 MEM_ADDR[5] LVCMOS SDRAM AC11 MEM_ADDR[9] LVCMOS SDRAM AC12 VDIG3V3 Power/ground pin VDIG3V3 AC13 VSS3V3 Power/ground pin VSS3V3 AC14 Power/ground pin AC15 MEM_DQ[52] LVCMOS SDRAM GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 473 SDRAM AD23 MEM_DQ[85] LVCMOS SDRAM AD24 MEM_DQ[84] LVCMOS SDRAM Power/ground pin Power/ground pin MEM_DQ[33] LVCMOS SDRAM MEM_DQ[37] LVCMOS SDRAM MEM_DQM[5] LVCMOS SDRAM MEM_DQ[43] LVCMOS SDRAM MEM_DQ[47] LVCMOS SDRAM MEM_ADDR[0] LVCMOS SDRAM MEM_ADDR[4] LVCMOS SDRAM GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 474 AE17 MEM_DQ[62] LVCMOS SDRAM AE18 MEM_DQ[66] LVCMOS SDRAM AE19 MEM_DQ[70] LVCMOS SDRAM AE20 MEM_DQ[72] LVCMOS SDRAM AE21 MEM_DQ[76] LVCMOS SDRAM AE22 MEM_DQ[80] LVCMOS SDRAM AE23 MEM_DQ[83] LVCMOS SDRAM AE24 Power/ground pin AE25 Power/ground pin GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 475: Package Drawing

    Package drawing 40.4.1 Overview The GR740 is available in different package configurations depending on device type, see ordering information in section 42. The drawing in section 40.4.2 applies to prototypes using the first version of the package (package revision 0). Sections 40.4.3 and 40.4.4 show the dimension of the latest pack- age with and without columns attached, respectively.
  • Page 476 GR740 40.4.3 Package drawing for GR740-[YY,CP,MP,MSEQ,MSEV,MSQ,MSV]-LG625 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 477 GR740 40.4.4 Package drawing for GR740-[YY,CP,MP,MSEQ,MSEV,MSQ,MSV]-CG625 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 478 GR740 GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 479: Temperature And Thermal Resistance

    GR740 Temperature and thermal resistance Table 598.Temperature limits Parameter Symbol Unit Storage temperature storage Operating temperature operation Table 599.Thermal resistance Parameter Symbol Unit  Thermal resistance, junction to case 3.23 C / W GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 480: Ordering Information

    GR740 Ordering information Please contact Cobham Gaisler AB through sales@gaisler.com. Ordering information is provided in table 600 and a legend in table 601. Table 600.Ordering information, available models Product Description Silicon rev Package rev Notes GR740-XX-LG625 Engineering model (prototype) GR740-XX-CG625...

  • Page 481: Silicon Revisions And Errata

    Weak pull-downs on TESTEN, DSU_EN, and JTAG_TRST. Not present Present Additional fields in register for bootstrap signals. Added functionality in revi- sion 1. Backward compatible change. LEON4 direct cache replacement policy implementation Affected Not affected GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...

  • Page 482: Change And Errata Descriptions

    This bug does not have any effect until the instruction cache is enabled. The DPBM function was added as a new feature to GR740 and not present in earlier LEON4 devices, the workaround to turn this off reverts back to the previous behavior without any other side effects.
  • Page 483 LEON4 will clear (invalidate) its cache. This operation requires at least 128 clock cycles after reset. The clock gating in the GR740 will clock-gate off the processors before this opera- tion has completed. Leading to the data cache RAM enable signals being left asserted. The data cache RAMs are clocked by a running clock in order to enable bus snooping.
  • Page 484 The interrupt controller can be used to start processor execution from a specified start address. The interface to accomplish this is different between GR740 silicon revision 0 and silicon revision 1. In GR740 revision 0, the following registers are available: •...
  • Page 485 GR740 In GR740 revision 1, the following registers are available • Error mode status register • Processor boot address registers for processors 0 - 3 The revision 1 register interface allows software to force a processor into debug or error mode. This means that the interface can be used to stop (and restart) a processor while the interface in silicon revi- sion 0 requires that a processor is idle before the processor can be restarted.
  • Page 486 PCI controller memory areas are accessed since a proper PCI clock is missing. In GR740 silicon revision 1 it is still possible to set the PCI controller’s enable bit in the clock gating unit. This will have no effect since the internal enable signals that control clock gates and AMBA bus multiplexers are guarded with the PCIMODE_ENABLE signal.
  • Page 487 Corner case where the result of a FDIV and FSQRT operation could fail to be written to the floating point register file. The issue is further described in the document GRLIB-TN-0013 available from http://www.gaisler.com/notes. Workaround: See GRLIB-TN-0013. Applicable to: This limitation is only present in silicon revision 0. GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler...
  • Page 488 Cobham; nor does the purchase, lease, or use of a product or service from Cobham convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Cobham or of third parties.

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