MICROBEE FTM-3SE Quick Start Manual

TWR-K70 Demo Quick Start Guide
The flexibility that programmable logic brings to hardware design has now arrived for the Freescale Tower System.
Now you can get even closer to your end product design through rapid prototyping by including FPGA design along
with your choice of processor and other system building blocks.
In this Demo / Quick Start Guide we demonstrate the use of the FTM-3SE FPGA board along with the TWR-K70
Kinetis processor board, the TWR-SER serial comms board & the TWR-LCD-RGB.
The purpose of this demonstration is to show the basics of loading a pre-compiled Xilinx logic design into the FPGA
and how to work with the K70's Flexbus interface to access the registers within the Xilinx Logic design.
To do this, the demonstration code that runs on the K70 processor takes the following steps:
Initialise internal peripherals, DRAM controller, LCD controller, I/O pin control, pull-ups, drive strength
•
Log the SDcard and test to see if the Xilinx logic configuration file exists on the card
•
Start the initialisation sequence for the Xilinx FPGA (strobe N_PROG)
•
Load blocks of 128 bytes from the file on the SDcard (FTM3SECI.BIN) into the FPGA until end of file
•
Test 'DONE' signal from the Xilinx FPGA is HIGH (signifying configuration complete)
•
Test the memory on the FTM-3SE board via the Flexbus via the internal signal routing in the FPGA
•
Toggle the I/O pins on the FTM-3SE board via the registers within the logic design loaded into the FPGA
•

Configuring your Freescale Tower System

The configuration for the TWR-K70 board is the same as in the quick start guide for that board – all configuration
jumpers remain as initially set to work with the TWR-SER module in the tower. Note that as per the K70 quick start
guide, the 50Mhz Oscillator clock is generated by the TWR-SER board.
The configuration for the TWR-LCD-RGB display is unmodified as well – all jumpers on this board are set as per the
standard configuration.

Configuring the FTM-3SE module

Microbee Technology
FTM-3SE
Freescale Tower System Compatible
Field Programmable Gate Array Module
Check that the jumpers on the FTM-3SE module are set as follows:
Jumper JP27 (Config Mode)
1-2 on, 3-4 off
(Slave parallel configuration)
Jumper JP4 (Power Enable)
1-2 on (closest to JP4 label)
N_PROG & DONE signal allocation:
JP2 – jumper pins 5 & 6
JP3 – jumper pins 3 & 4
LINK JP2 pin 1 to JP3 pin 2
FlexBus Chip select – select CS0
JP1 – jumper pins 1 & 2