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Freescale Semiconductor

MPC5510 Reference Manual

This is the MPC5510 Reference Manual set consisting of the following files:

•

MPC5510 Reference Manual Addendum, Rev 1

•

MPC5510 Reference Manual, Rev 1

© Freescale Semiconductor, Inc., 2012. All rights reserved.

MPC5510RM

Rev. 1.1, 04/2012

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Page 1 Freescale Semiconductor MPC5510RM Rev. 1.1, 04/2012 MPC5510 Reference Manual This is the MPC5510 Reference Manual set consisting of the following files: • MPC5510 Reference Manual Addendum, Rev 1 • MPC5510 Reference Manual, Rev 1 © Freescale Semiconductor, Inc., 2012. All rights reserved.
Page 2 MPC5510RM. For convenience, the addenda items are grouped by revision. Please check our website http://www.freescale.com/powerarchitecture for the latest updates. The current version available of the MPC5510 Microcontroller Reference Manual is Revision 1.0. © Freescale Semiconductor, Inc., 2012. All rights reserved.
Page 3: Mpc5510 Reference Manual Addendum, Rev
(MDIS) bits and a system-level halt mechanism. Figure 3-2 Diagram” shows the device-level clock gating mechanism for the MPC5510. Figure 3-3 shows a more detailed implementation of the MDIS and halt mechanism connections for a given peripheral. These features are detailed in subsequent sections.
Page 4: Rev.
Module clock FlexCAN_A MDIS Protocol clock CLK_SRC DSPI_A MDIS LPCLKDIV1 ESCI_A,IIC_A,PIT MDIS (RTI) LPCLKDIV2 Module clock FlexCAN_B-F MDIS Protocol clock CLK_SRC LPCLKDIV3 DSPI_B-D MDIS LPCLKDIV4 ESCI_B-H MDIS LPCLKDIV5 eMIOS MDIS LPCLKDIV6 MDIS MPC5510 Reference Manual Addendum, Rev. 1 Freescale Semiconductor...
Page 5: Rev.
45% of a bit time has passed, the Tx load will be transmitted in less (ESCIx_DR)” than a bit time. Otherwise, the Tx will take up to 1.5 of a bit time. MPC5510 Reference Manual Addendum, Rev. 1 Freescale Semiconductor...
Page 6: Revision History
CFIFO number that each trigger is connected to, divide the eDMA channel number by 2. Revision History Table 2 provides a revision history for this document. Table 2. Revision History Table Rev. Number Substantive Changes Date of Release First release. 04/2012 MPC5510 Reference Manual Addendum, Rev. 1 Freescale Semiconductor...
Page 7 Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer...
Page 8 MPC5510 Microcontroller Family Reference Manual Devices Supported: MPC5517G/E/S MPC5516G/E/S MPC5515S MPC5514G/E Document Number: MPC5510RM Rev. 1 06/2008 PRELIMINARY...
Page 9 Freescale Semiconductor China Ltd. application in which the failure of the Freescale Semiconductor product could Exchange Building 23F create a situation where personal injury or death may occur. Should Buyer No.
Page 10: Table Of Contents
MPC5510 Family Comparison ........
Page 11 5.2.2 Register Descriptions ..........5-4 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 12 7.4.1 Reset Configuration Timing ......... . . 7-4 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 13 9.5.10 Examining LIFO contents ......... . . 9-27 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 14 10.3.2 e200-Specific Special Purpose Registers ....... 10-11 10.3.3 e200z1 Core Complex Features Not Supported on the MPC5510 ... 10-13 10.4 e200z1 Memory Management Unit .
Page 15 14.4 Functional Description ........... . . 14-2 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 16 17.6 Application Information ........... 17-17 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 17 20.1 Introduction ............. 20-1 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 18 22.3 External Signal Description ..........22-3 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 19 23.5.4 Calculation of FIFO Pointer Addresses ....... . 23-60 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 20 25.4.10Bus Interface ........... . 25-41 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 21 27.1.4 Modes of Operation ..........27-4 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 22 29.4.1 External Bus Interface Features ........29-16 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 23 30.6.19Interrupt Support ..........30-140 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 24 32.1.1 Features ............32-1 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 25 A.1 Changes Between Revisions 0 and 1 ......... . . A-1 MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 26: Introduction
The MPC5510 platform has a single level of memory hierarchy and can support up to 80 KB of on-chip static random access memory (SRAM) and 1.5 MB of internal flash memory. Refer to Table 1-1 specific memory and feature sets of the proposed roadmap product members.
Page 27: Block Diagram
Reset Controller Blocks IMUX GPIO and Pad Control Note: The e200z1 is called Processor 0, and the e200z0 is called Processor 1 throughout this document Figure 1-1. MPC5516 Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 28: Mpc5510 Family Comparison
Overview MPC5510 Family Comparison Table 1-1 provides a summary of the different members of the MPC5510 family and their proposed features. This information is intended to provide an understanding of the range of functionality offered by this family. MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 29 Table 1-1. MPC5510 Family Comparison, Maximum Feature Set Feature MPC5517G MPC5517E MPC5517S MPC5516G MPC5516E MPC5516S MPC5515S MPC5514G MPC5514E Package 208-BGA 144-LQFP 208-BGA/ 144-LQFP 208-BGA/ 144-LQFP 208-BGA 144-LQFP 208-BGA/ 144-LQFP 176-LQFP 144-LQFP 176-LQFP 144-LQFP 144-LQFP 176-LQFP 176-LQFP 176-LQFP Main CPU e200z1...
Page 30: Family Feature Set Scaling
1.3.1 Family Feature Set Scaling The MPC5510 family supports multiple functions on most of the pins. This allows flexibility in the positioning and the availability of device features. It is the user’s choice what trade-offs are made between the feature set used for the available pin count through this device pin multiplexing. The available features implemented on silicon will be incrementally added as the family functionality increases.
Page 31: Chip-Level Features
On-chip voltage regulator (VREG) regulation of input supply for all internal levels • Optional e200z0, second I/O processor built on Power Architecture technology with VLE instruction set • Optional FlexRay controller • Optional external bus interface (EBI) module MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 32: Low-Power Operation
MPC5510. SLEEP mode retains the output levels on the pins, but power gating means that the contents of the cores, on-chip peripheral registers, and some of the volatile memory are not held.
Page 33 Overview Table 1-5. Detailed MPC5510 Family Memory Map (continued) Allocated Size Address Range (bytes) 0x2000_0000–0x3FFF_FFFF 512 M External Memory 0x4000_0000–0x4000_1FFF Internal SRAM Array. Powered during Sleep when CRP_PSCR[RAMSEL] = 1 to 7 0x4000_2000–0x4000_3FFF Internal SRAM Array. Powered during Sleep when CRP_PSCR[RAMSEL] = 2 to 7 0x4000_4000–0x4000_7FFF...
Page 34 Overview Table 1-5. Detailed MPC5510 Family Memory Map (continued) Allocated Size Address Range (bytes) 0xFFFB_4000–0xFFFB_7FFF 16 K Serial Communications Interface (eSCI_F) 0xFFFB_8000–0xFFFB_FFFF 16 K Serial Communications Interface (eSCI_G) 0xFFFB_C000–0xFFFB_FFFF 16 K Serial Communications Interface (eSCI_H) 0xFFFC_0000–0xFFFC_3FFF 16 K Controller Area Network (FlexCAN_A) 0xFFFC_4000–0xFFFC_7FFF...
Page 35 Overview MPC5510 Microcontroller Family Reference Manual, Rev. 1 1-10 Freescale Semiconductor Preliminary...
Page 36: Introduction
This chapter describes signals that connect off-chip. It includes a signal properties summary, power and ground segmentation summary, package pinouts, and detailed descriptions of signals. Because the MPC5510 comes in multiple packages, some signals will not be available on every package. Refer to the MPC5510 Microcontroller Family Data Sheet for electrical characteristics.
Page 37 Analog Input A + SH — — DDE1 PCS_C[2] DSPI_C Peripheral Chip Select PB[4] GPIO AN[32] eQADC Analog Input A + SH — — DDE1 PCS_C[1] DSPI_C Peripheral Chip Select MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 38 Channel — — DDE1 FR_A_TX FlexRay Channel A Transmit AD[16] EBI Multiplexed Address/Data PC[2] GPIO eMIOS[2] eMIOS Channel — — DDE1 FR_A_RX FlexRay Channel A Receive EBI Transfer Start MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 39 DDE1 PCS_A[4] DSPI_A Peripheral Chip Select PCS_D[1] DSPI_D Peripheral Chip Select PC[15] GPIO eMIOS[15] eMIOS Channel PC15 — — DDE1 PCS_A[3] DSPI_A Peripheral Chip Select PCS_D[2] DSPI_D Peripheral Chip Select MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 40 NMI Input for Z0 Core PD[12] GPIO PD12 PCS_B[0] DSPI_B Peripheral Chip Select — — DDE1 eMIOS[9] eMIOS Channel PD[13] GPIO PD13 SCK_B DSPI_B Clock — — DDE1 eMIOS[8] eMIOS Channel MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 41 — DDE1 PE10 PE[10] GPIO — — — DDE1 PE11 PE[11] GPIO — — — DDE1 PE12 PE[12] GPIO — — — DDE1 PE13 PE[13] GPIO — — — DDE1 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 42 DDE3 ADDR[13] EBI Non Muxed Address MDO[3] Nexus Message Data Out PF[8] GPIO AD[14] EBI Muxed Address/Data — — DDE2 ADDR[14] EBI Non Muxed Address MDO[4] Nexus Message Data Out MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 43 EBI Muxed Address/Data — — DDE2 eMIOS[19] eMIOS Channel SCK_C DSPI_C Serial Clock PG[4] GPIO AD[20] EBI Muxed Address/Data — — DDE2 eMIOS[20] eMIOS Channel PCS_C[0] DSPI_C Peripheral Chip Select MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 44 A + SH — — DDE2 eMIOS[20] eMIOS Channel SCL_A C_A Serial Clock PH[1] GPIO AN[26] eQADC Analog Input A + SH — — DDE2 eMIOS[21] eMIOS Channel SDA_A C_A Serial Data MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 45 EBI Write Enable PH[15] GPIO PH15 — — — DDE2 WE[3] EBI Write Enable Port J (16) (Section/Page: 2.7.9/2-32) PJ[0] GPIO — — — — DDE3 AD[0] EBI Muxed Address/Data MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-10 Freescale Semiconductor Preliminary...
Page 46 External Clock Input XTAL — XTAL Main Crystal Oscillator Output XTAL DDSYN — JTAG Test Mode Select Input TMS (Pull Up) DDE3 — JTAG Test Clock Input TCK (Pull Down) DDE3 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-11 Preliminary...
Page 47: Power And Ground Supply Summary
Port A[14:15]—EXTAL32 and XTAL32 functions only apply on the 144LQFP. These functions are on PortK[0:1] for the 176LQFP and 208BGA. This analog input pin has reduced analog-to-digital conversion accuracy compared to PA0–PA15. See the MPC5510 Microcontroller Family Data Sheet for values.
Page 48 V in the 144LQFP and 176LQFP packages. requires nominal 5V for program/erase operations, but may be 0-5V otherwise. is shorted to V in the package. FLASH DD33 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-13 Preliminary...
Page 49: Pinout – 144 Lqfp
PE4/SOUT_A/eMIOS1/MLBDO SCK_A/AD29/PG13 PE5/SIN_A/eMIOS0/MLB_SLOT PCS_A0/AD28/PG12 PCS_A1/AD27/PG11 PCS_A2/AD26/PG10 SSE2 DD33 FLASH DDE2 SSSYN TXD_C/PCS_A3/AD25/PG9 EXTAL PCS_A4/AD24/PG8 XTAL RXD_C/eMIOS23/AD23/PG7 DDSYN Denotes active during RESET only Figure 2-2. MPC5510 Pinout – 144 LQFP MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-14 Freescale Semiconductor Preliminary...
Page 50: Pinout – 176 Lqfp
PCS_A1/AD27/PG11 PE3/SCK_A/eMIOS2//MLBSO PCS_A2/AD26/PG10 PE15 PE4/SOUT_A/eMIOS1/MLBDO SSE2 PE5/SIN_A/eMIOS0/MLB_SLOT DDE2 TXD_C/PCS_A3/AD25/PG9 PCS_A4/AD24/PG8 RXD_C/eMIOS23/AD23/PG7 DD33 FLASH SSSYN EXTAL XTAL DDSYN Denotes active during RESET only Figure 2-3. MPC5510 Pinout – 176 LQFP MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-15 Preliminary...
Page 51: Pinout – 208 Bga
PF10 TEST DDSYN JCOMP PH14 DDE3 Figure 2-4. MPC5510 Pinout – 208 PBGA Detailed External Signal Descriptions 2.7.1 Port A Pins 2.7.1.1 PA0 to PA13 — GPI (PA[0:13]) / Analog Input (AN[0] – AN[13]) PA[0:13] are general-purpose input (GPI) pins. AN[0] to AN[13] are single-ended analog input pins.
Page 52: Port B Pins
PB4 — GPIO (PB[4]) / Analog Input (AN[32]) / DSPI_C Peripheral Chip Select (PCS_C[1]) PB[4] is a GPIO pin. AN[32] is a single-ended analog input pin. PCS_C[1] is a peripheral chip select output pin for the DSPI C module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-17 Preliminary...
Page 53 Chip Select (PCS_B[4]) PB[12] is a GPIO pin. TXD_G is the transmit pin for the eSCI G module. PCS_B[4] is a peripheral chip select output pin for the DSPI B module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-18 Freescale Semiconductor...
Page 54: Port C Pins
PC4 — GPIO (PC[4]) / eMIOS Channel (eMIOS[4]) / FlexRay Debug 1 (FR_DBG1) PC[4] is a GPIO pin. eMIOS[4] is an input/output channel pin for the eMIOS200 module. FR_DBG1 is one of the FlexRay debug port pins. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-19 Preliminary...
Page 55 PC[11] is a GPIO pin. eMIOS[11] is an input/output channel pin for the eMIOS200 module. PCS_C[4] is a peripheral chip select output pin for the DSPI C module. SOUT_D is the serial data output from the DSPI_D module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-20 Freescale Semiconductor...
Page 56: Port D Pins
PD1 — GPIO (PD[1]) / CAN_A Receive (CNRX_A) / DSPI_D Peripheral Chip Select (PCS_D[4]) PD[1] is a GPIO pin. CNRX_A is the receive pin for the FlexCan A module. PCS_D[4] is a peripheral chip select for the DSPI_D module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-21 Preliminary...
Page 57 C Serial Clock Line (SCL_A) PD[8] is a GPIO pin. TXD_B is the transmit pin for the eSCI_B module. SCL_A is the serial clock signal for the I C_A module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-22 Freescale Semiconductor Preliminary...
Page 58 PD15 — GPIO (PD[15]) / DSPI_B Data Input (SIN_B) / eMIOS Channel (eMIOS[6]) PD[15] is a GPIO pin. SIN_B is the data input pin for the DSPI B module. eMIOS[6] is an output-only channel pin for the eMIOS200 module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-23 Preliminary...
Page 59: Port E Pins
In a 3-pin MLB interface, MLBDAT_BUFEN controls the external level shifter for the MLBDAT pin. In a 5-pin MLB interface, MLBDO carries user data from the emulated MLB module to the MOST network controller. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-24 Freescale Semiconductor...
Page 60: Port F Pins
MOST network controller. In a 5-pin interface, MLBSI carries signal line data from the MOST network controller to the emulated MLB module. MSEO is an output that indicates when messages start and end on the MDO pins. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-25...
Page 61 PF[7] is a GPIO pin. AD[13] is the EBI multiplexed address and data bus. ADDR[13] is the EBI non multiplexed address bus. MDO[3] is a trace message output to the development tools. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-26...
Page 62 PF[15] is a GPIO pin. WE[1] specifies which data pins contain valid data for an external bus transfer. TEA indicates that an error occurred in the current external bus transfer. CNRX_D is the receive pin for the FlexCan D module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-27...
Page 63: Port G Pins
PG6 — GPIO (PG[6]) / EBI Multiplex Address/Data (AD[22]) / eMIOS Channel (eMIOS[22]) PG[6] is a GPIO pin. AD[22] is the EBI multiplexed address and data bus. eMIOS[22] is an input/output channel pin for the eMIOS200 module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-28 Freescale Semiconductor Preliminary...
Page 64 PG14 — GPIO (PG[14]) / EBI Multiplex Address/Data (AD[30]) / DSPI_C Data Out (SOUT_A) PG[14] is a GPIO pin. AD[24] is the EBI multiplexed address and data bus. SOUT_A is the data output pin for the DSPI A module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-29 Preliminary...
Page 65: Port H Pins
PH[5] is a GPIO pin. AN[22] is a single-ended analog input pin. RXD_E is the receive pin for the eSCI_E module. MA[1] is a address output for an external analog mux used to select the mux input channel to connect to the QADC. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-30 Freescale Semiconductor...
Page 66 PH[13] is a GPIO pin. 2.7.8.15 PH14 — GPIO (PH[14]) / EBI Write Enable (WE[2]) PH[14] is a GPIO pin. WE[2] specifies which data pins contain valid data for an external bus transfer. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-31 Preliminary...
Page 67: Port J Pins
PJ14 is a GPIO pin. SOUT_D is the SPI serial data out for the DSPI_D module. 2.7.9.9 PJ15 - GPIO (PJ15) / DSPI_D Serial Data In (SIN_D) PJ15 is a GPIO pin. SIN_D is the SPI serial data in for the DSPI_D module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-32 Freescale Semiconductor Preliminary...
Page 68: Port K Pins
TDO provides the serial test data output for the on-chip test logic. 2.7.11.7 TMS — JTAG Test Mode Select Input TMS controls test mode operations for the on-chip test logic. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-33 Preliminary...
Page 69: Power And Ground Pins
REFBYPC pin and VRL. 2.7.12.7 VDDSYN — Clock Synthesizer Supply VDDSYN is the supply power for the FMPLL. 2.7.12.8 VSSSYN — Clock Synthesizer Ground VSSSYN is the ground reference for the FMPLL. MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-34 Freescale Semiconductor Preliminary...
Page 70 VDDEx is the 3.3 V to 5.0 V external I/O supply independently controlling the level for one of three groups of I/O pins. (x=1,2,3.) 2.7.12.14 VSSEx — External I/O Ground VSSEx is the external I/O ground for one of three groups of I/O pins. (x=1,2,3.) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 2-35 Preliminary...
Page 71 Signal Descriptions MPC5510 Microcontroller Family Reference Manual, Rev. 1 2-36 Freescale Semiconductor Preliminary...
Page 72: Introduction
System Clock Description Introduction The MPC5510 supports several clock sources that include an internal phase-locked loop (PLL), an external high-frequency crystal (XOSC), an external low-frequency crystal (32kOSC), an internal high-frequency RC oscillator (IRC), and an internal low-frequency RC oscillator (32kRC).
Page 73: External High-Frequency Crystal (Xosc)
3.2.1 External High-Frequency Crystal (XOSC) The MPC5510 features an internal automatic level control (ALC) oscillator. The oscillator is designed for optimal startup margin with typical crystal oscillators. Oscillator power is supplied from its own 3.3 V PLL supply voltage generated by the voltage regulator to minimize noise. The oscillator provides the reference clock for the entire chip.
Page 74: External Low-Frequency Crystal (32Kxosc)
Always enabled except optionally disabled in sleep modes when not being used 3.2.4 Internal Low-Frequency RC Oscillator (32kRC) The MPC5510 includes a 32 kHz internal RC oscillator that is intended to be used as a highly reliable clock source during low-power modes. Features: •...
Page 75: System Clock Architecture Block Diagram
System Clock Description System Clock Architecture Block Diagram To optimize system power consumption, the MPC5510 supports both system- and peripheral-level clock dividers, and static clock gating using peripheral-level module disable (MDIS) bits and a system-level halt mechanism. Figure 3-2 shows the device-level clock gating mechanism for the MPC5510.These features are detailed in subsequent sections.
Page 76: Clock Dividers
CLKOUT and MCKO. 3.4.5 Peripheral Clock Dividers The peripheral clock dividers provide a mechanism to reduce run power when it is not necessary to clock peripherals at the full system clock frequency. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 77: Software-Controlled Power Management
LPCLKDIV7 Reserved The MPC5510 implements a single clock divider circuit that uses the system clock as its source. The LPCLKDIV bits control which clock divide tap is used for each module grouping clock gate enable. The resultant gated clocks will be at the desired frequency but are clock pulses instead of a 50% duty cycle (the high clock pulse width is half the system clock period).
Page 78: Halt Clock Gating
Executing the WAIT instruction puts the corresponding core in an idle state at a clean transition point. When the core stops, clocks to the core are gated off, and the core MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 79: Alternate Module Clock Domains
To prevent improper FlexRay behavior, the system clock or the FlexRay protocol engine clock source must be switched and stable before enabling the FlexRay module. After it is enabled, the FlexRay module can be disabled only by asserting RESET. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 80: Rtc Clock Domain
To prevent improper software watchdog timer (SWT) behavior when switching the system clock source, or before the desired clock source has stabilized, the SWT must first be disabled by clearing the MCM_MSWTCR[SWE] = 0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 81 System Clock Description MPC5510 Microcontroller Family Reference Manual, Rev. 1 3-10 Freescale Semiconductor Preliminary...
Page 82: Introduction
ERFD Used to create the EMFD loss of clock reset request and decide which PLL mode to LOC_PLL switch to when these things happen LOC_REF Figure 4-1. FMPLL Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 83: Features
Input clock frequency range: 4 MHz to 40 MHz (EXTAL pin) • Because the MPC5510 uses a 16 MHz IRC as its default system clock, the FMPLL will be put in PLL Off mode during reset, so that power dissipation is minimized by disabling the FMPLL until needed by the system.
Page 84: Module Memory Map
Access: User read/write Reset LOLF LOCF CAL LOC MODE LOCKS LOCK DONE PASS Reset Figure 4-2. FMPLL Synthesizer Status Register (SYNSR) Table 4-2. SYNSR Register Field Descriptions Field Description bits 0–21 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 85 1 PLL has not lost lock since last system reset, a write to ESYNCR1 to modify the ESYNCR1[EMFD] bit field, or frequency modulation enabled 0 PLL has lost lock since last system reset, a write to ESYNCR1 to modify the ESYNCR1[EMFD] bit field, or frequency modulation enabled MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 86: Features
This is one of two FMPLL synthesizer control registers that are used to access enhanced features in the FMPLL. The bit fields in the ESYNCR1 behave as described in Figure 4-3. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 87 LOLRE bit before writing the EPREDIV bits. In PLL Off mode the EPREDIV bits have no affect. The available enhanced pre-divider ratios are given in Table 4-5. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 88 0010 0011 0100 0101 0110 Invalid 0111 1000 Invalid 1001 1010–1111 Invalid Table 4-6. Enhanced Feedback Divide Ratios EMFD Feedback Divide Ratio (EMFD+16) 0000_0000–0001_1111 Invalid 0010_0000 0010_0001 0010_0010 0010_0011 0010_0100 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 89 When operating in normal PLL mode, the PLL must be locked before setting the LOLRE bit. Otherwise reset is immediately asserted. The LOLRE bit has no affect in PLL Off mode. 1 Assert reset on loss of lock enabled. 0 Assert reset on loss of lock disabled. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 90 (LOCK) is set, to avoid surpassing the allowable system operating frequency. In PLL Off mode the ERFD bits have no affect. The available enhanced output divider ratios are given in Table 4-10. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 91 Table 4-10. Enhanced Output Divide Ratios ERFD Output Divide Ratio (ERFD+1) 00_0000 00_0001 00_0010 Invalid 00_0011 00_0100 Invalid 00_0101 6 (default value for MPC5510) 00_0110 Invalid 00_0111 11_1100 Invalid 11_1101 11_1110 Invalid 11_1111 MPC5510 Microcontroller Family Reference Manual, Rev. 1 4-10 Freescale Semiconductor Preliminary...
Page 92: Functional Description
PLL Off mode. The selected clock is directly used to produce the various system clocks. Refer to MPC5510 Microcontroller Family Data Sheet for external clock input requirements. In bypass mode, the analog portion of the PLL is disabled, the frequency modulation capability is not available, and no clocks are generated at the PLL output.
Page 93 N + K back cycles compare sequence. in same count and elapsed. compare sequence. Figure 4-5. Lock Detect Sequence MPC5510 Microcontroller Family Reference Manual, Rev. 1 4-12 Freescale Semiconductor Preliminary...
Page 94 LOC circuitry considers the clock to have failed and a loss-of-clock status is reflected by the sticky LOCF bit, and non-sticky LOC bit in the SYNSR. See MPC5510 Microcontroller Family Data Sheet for the minimum clock frequency. In PLL Off mode, the loss-of-clock circuitry is disabled.
Page 95 It is critical that the system clock frequency remain within the range for the device (see MPC5510 Microcontroller Family Data Sheet). The output of the FMPLL can be divided down in powers of two up to 128 to reduce the system frequency with the ERFD. The ERFD is not contained in the feedback loop of the PLL, so changing the ERFD bits does not affect FMPLL operation.
Page 96 Based on the desired system clock frequency, EPREDIV, EMFD, and ERFD must be calculated for the given crystal or external reference frequency. See MPC5510 Microcontroller Family Data Sheet for the max/min VCO frequency range and the maximum allowable system frequency.
Page 97 COUNT0 register. The calibration system then enables modulation at programmed ΔFm and the VCO gets time to settle. Both counters are reset and restarted. The feedback counter begins to count full VCO clock MPC5510 Microcontroller Family Reference Manual, Rev. 1 4-16...
Page 98 Finally, the error due to the manufacturing and environment variation alone can cause the frequency modulation depth error to be greater than 20 percent. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 4-17...
Page 99: Resets
The PLL will not operate until the POR signal has negated and the CLKCFG set for PLL mode. Refer to MPC5510 Microcontroller Family Data Sheet for these thresholds. At this point, the PLL will operate in self-clocked mode (SCM) until a valid reference clock is detected by the internal clock monitor circuit.
Page 100: Pll Loss-Of-Lock Reset
When a loss-of-clock condition is recognized, the PLL will request an interrupt if the LOCIRQ bit in the SYNCR is set. The LOCIRQ bit has no affect in bypass mode or if LOCEN is equal to 0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 101 Frequency Modulated Phase Locked Loop (FMPLL) MPC5510 Microcontroller Family Reference Manual, Rev. 1 4-20 Freescale Semiconductor Preliminary...
Page 102: Introduction
There are also several miscellaneous integration functions included in the CRP that are discussed in detail in later sections of this chapter. 5.1.1 Block Diagram A simplified block diagram of the CRP illustrates the functionality and interdependence of major blocks (see Figure 5-1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 103 RESET CONTROL WAKEUP, POWER STATUS RTC / INPUT ISOLATION SRC/WELL POWER ISOLATION SWITCHES BIAS LOGIC VREG KEEPER CLOCK SYSTEM CONTROL CLOCK SEA-OF-GATES BLOCK LOGIC BLOCKS Figure 5-1. CRP Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 104: Features
The voltage regulator, LVI, and power switch outputs are in the enabled state. The RTC/API and associated interrupts are optionally enabled. In sleep and stop modes, the bus interface MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 105: Memory Map And Registers
0x0070 CRP_SOCSC — SoC Status and Control Register 0x0000_0000 5.2.2.10/5-15 5.2.2 Register Descriptions This section lists the CRP registers in address order and describes the registers and their bit fields. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 106 0 32K OSC disabled 1 32K OSC enabled Note: After enabling the 32K OSC, software needs to wait the required crystal startup/stabilization time before making use of the 32K OSC. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 107 APIVAL Reset These bits are only reset by power-on, VDD15 LVI, VDD33 LVI, and VDDSYN LVI, VDD5 low LVI, and VDD5 LVI. Figure 5-3. RTC Status and Control Register (CRP_RTCSC) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 108 00 32 kHz IRC 01 32 kHz OSC 10 16 MHz IRC with 512 prescaler divide 11 16 MHz IRC without 512 prescaler divide MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 109 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 WKPSEL 0 WKPSEL 0 WKPSEL 0 WKPSEL 0 WKPSEL 0 WKPSEL 0 WKPSEL 0 WKPSEL Reset 0 Figure 5-5. Wakeup Pin Source Select Register (CRP_WKPINSEL) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 110 Wakeup clock select Offset: CRP_BASE + 0x0044 Access: User read/write WKPDET7 WKPDET6 WKPDET5 WKPDET4 WKPDET3 WKPDET2 WKPDET1 WKPDET0 Reset RTCOVR RTCWK APIWK WKCLK Reset Figure 5-6. Wakeup Source Enable Register (CRP_WKSE) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 111 Z1 Reset Vector Register (CRP_Z1VEC) The CRP_Z1VEC register contains: • Recovery vector for the Z1 core • Reset for the Z1 core • VLE select for the Z1 core MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-10 Freescale Semiconductor Preliminary...
Page 112 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-8. Z0 Reset Vector Register (CRP_Z0VEC) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 113 This register may be used by the user software to indicate where in RAM a recovery routine exists. On reset, this register defaults to 0xFFFF_FFFC so that it points to the same location as the Z1VEC and Z0VEC registers. MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-12 Freescale Semiconductor...
Page 114 Offset:CRP_BASE + 0x0060 Access: User read/write PWKSRCF w1c w1c w1c w1c w1c w1c w1c w1c Reset SLEEP STOP RAMSEL PWKSRIE[0:7] PKREL Reset Figure 5-10. Power Status and Control Register (CRP_PSCR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 5-13 Preliminary...
Page 115 The PKREL bit is write only and always reads 0. 0 No effect 1 The I/O states held by the pad keepers are released back to normal functions MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-14 Freescale Semiconductor...
Page 116 These bits are only reset by power on, VDD15 LVI, VDD33 LVI, VDDSYN LVI, and VDD5 Low LVI. These bits are only reset by power on, VDD15 LVI, VDD33 LVI, VDDSYN LVI, VDD5 Low LVI, and VDD5 LVI. Figure 5-11. LVI Status and Control Register (CRP_SOCSC) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 5-15...
Page 117: Functional Description
JTAG and Nexus debug capability. The following sections discuss in detail the entry sequence, the operation, and the exit sequence for the low power modes. MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-16...
Page 118: Low-Power Mode Entry
WAIT instruction. If only one core is active, and one is held in reset by the user, then executing the WAIT MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 119: Low-Power Operation
Figure 5-16 give the same diagram for RUN mode to stop, and back to RUN mode. The CRP does not support going directly to/from Sleep mode from/to stop mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-18 Freescale Semiconductor Preliminary...
Page 120 SLEEP/STOP - Assert TDO OBE 3 clks Clock stop asserted by CCB? Sleep mode Go to Figure 5-13 Go to Figure 5-15 requested? Figure 5-12. SLEEP/STOP Mode Entry Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 5-19 Preliminary...
Page 121 PwrGate fetode circuit switch switch close) close) wait wait 10 clks 5 usec - Disable isolation Go to Figure 5-14 Figure 5-13. SLEEP Mode Transition Diagram (Part 1) MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-20 Freescale Semiconductor Preliminary...
Page 122 - Negate TDO Pin - Clear NPC PCR Sleep Sync Bit Allow NPC input Go to INIT signals to propagate (Figure 5-12) 5 clks Figure 5-14. SLEEP Mode Transition Diagram (Part 2) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 5-21 Preliminary...
Page 123 Go to Figure 5-16 enables - Enable LVIs (well voltage = 1.5V) wait wait 5 usec 10 clocks Figure 5-15. STOP Mode Transition Diagram (Part 1) MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-22 Freescale Semiconductor Preliminary...
Page 124 Pins that are to be used for wakeup from sleep/stop modes, must have the IBE enabled in the SIU PCR prior to sleep/stop entry. If a pullup/down is enabled on an input pin prior to entry into sleep or stop mode, it will remain enabled during the low-power mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 5-23...
Page 125: Low-Power Wakeup
64 possible external pin wakeup sources. External pin wakeup source selection is done in the CRP_WKPINSEL register, and Table 5-8 gives the I/O pin mapping to the eight external pin wakeup MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-24 Freescale Semiconductor Preliminary...
Page 126 A block diagram for the external pin wakeup logic is given in Figure 5-17. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 5-25 Preliminary...
Page 127 In order for the debug tool not to miss instruction execution, the CRP does not assert the wakeup interrupt to the Z0 and Z1 cores until after the debug tool has acknowledged the TDO assertion. MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-26...
Page 128: Debug Mode
SLEEP/STOP with the pad keepers enabled, and debug enabled. In this case, the low power mode will function as normal, but there is no capability for synchronization with the debug tool. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 129: Real-Time Counter (Rtc)
The RTC also supports an autonomous periodic interrupt function used to generate a periodic wakeup request to exit a low-power sleep mode or an interrupt request. 5.4.1 RTC Features Features of the RTC include: • 32-bit counter • Selectable counter clock sources MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-28 Freescale Semiconductor Preliminary...
Page 130: Rtc Functional Description
If there is a match while in a sleep or stop mode, and the CRP_WKSE[RTCWKEN] bit is set, then the RTC will first generate a wakeup request to force a wakeup MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 131 RUN mode, then the APIF flag will be set. The API wakeup flag is captured in the CRP_PSCR[WKAPIF] bit. The RTC counter is unaffected during debug mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-30 Freescale Semiconductor...
Page 132: Register Description
RTC are as follows. • RTC status and control register (Section 5.2.2.2, “RTC Status and Control Register (CRP_RTCSC)”) • RTC counter register (Section 5.2.2.3, “RTC Counter Register (CRP_RTCCNT)”) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 5-31 Preliminary...
Page 133: Power Supply Monitors
The LVI5 is normally configured to generate a reset if the supply voltage is below 4.5 V. If this is always the desired function, then set the CRP_SOCSC[LVI5RE] to enable the reset function and set the write-once CRP_SOCSC[LVI5LOCK] bit to prevent any unintentional changes to the CRP_SOCSC[LVI5RE] bit. MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-32 Freescale Semiconductor...
Page 134 CRP_SOCSC[LVI5HF] interrupt request), the LVI5 is configured for an interrupt function instead of a reset function. Low-voltage operation below 4.0 V is not supported, as the LVI5L will force a reset at this point. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 5-33...
Page 135 Clock, Reset, and Power Control (CRP) MPC5510 Microcontroller Family Reference Manual, Rev. 1 5-34 Freescale Semiconductor Preliminary...
Page 136: Introduction
SIU. The signals shown are external pins to the device. The SIU registers are accessed through the crossbar switch. The power-on reset (POR) detection block, pad interface/pad ring block, and peripheral I/O channels are external to the SIU. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 137: Features
Triggers Peripheral I/O Channels Figure 6-1. SIU Block Diagram 6.1.2 Features Features include the following: • System configuration — MCU reset configuration via external pins — Pad configuration control MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 138: Modes Of Operation
In normal mode, the SIU provides the register interface and logic that controls system configuration, the reset controller, GPIO, clock divider control, and peripheral clock disable/acknowledge. 6.1.3.2 Debug Mode SIU operation in debug mode is identical to normal mode operation. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 139: External Signal Description
PD[10] is a GPIO pin. NMI0 is the critical interrupt input for the e200z1 core. PD[11] is a GPIO pin. NMI1 is the critical interrupt input for the e200z0 core. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 140: Memory Map And Registers
0x0800–0x0891 SIU_GPDI0_3 – SIU_GPDI144_145 — GPIO Pin Data Input — 6.3.2.15/6-26 Register 0-3 –GPIO Pin Data Input Register 144-145 0x0892–0x08FF Reserved 0x0900–0x0903 SIU_ISEL0 — IMUX Select Register 0 0x0000_0000 6.3.2.16/6-27 0x0904–0x0907 SIU_ISEL1— IMUX Select Register 1 0x0000_0000 6.3.2.17/6-28 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 141 Table 6-2. Detailed Memory Map for SIU_PCR, SIU_GPDO, and SIU_GPDI SIU_PCR SIU_GPDO SIU_GPDI Pad ID Pad # Address Address Address FFFE8040 FFFE8800 FFFE8042 FFFE8801 FFFE8044 FFFE8802 FFFE8046 FFFE8803 FFFE8048 FFFE8804 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 142 FFFE8078 FFFE861C FFFE881C PB13 FFFE807A FFFE861D FFFE881D PB14 FFFE807C FFFE861E FFFE881E PB15 FFFE807E FFFE861F FFFE881F FFFE8080 FFFE8620 FFFE8820 FFFE8082 FFFE8621 FFFE8821 FFFE8084 FFFE8622 FFFE8822 FFFE8086 FFFE8623 FFFE8823 FFFE8088 FFFE8624 FFFE8824 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 143 FFFE80B8 FFFE863C FFFE883C PD13 FFFE80BA FFFE863D FFFE883D PD14 FFFE80BC FFFE863E FFFE883E PD15 FFFE80BE FFFE863F FFFE883F FFFE80C0 FFFE8640 FFFE8840 FFFE80C2 FFFE8641 FFFE8841 FFFE80C4 FFFE8642 FFFE8842 FFFE80C6 FFFE8643 FFFE8843 FFFE80C8 FFFE8644 FFFE8844 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 144 FFFE80F8 FFFE865C FFFE885C PF13 FFFE80FA FFFE865D FFFE885D PF14 FFFE80FC FFFE865E FFFE885E PF15 FFFE80FE FFFE865F FFFE885F FFFE8100 FFFE8660 FFFE8860 FFFE8102 FFFE8661 FFFE8861 FFFE8104 FFFE8662 FFFE8862 FFFE8106 FFFE8663 FFFE8863 FFFE8108 FFFE8664 FFFE8864 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 145 FFFE867C FFFE887C PH13 FFFE813A FFFE867D FFFE887D PH14 FFFE813C FFFE867E FFFE887E PH15 FFFE813E FFFE867F FFFE887F FFFE8140 FFFE8680 FFFE8880 FFFE8142 FFFE8681 FFFE8881 FFFE8144 FFFE8682 FFFE8882 FFFE8146 FFFE8683 FFFE8883 FFFE8148 FFFE8684 FFFE8884 MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-10 Freescale Semiconductor Preliminary...
Page 146: Register Descriptions
The mask number is a read-only field mask-programmed with the device’s specific mask revision level. Offset: SIU_BASE + 0x0004 Access: User read PARTNUM Reset MASKNUM_MAJOR MASKNUM_MINOR Reset Figure 6-2. MCU ID Register (SIU_MIDR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-11 Preliminary...
Page 147 Chip Scale Package. The CSP bit indicates whether the die is mounted in a chip scale package. 0 Not a chip scale package. 1 Chip scale package. Package Configuration. These values set the pin package used for each MPC5510 device. 01101 144-pin LQFP 10001 176-pin LQFP...
Page 148 0 Last reset source the reset controller acknowledged was not a watchdog timer or debug reset. 1 Last reset source the reset controller acknowledged was a watchdog timer or debug reset. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 149 The software system reset is processed as a synchronous reset. The bit is automatically cleared on the assertion of any other reset source except a software external reset. 0 Do not generate a software system reset. 1 Generate a software system reset. bits 1–15 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-14 Freescale Semiconductor Preliminary...
Page 150 R EIF15 EIF14 EIF13 EIF12 EIF11 EIF10 EIF9 EIF8 EIF7 EIF6 EIF5 EIF4 EIF3 EIF2 EIF1 EIF0 w1c w1c w1c Reset Figure 6-5. SIU External Interrupt Status Register (SIU_EISR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-15 Preliminary...
Page 151 The SIU_DIRSR selects between DMA and interrupt requests. If the corresponding bits are set in SIU_EISR and the SIU_DIRER, then the DMA/interrupt request select bit determines whether a DMA or interrupt request is asserted. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-16 Freescale Semiconductor...
Page 152 SIU_BASE + 0x0020 Access: User read/write Reset R OVF15 OVF14 OVF13 OVF12 OVF11 OVF10 OVF9 OVF8 OVF7 OVF6 OVF5 OVF4 OVF3 OVF2 OVF1 OVF0 Reset Figure 6-8. Overrun Status Register (SIU_OSR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-17 Preliminary...
Page 153 IRQ Rising-Edge Event Enable Register (SIU_IREER) The SIU_IREER allows rising-edge-triggered events to be enabled on the corresponding IRQn pins. Setting the corresponding bits in the SIU_IREER and SIU_IFEER enables rising- and falling-edge events. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-18 Freescale Semiconductor...
Page 154 R NFEE0 NFEE1 Reset R IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE Reset Figure 6-11. IRQ Falling-Edge Event Enable Register (SIU_IFEER) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-19 Preliminary...
Page 155 IRQ input pins with the system clock. 6.3.2.12 IRQ Filtered Input Register (SIU_IFIR) This is a read only register that captures the output of the NMIn and IRQn digital input filters. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-20 Freescale Semiconductor Preliminary...
Page 156 For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally, and the IBE and OBE bits have no effect. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 157 Output Buffer Enable. Enables the pad as an output and drives the output buffer enable signal. 0 Output buffer for the pad disabled. 1 Output buffer for the pad enabled. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-22 Freescale Semiconductor...
Page 158 Actual slew rate is dependent on the pad type and load. See the MPC5510 Microcontroller Family Data Sheet for this information. 00 Minimum slew rate (slowest)
Page 159 NOTE On MPC5510, the Port A and Port K pins are only general-purpose inputs. Therefore, there are no output data registers associated with these pins. The SIU_GPDOx_x registers are written to by software to drive data out on the external GPIO pin. Each byte of a register drives a single external GPIO pin, which allows the pin state to be controlled independently from other GPIO pins.
Page 160 0x0638 PD8-PD11 60_63 0x063C PD12-PD15 64_67 0x0640 PE0-PE3 68_71 0x0644 PE4-PE7 72_75 0x0648 PE8-PE11 76_79 0x064C PE12-PE15 80_83 0x0650 PF0-PF3 84_87 0x0654 PF4-PF7 88_91 0x0658 PF8-PF11 92_95 0x065C PF12-PF15 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-25 Preliminary...
Page 161 Pin Data In. This bit reflects the input state on the external GPIO pin associated with the register. 0 Signal on pin is less than or equal to V 1 Signal on pin is greater than or equal to V MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-26 Freescale Semiconductor Preliminary...
Page 162 132_135 0x0884 PJ4–PJ7 136_139 0x0888 PJ8–PJ11 140_143 0x088C PJ12–PJ15 144_145 0x0890 PK0–PK1 6.3.2.16 IMUX Select Register 0 (SIU_ISEL0) The SIU_ISEL0 register selects the source for the EQADC trigger inputs. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-27 Preliminary...
Page 163 00 PC4 pin 01 PG4 pin 10 PIT 7 11 PIT 8 bits 8–31 Reserved. 6.3.2.17 IMUX Select Register 1 (SIU_ISEL1) The SIU_ISEL1 selects the source for the external interrupt/DMA inputs. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-28 Freescale Semiconductor Preliminary...
Page 164 External IRQ Input Select 11. Specifies input for IRQ11. 00 PB12 01 PD11 10 PF11 11 PG9 ESEL10 External IRQ Input Select 10. Specifies input for IRQ10. 00 PD9 01 PF14 10 PG7 11 PC6 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-29 Preliminary...
Page 165 External IRQ Input Select 3. Specifies input for IRQ3. 00 PA3 01 PB10 10 PD8 11 PC1 ESEL2 External IRQ Input Select 2. Specifies input for IRQ2. 00 PA2 01 PB5 10 PD6 11 PC0 MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-30 Freescale Semiconductor Preliminary...
Page 166 SELEMIOS14 eMIOS[14] Input Select. The source of the input for the eMIOS[14] timer channel is selected according to the SELEMIOS14 field. 00 eMIOS[14] input pin 01 DSPI_A deserialized output 10 DSPI_B deserialized output 11 DSPI_C deserialized output MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-31 Preliminary...
Page 167 SELEMIOS6 eMIOS[6] Input Select. The source of the input for the eMIOS[6] timer channel is selected according to the SELEMIOS6 field. 00 eMIOS[6] input pin 01 DSPI_A deserialized output 10 DSPI_B deserialized output 11 DSPI_C deserialized output MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-32 Freescale Semiconductor Preliminary...
Page 168 SELEMIOS0 eMIOS[0] Input Select. The source of the input for the eMIOS[0] timer channel is selected according to the SELEMIOS0 field. 00 eMIOS[0] input pin 01 DSPI_A deserialized output 10 DSPI_B deserialized output 11 DSPI_C deserialized output MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-33 Preliminary...
Page 169 The SIU_ECCR controls the timing relationship between the system clock and the external clocks, CLKOUT. All bits and fields in the SIU_ECCR are read/write and reset by the asynchronous reset signal. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-34 Freescale Semiconductor...
Page 170 Compare A High Register (SIU_CMPAH) The SIU_CMPAH register holds the 32-bit value that is compared against the value in the SIU_CMPBH register. The CMPAH field is read/write and reset by the asynchronous reset signal. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-35...
Page 171 The CMPBH field is read/write and reset by the asynchronous reset signal. Offset: SIU_BASE + 0x0990 Access: User read-only CMPBH Reset CMPBH Reset Figure 6-26. Compare B High Register (SIU_CMPBH) MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-36 Freescale Semiconductor Preliminary...
Page 172 The SIU_SYSCLK register controls the source for the system clock, the divider for the system clock, and eight fields that control the clock divider for groups of peripherals. For a listing of which peripherals are associated with which LPCLKDIV bit on MPC5510, see Section 3.4.5, “Peripheral Clock Dividers.”...
Page 173 The SIU_HLT register is used to disable the clocks to various modules. Each bit drives a separate halt request to the associated peripheral. Table 6-28 shows these connected outputs. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-38 Freescale Semiconductor Preliminary...
Page 174 The SIU_HLTACK bits indicate that the peripheral requested to halt via the HLT bit has completed the halt process and has entered a halted state with the peripheral clocks disabled. The HLTACK bits are read-only MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 175 Note: Writes to reserved HLT bits 4, 5, and 11 are reflected in the reserved HLTACK bits 4, 5, and 11. 6.3.2.28 Parallel GPIO Pin Data Output Register 0 (SIU_PGPDO0) The SIU_PGPDO0 register contains the parallel GPIO pin data output for PB[0:15]. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-40 Freescale Semiconductor Preliminary...
Page 176 Reads and writes to this register are coherent with the registers SIU_GPDO16_19, SIU_GPDO20_23, SIU_GPDO24_27, and SIU_GPDO28_31. NOTE On MPC5510, the port A pins are general-purpose inputs only. Therefore, there are no parallel GPIO pin data output register bits for port A. Offset:...
Page 177 Reads and writes to this register are coherent with the registers SIU_GPDO18_131, SIU_GPDO132_135, SIU_GPDO136_139, and SIU_GPDO140_143. NOTE On MPC5510, the port K pins are only inputs. Therefore, there are no parallel GPIO pin data output bits associated with port K. MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 178 Reads to the SIU_PGPDI1 register provide the parallel GPIO pin data input for PC0:PC15 and PD0:PD15. Writes have no effect. Reads of this register are coherent with the registers SIU_GPDI32_35, SIU_GPDI36_39, SIU_GPDI40_43, SIU_GPDI44_47, SIU_GPDI48_51, SIU_GPDI52_55, SIU_GPDI56_59, and SIU_GPDI60_63. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-43 Preliminary...
Page 179 Reads to the SIU_PGPDI2 register provide the parallel GPIO pin data input for PG0:PG15 and PH0:PH15. Writes have no effect. Reads of this register are coherent with the registers SIU_GPDI96_99, SIU_GPDI100_103, SIU_GPDI104_107, SIU_GPDI108_111, SIU_GPDI112_115, SIU_GPDI116_119, SIU_GPDI120_123, and SIU_GPDI124_127. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-44 Freescale Semiconductor Preliminary...
Page 180 This register always reads as 0. 6.3.2.38.1 Masked Parallel GPIO Pin Data Output Register 1 (SIU_MPGPDO1) The SIU_MPGPDO1 register contains the Masked Parallel GPIO Pin Data Output for PB[0:15]. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-45 Preliminary...
Page 181 Masked Parallel GPIO Pin Data Output Register 3 (SIU_MPGPDO3) The SIU_MPGPDO3 register contains the masked parallel GPIO pin data output for PD[0:15]. Writes to this register are coherent with the registers SIU_GPDO48_51, SIU_GPDO52_55, SIU_GPDO56_59, and SIU_GPDO60_63. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-46 Freescale Semiconductor Preliminary...
Page 182 Masked Parallel GPIO Pin Data Output Register 5 (SIU_MPGPDO5) The SIU_MPGPDO5 register contains the masked parallel GPIO pin data output for PF[0:15]. Writes to this register are coherent with registers SIU_GPDO80_83, SIU_GPDO84_87, SIU_GPDO88_91, and SIU_GPDO92_95. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-47 Preliminary...
Page 183 Masked Parallel GPIO Pin Data Output Register 7 (SIU_MPGPDO7) The SIU_MPGPDO7 register contains the masked parallel GPIO pin data output for PH[0:15]. Writes to this register are coherent with registers SIU_GPDO112_115, SIU_GPDO116_119, SIU_GPDO120_123, and SIU_GPDO124_127. MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-48 Freescale Semiconductor Preliminary...
Page 184: Functional Description
CAN or SCI boot. See Section 32.3.3.1.1, “Reset Configuration Halfword Read” of the BAM chapter for detail on the RCHW. Table 6-30 defines the boot modes specified by the SIU_RST[BOOTCFG] field. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 6-49 Preliminary...
Page 185: Reset Control
Each IRQ pin has a programmable filter for rejecting glitches on the IRQ signals. The filter length for the IRQ pins is specified in the external IRQ digital filter register (SIU_IDFR). MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-50 Freescale Semiconductor...
Page 186: Gpio Operation
As shown in the figure, the ETRIG[0] input of the eQADC can be connected to the PC4 pin, the PG4 pin, the PIT7 channel, or the PIT8 channel. Remaining ETRIG inputs are multiplexed in the same manner. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 187 IRQ[0] input of the SIU can be connected to the PA0 pin, PD0 pin, PD10, or PG11 pin. The remaining IRQ inputs are multiplexed in the same manner. IRQ[0] PG11 PD10 SIU_ISEL1[30:31] Figure 6-51. SIU External Interrupt Input Multiplexing MPC5510 Microcontroller Family Reference Manual, Rev. 1 6-52 Freescale Semiconductor Preliminary...
Page 188: Introduction
Chapter 7 Reset Introduction The reset sources supported in the MPC5510 are: • Power-on reset (POR) • Low-voltage inhibit (LVI) reset • External reset • Loss-of-lock reset • Loss-of-clock reset • Watchdog timer • JTAG reset • Checkstop reset (both Z1 and Z0 cores) •...
Page 189: Reset (Reset)
Z1, Z0 Cores Reset Vectors The reset vectors for the Z1 and Z0 cores in the MPC5510 MCU are controlled via the Z1VEC and Z0VEC registers in the Clock, Reset, and Power control (CRP) module. The power-on reset values for the Z1VEC and Z0VEC registers point to the first instruction of the BAM program.
Page 190: Reset Sources
Reset Sources 7.3.2.1 Power-on Reset (POR) The internal power-on reset signal is asserted when the voltage on the 5 V VDDA supply is below defined values. See the MPC5510 Microcontroller Family Data Sheet and Section 7.3.2.2, “Low-Voltage Inhibit (LVI) Resets.”...
Page 191: Reset Configuration
The timing diagram is also valid for internal/external resets assuming VDD, VDD33, and VDDA are within valid operating ranges. The value of the BOOTCFG pin is latched 4 clock cycles before the negation of the RESET pin and stored in the reset status register. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 192 2400 clocks Internal Reset (4 clock cycles) RESET BOOTCFG can be applied, BOOTCFG is latched. but not latched. User drives configuration pins relative to RESET Figure 7-1. Reset Configuration Timing MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 193 Reset MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 194: Introduction
— Software interrupts would be used for inter processor signaling. — A use-case for the MPC5510: use the DMA for simple data movement, the Z0 for data movement with some intermediate processing, and the Z1 for the main algorithm.
Page 195: Interrupt Vectors
IVPR + 2 KB INTC Hardware Vector Mode Interrupt Vectors Figure 8-1. MPC5510 Interrupt Vector Memory Map 8.2.1 Core Interrupts Table 8-1. MPC5510 Core Interrupt Vector Memory Map State Core Interrupt Type IVOR # Enables Examples Offset Saved In Critical Input...
Page 196: External Input: Software Vector Mode
Interrupts Table 8-1. MPC5510 Core Interrupt Vector Memory Map (continued) State Core Interrupt Type IVOR # Enables Examples Offset Saved In Data TLB Error IVOR 13 0x0D0 — SRR[0:1] Data TLB miss in MMU Instruction TLB Error IVOR 14 0x0E0 —...
Page 197: Critical Input
SIU_IREER or SIU_IFEER. (Note that these bits are “write once” bits.) When the NMI is taken, the flag must be cleared in the SIU_EISR. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 198: Interrupt Sources
MCM_MSWTIR_SWTIC 0x0820 MCM.MSWTIR[SWTIC] MCM software watchdog interrupt flag MCM combined interrupt request of the platform RAM non-correctable error and MCM.ESR[PRNCE] || MCM_ESR_COMB 0x0824 MCM.ESR[PFNCE] platform flash non-correctable error interrupt requests MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 199 Reserved Reserved Reserved 0x088C Reserved Reserved Reserved 0x0890 Reserved Reserved Reserved 0x0894 Reserved Reserved Reserved 0x0898 Reserved Reserved Reserved 0x089C Reserved Reserved Reserved 0x08A0 Reserved Reserved Reserved 0x08A4 Reserved Reserved MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 200 8 flag eMIOS200_FLAG_F9 0x090C eMIOS200.eMIOS200FLAG[F9] eMIOS200 channel 9 flag eMIOS200_FLAG_F10 0x0910 eMIOS200.eMIOS200FLAG[F10] eMIOS200 channel 10 flag eMIOS200_FLAG_F11 0x0914 eMIOS200.eMIOS200FLAG[F11] eMIOS200 channel 11 flag eMIOS200_FLAG_F12 0x0918 eMIOS200.eMIOS200FLAG[F12] eMIOS200 channel 12 flag MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 201 FIFO 1 drain flag eQADC command FIFO 2 non-coherency eQADC_FISR2_NCF2 0x0974 eQADC.eQADC_FISR2[NCF2] flag eQADC_FISR2_PF2 0x0978 eQADC.eQADC_FISR2[PF2] eQADC command FIFO 2 pause flag eQADC command FIFO 2 command eQADC_FISR2_EOQF2 0x097C eQADC.eQADC_FISR2[EOQF2] queue end-of-queue flag MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 202 CRC error, checksum error, frame SCI_A.LINSTAT1[TXRDY] || SCI_A.LINSTAT1[LWAKE] || complete interrupts requests, and LIN SCI_A.LINSTAT1[STO] || status register 2 receive register overflow SCI_A.LINSTAT1[PBERR] || interrupt request SCI_A.LINSTAT1[CERR] || SCI_A.LINSTAT1[CKERR] || SCI_A.LINSTAT1[FRC] || SCI_A.LINSTAT2[OVFL] MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 203 CRC error, checksum error, frame SCI_D.LINSTAT1[LWAKE] || complete interrupts requests, and LIN SCI_D.LINSTAT1[STO] || status register 2 receive register overflow SCI_D.LINSTAT1[PBERR] || interrupt request SCI_D.LINSTAT1[CERR] || SCI_D.LINSTAT1[CKERR] || SCI_D.LINSTAT1[FRC] || SCI_D.LINSTAT2[OVFL] MPC5510 Microcontroller Family Reference Manual, Rev. 1 8-10 Freescale Semiconductor Preliminary...
Page 204 FLEXCAN_A_IFLAG1_BUF10I 0x0A30 FLEXCAN_A.IFLAG1[BUF10I] FLEXCAN_A buffer 10 interrupt FLEXCAN_A_IFLAG1_BUF11I 0x0A34 FLEXCAN_A.IFLAG1[BUF11I] FLEXCAN_A buffer 11 interrupt FLEXCAN_A_IFLAG1_BUF12I 0x0A38 FLEXCAN_A.IFLAG1[BUF12I] FLEXCAN_A buffer 12 interrupt FLEXCAN_A_IFLAG1_BUF13I 0x0A3C 143 FLEXCAN_A.IFLAG1[BUF13I] FLEXCAN_A buffer 13 interrupt MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 8-11 Preliminary...
Page 205 FLEXCAN_B_IFLAG1_BUF9I 0x0AA4 FLEXCAN_B.IFLAG1[BUF9I] FLEXCAN_B buffer 9 interrupt FLEXCAN_B_IFLAG1_BUF10I 0x0AA8 FLEXCAN_B.IFLAG1[BUF10I] FLEXCAN_B buffer 10 interrupt FLEXCAN_B_IFLAG1_BUF11I 0x0AAC 171 FLEXCAN_B.IFLAG1[BUF11I] FLEXCAN_B buffer 11 interrupt FLEXCAN_B_IFLAG1_BUF12I 0x0AB0 FLEXCAN_B.IFLAG1[BUF12I] FLEXCAN_B buffer 12 interrupt MPC5510 Microcontroller Family Reference Manual, Rev. 1 8-12 Freescale Semiconductor Preliminary...
Page 206 [BUF31I:BUF16I] FLEXCAN_C.IFLAG2 FLEXCAN_C buffers 63–32 interrupts FLEXCAN_C_IFLAG2_BUF63_32I 0x0B18 [BUF63I:BUF32I] FLEXCAN_D bus off interrupt, FLEXCAN_D.ESR[BOFF_INT] || FLEXCAN_D_ESR_BOFF_INT 0x0B1C 199 FLEXCAN_D.ESR[TWRN_INT] || FLEXCAN_D transmit warning interrupt, FLEXCAN_D.ESR[RWRN_INT] FLEXCAN_D receive warning interrupt MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 8-13 Preliminary...
Page 207 FLEXCAN_E_IFLAG1_BUF2I 0x0B84 FLEXCAN_E.IFLAG1[BUF2I] FLEXCAN_E buffer 2 interrupt FLEXCAN_E_IFLAG1_BUF3I 0x0B88 FLEXCAN_E.IFLAG1[BUF3I] FLEXCAN_E buffer 3 interrupt FLEXCAN_E_IFLAG1_BUF4I 0x0B8C 227 FLEXCAN_E.IFLAG1[BUF4I] FLEXCAN_E buffer 4 interrupt FLEXCAN_E_IFLAG1_BUF5I 0x0B90 FLEXCAN_E.IFLAG1[BUF5I] FLEXCAN_E buffer 5 interrupt MPC5510 Microcontroller Family Reference Manual, Rev. 1 8-14 Freescale Semiconductor Preliminary...
Page 208 FLEXCAN_F_IFLAG1_BUF10I 0x0BF8 FLEXCAN_F.IFLAG1[BUF10I] FLEXCAN_F buffer 10 interrupt FLEXCAN_F_IFLAG1_BUF11I 0x0BFC 255 FLEXCAN_F.IFLAG1[BUF11I] FLEXCAN_F buffer 11 interrupt FLEXCAN_F_IFLAG1_BUF12I 0x0C00 FLEXCAN_F.IFLAG1[BUF12I] FLEXCAN_F buffer 12 interrupt FLEXCAN_F_IFLAG1_BUF13I 0x0C04 FLEXCAN_F.IFLAG1[BUF13I] FLEXCAN_F buffer 13 interrupt MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 8-15 Preliminary...
Page 209 CRC error, checksum error, frame SCI_E.LINSTAT1[TXRDY] || SCI_E.LINSTAT1[LWAKE] || complete interrupts requests, and LIN SCI_E.LINSTAT1[STO] || status register 2 receive register overflow SCI_E.LINSTAT1[PBERR] || interrupt request SCI_E.LINSTAT1[CERR] || SCI_E.LINSTAT1[CKERR] || SCI_E.LINSTAT1[FRC] || SCI_E.LINSTAT2[OVFL] MPC5510 Microcontroller Family Reference Manual, Rev. 1 8-16 Freescale Semiconductor Preliminary...
Page 210 CRC error, checksum error, frame SCI_H.LINSTAT1[LWAKE] || complete interrupts requests, and LIN SCI_H.LINSTAT1[STO] || status register 2 receive register overflow SCI_H.LINSTAT1[PBERR] || interrupt request SCI_H.LINSTAT1[CERR] || SCI_H.LINSTAT1[CKERR] || SCI_H.LINSTAT1[FRC] || SCI_H.LINSTAT2[OVFL] MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 8-17 Preliminary...
Page 211 The priorities are selected in INTC_PSRx_x, where the specific select register is assigned according to the vector. This column is for the user to fill in how they set their specific priorities. MPC5510 Microcontroller Family Reference Manual, Rev. 1 8-18...
Page 212: Interrupt Operation
8.4.3 Non Maskable Interrupt (NMI) The MPC5510 can be configured to use the pins PD[10] and PD[11] as non maskable interrupts (NMI) by providing a path to the critical interrupt input of the e200Z1 and e200z0 cores, respectively. After the SIU is configured by user code, an NMI cannot be prevented from reaching the assigned core.
Page 213: Dynamic Priority Elevation
Great care must be taken when using the priority elevation as it can enable a master to starve the rest of the masters in the system. 8.4.4.1 Hardware Implementation Dependent Register 1 The HID1 register is used for bus configuration and system control. HID1 is shown in Figure 8-6. MPC5510 Microcontroller Family Reference Manual, Rev. 1 8-20 Freescale Semiconductor Preliminary...
Page 214 Atomic status (read-only). Indicates state of the reservation bit in the load/store unit. bit 31 Reserved. These bits are not implemented and should be written with zero for future compatibility. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 8-21 Preliminary...
Page 215 Interrupts MPC5510 Microcontroller Family Reference Manual, Rev. 1 8-22 Freescale Semiconductor Preliminary...
Page 216: Introduction
When sending an interrupt to both cores, the user must take care to prevent the interrupt from going away from the other core when not expected. • 9-bit vector — Unique vector for each interrupt request source MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 217: Block Diagram
• Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor. 9.1.2 Block Diagram Figure 9-1 is a block diagram of the interrupt controller (INTC). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 218 Processor 1 Push/Update/Acknowledge 1 for Reads Memory Mapped Registers & Writes Processor 1 Pop Non-Memory Mapped Logic NOTE: Processor 0 is Z1 and Processor 1 is Z0. Figure 9-1. INTC Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 219: Modes Of Operation
LIFO and updating PRI in the associated INTC_CPR_PRCn does not occur when the associated interrupt acknowledge signal asserts and INTC_SSCIR0_3–INTC_SSCIR4_7 is written at a time such that the PRI value in the associated INTC_CPR_PRCn register would need to be pushed and the previously MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 220: Signal Description
0x0000_0000 9.3.2.5/9-10 for processor 1 (Z0) 0x0018 INTC_EOIR_PRC0—INTC end of interrupt register for 0x0000_0000 9.3.2.6/9-10 processor 0 (Z1) 0x001C INTC_EOIR_PRC1—INTC end of interrupt register for 0x0000_0000 9.3.2.7/9-11 processor 1 (Z0) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 221: Register Descriptions
The module configuration register is used to configure options of the INTC. Offset: 0x0000 Access: User read/write Reset VTES_ HVEN_ VTES_ HVEN_ PRC1 PRC1 PRC0 PRC0 Reset Figure 9-2. INTC Module Configuration Register (INTC_MCR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 222 An exception case in hardware vector mode to this behavior is described in Section 9.1.3.1.2, “Hardware Vector Mode”.” The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to Section 9.5.5, “Priority Ceiling Protocol.” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 223 Table 9-5. INTC_CPR_PRC1 Field Descriptions Field Description Priority. The function of this register is the same as described for processor 0 (Z1) in Section 9.3.2.2, “INTC Current Priority Register for Processor 0 (Z1) (INTC_CPR_PRC0).” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor Preliminary...
Page 224 The side effects are the same regardless of the size of the read. Reading the INTC_IACKR_PRC0 does not have side effects in hardware vector mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 225 INTC_EOIR_PRC0 are ignored. The values and sizes written to this register neither update the INTC_EOIR_PRC0 contents or affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0s to the INTC_EOIR_PRC0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-10 Freescale Semiconductor...
Page 226 Figure 9-9. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3]) Offset: 0x0024 Access: User read/write CLR4 CLR5 SET4 SET5 Reset CLR6 CLR7 SET6 SET7 Reset Figure 9-10. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7]) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 9-11 Preliminary...
Page 227 Figure 9-11. INTC Priority Select Register 0–3 (INTC_PSR0–3) Offset: 0x0164 Access: User read/write PRC_ PRC_ PRI292 PRI293 SEL292 SEL293 Reset Reset Figure 9-12. INTC Priority Select Register 292–293 (INTC_PSR292–293) MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-12 Freescale Semiconductor Preliminary...
Page 228 0x0118 INTC_PSR72_75 0x0088 INTC_PSR220_223 0x011C INTC_PSR76_79 0x008C INTC_PSR224_227 0x0120 INTC_PSR80_83 0x0090 INTC_PSR228_231 0x0124 INTC_PSR84_87 0x0094 INTC_PSR232_235 0x0128 INTC_PSR88_91 0x0098 INTC_PSR236_239 0x012C INTC_PSR92_95 0x009C INTC_PSR240_243 0x0130 INTC_PSR96_99 0x00A0 INTC_PSR244_247 0x0134 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 9-13 Preliminary...
Page 229 Interrupt request sent to processor 1 (Z0) NOTE When sending an interrupt to both cores, the user must take care to prevent the interrupt from going away from the other core when not expected. MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-14 Freescale Semiconductor Preliminary...
Page 230: Functional Description
INTC starts to drive the interrupt request to the processor is three clocks. Interrupt requests from devices external to the MPC5510 are classified as peripheral interrupt requests in this reference manual. External interrupts are handled by the SIU (see Section 6.4.3, “External...
Page 231: Priority Management
9.4.2.1.3 Vector Encoder Sub-block The vector encoder sub-block generates the unique 9-bit vector for the asserted interrupt request from the request selector sub-block for the associated processor. MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-16 Freescale Semiconductor Preliminary...
Page 232: Handshaking With Processor
0 was overwritten, it is regenerated with the popping of an empty LIFO. The LIFO is not memory mapped, even in debug mode. 9.4.3 Handshaking with Processor 9.4.3.1 Software Vector Mode Handshaking This section describes handshaking in software vector mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 9-17 Preliminary...
Page 233 Instead, after the restoration of the preempted context, the processor returns to the instruction address it was to execute before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-18 Freescale Semiconductor...
Page 234 The handshaking near the end of the interrupt exception handler, that is written to the associated INTC_EOIR_PRC0 or INTC_EOIR_PRC1, is the same as in software vector mode (see Section 9.4.3.1.2, “End of Interrupt Exception Handler”). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 9-19 Preliminary...
Page 235: Initialization/Application Information
PRI in INTC_CPR_PRCn to zero enable processor(s) recognition of interrupts 9.5.2 Interrupt Exception Handler These example interrupt exception handlers use Power Architecture assembly code. MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-20 Freescale Semiconductor Preliminary...
Page 236 4 instructions available, branch to continue interrupt_exception_handler_continuedn: code to save SRR0 and SRR1 code to enable processor recognition of interrupts and save context required by EABI MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 9-21 Preliminary...
Page 237: Isr, Rtos, And Task Hierarchy
However, the ability to meet deadlines with this scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software settable interrupt requests asserted. MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-22 Freescale Semiconductor...
Page 238: Priority Ceiling Protocol
Before ISR1 or ISR2 can access that resource, they must raise the PRI value in INTC_CPR_PRCn to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 239: Selecting Priorities According To Request Rates And Deadlines
The INTC has 16 priorities, which may be less than the number of ISRs. In this case, the ISRs should be grouped with other ISRs that have similar deadlines. For example, a priority could be allocated for every MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-24...
Page 240: Software Settable Interrupt Requests
Another application is the sharing of a block of data. For example, a first processor has completed accessing a block of data and wants a second processor to then access it. Furthermore, after the second MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 241: Lowering Priority Within An Isr
INTC_SSCIR0_3–INTC_SSCIR4_7 as the clearing of the flag bit that caused the present ISR to be executed (see Section 9.4.3.1.2, “End of Interrupt Exception Handler”). MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-26 Freescale Semiconductor Preliminary...
Page 242: Examining Lifo Contents
When the examination is complete, the LIFO can be restored using this code sequence: push_lifo: load stacked PRI value and store to INTC_CPR_PRCn load INTC_IACKR_PRCn if stacked PRI values are not depleted, branch to push_lifo MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 9-27 Preliminary...
Page 243 Interrupt Controller (INTC) MPC5510 Microcontroller Family Reference Manual, Rev. 1 9-28 Freescale Semiconductor Preliminary...
Page 244: Introduction
Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data BIUs. • Load/store unit — 1 cycle load latency MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-1 Preliminary...
Page 245: Microarchitecture Summary
— Power saving modes: doze, nap, sleep, and wait — Dynamic power management of execution units NOTE The MPC5510 does not use the core’s HID0[DOZE,NAP,SLEEP] bits to enter/exit low-power modes. Entry to and exit from low-power modes is managed by the CRP module.
Page 246: Instruction Unit Features
Data Control Load/ store unit Data bus interface unit Address Data Control Figure 10-1. e200z1 Block Diagram 10.2.1 Instruction Unit Features The features of the e200 instruction unit are: MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-3 Preliminary...
Page 247: Integer Unit Features
• Overlapped, in-order accesses 10.2.5 MMU Features The features of the MMU are as follows: • Virtual memory support • 32-bit virtual and physical addresses • 8-bit process identifier MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-4 Freescale Semiconductor Preliminary...
Page 248: Core Registers And Programmer's Model
0 bypass bit (MMUCSR0[Bypass]) is set to 1, so that address translation is not performed. If the MMUCSR0[Bypass] bit is 0, then the maximum system frequency will be less than the maximum frequency listed in the MPC5510 Microcontroller Family Data Sheet. 10.3 Core Registers and Programmer’s Model This section describes the registers implemented in the e200z1 core.
Page 249 1 - These e200-specific registers may not be supported by other Power Architecture processors L1CFG0 SPR 515 2 - Optional registers defined by the Power Architecture Book-E architecture Figure 10-2. e200z1 Supervisor Mode Programmer’s Model SPRs MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-6 Freescale Semiconductor Preliminary...
Page 250 General purpose registers (GPRs) are accessed through instruction operands. Access to other registers can be explicit (by using instructions for that purpose such as Move to Special Purpose Register ( ) and mtspr MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-7 Preliminary...
Page 251: Power Architecture Book E Registers
Purpose Registers (SPRGs). SPRG4 through SPRG7 are accessible in a read-only fashion by user-level software. e200 does not allow user mode access to the SPRG3 register (defined as implementation dependent by Book E). MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-8 Freescale Semiconductor...
Page 252 — Interrupt Vector Prefix Register (IVPR). This register together with hardwired offsets which replace the IVOR0-15 registers provide the address of the interrupt handler for different classes of interrupts. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-9 Preliminary...
Page 253 — Timer Control Register (TCR). This register controls Decrementer, Fixed-Interval Timer, and Watchdog Timer options. — Timer Status Register (TSR). This register contains status on timer events and the most recent Watchdog Timer-initiated processor reset. MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-10 Freescale Semiconductor Preliminary...
Page 254: E200-Specific Special Purpose Registers
MMU Configuration Register (MMUCFG) is a read-only register that allows software to query the configuration of the MMU. • Memory Management Registers — MMU Assist (MAS0-MAS4, MAS6) registers. These registers provide the interface to the e200 core from the Memory Management Unit. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-11 Preliminary...
Page 255 Note that it is not guaranteed that the implementation of e200 core-specific registers is consistent among Power Architecture processors, although other processors may implement similar or identical registers. All e200 SPR definitions are compliant with the Freescale EIS specification definitions. MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-12 Freescale Semiconductor...
Page 256: E200Z1 Core Complex Features Not Supported On The Mpc5510
Core (Z1) 10.3.3 e200z1 Core Complex Features Not Supported on the MPC5510 The MPC5510 implements a subset of the e200z1 core complex features. The e200z1 core complex features that are not supported in the MPC5510 are described in Table 10-2.
Page 257 TLB entries. MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-14 Freescale Semiconductor...
Page 258 256 Mbyte EA[0:3] =? EPN[0:3] 0b1010 1 Gbyte EA[0:1] =? EPN[0:1] 0b1011 4Gbyte (none) On a TLB hit, the generation of the physical address occurs as shown in Figure 10-6. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-15 Preliminary...
Page 259 SW—Supervisor write permission. Allows store instructions to access the page while in supervisor mode (MSR[PR=0]). • SX—Supervisor execute permission. Allows instruction fetches to access the page and instructions to be executed from the page while in supervisor mode (MSR[PR=0]). MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-16 Freescale Semiconductor Preliminary...
Page 260: Translation Lookaside Buffer
A hit to multiple TLB entries is considered to be a programming error. If this occurs, the TLB generates an invalid address and TLB entries may be corrupted (an exception will not be reported). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 261: Mmu Assist Registers (Mas)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 624; Read/ Write; Reset - Unaffected Figure 10-8. MMU Assist Register 0 (MAS0) MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-18 Freescale Semiconductor...
Page 262 This field is compared with the current process IDs of the effective address to be translated. A TID value of 0 defines an entry as global and matches with all process IDs. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-19...
Page 263 Figure 10-10. MMU Assist Register 2 (MAS2) Table 10-7. MAS2 - EPN and Page Attributes Name Comments, or Function when Set 0:19 Effective page number [0:19] [32:51] 20:25 — Reserved [52:57] MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-20 Freescale Semiconductor Preliminary...
Page 264 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 627; Read/ Write; Reset - Unaffected Figure 10-11. MMU Assist Register 3 (MAS3) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-21...
Page 265 01 - Reserved, do not use 10 - Reserved, do not use 11=TIDZ (8’h00)) (Use all zeros, the globally shared value) 16:19 — Reserved [48:51] 20:23 TSIZED Default TSIZE value [52:55] MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-22 Freescale Semiconductor Preliminary...
Page 266: Interrupt Types
These bits are not implemented, will be read as zero, and writes are ignored. 10.5 Interrupt Types The interrupts implemented on the MPC5510 and the exception conditions that cause them are listed in Table 10-11. MPC5510 Microcontroller Family Reference Manual, Rev. 1...
Page 267 Data translation lookup did not match a valid entry in the TLB Instruction TLB IVOR 14 Instruction translation lookup did not match a valid entry in the TLB Error MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-24 Freescale Semiconductor Preliminary...
Page 268: Bus Interface Unit (Biu)
Single-beat and misaligned transfers are supported for read and write cycles. Incrementing burst transfers are supported for instruction prefetch operations. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 10-25 Preliminary...
Page 269 Core (Z1) MPC5510 Microcontroller Family Reference Manual, Rev. 1 10-26 Freescale Semiconductor Preliminary...
Page 270: Introduction
Supports instruction and data access via a unified 32-bit Instruction/Data BIU (e200z0 only). • Load/store unit — 1 cycle load latency — Fully pipelined — Big-endian support only — Misaligned access support MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 11-1 Preliminary...
Page 271: Microarchitecture Summary
— Power saving modes: doze, nap, sleep, and wait — Dynamic power management of execution units NOTE The MPC5510 does not use the core’s HID0[DOZE,NAP,SLEEP] bits to enter/exit low-power modes. Entry to and exit from low-power modes is managed by the CRP module.
Page 272: Instruction Unit Features
Branch unit with dedicated branch address adder supporting single cycle of execution of certain branches, two cycles for all others 11.2.2 Integer Unit Features The e200 integer unit supports single cycle execution of most integer instructions: MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 11-3 Preliminary...
Page 273: Load/Store Unit Features
The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 11-4 Freescale Semiconductor...
Page 274 E numbering scheme of 32:63, thus register bit numbers for some registers in Book E are 32 higher. Where appropriate, the Book E defined bit numbers are shown in parentheses. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 11-5 Preliminary...
Page 275 1 - These e200-specific registers may not be supported by other Power Architecture processors 2 - Optional registers defined by the Power Architecture Book E Figure 11-2. e200z0 Supervisor Mode Programmer’s Model MPC5510 Microcontroller Family Reference Manual, Rev. 1 11-6 Freescale Semiconductor Preliminary...
Page 276: Power Architecture Book E Registers
“Condition Register (CR),” in Chapter 3, “Branch and Condition Register Operations, Power Architecture Book E Specification. The remaining user-level registers are SPRs. Note that the Power Architecture Book E provides the instructions for accessing SPRs. mtspr mfspr MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 11-7 Preliminary...
Page 277 It is used by the Nexus2 module for Ownership Trace message generation. Although the Power Architecture Book E allows for multiple PIDs, e200z0 implements only one. • Interrupt Registers MPC5510 Microcontroller Family Reference Manual, Rev. 1 11-8 Freescale Semiconductor Preliminary...
Page 278: E200-Specific Special Purpose Registers
The L1 Cache Configuration register (L1CFG0). This read-only register allows software to query the configuration of the L1 Cache. For the e200z0, this register returns all zeros indicating no cache is present. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 11-9...
Page 279 Note that it is not guaranteed that the implementation of e200 core-specific registers is consistent among Power Architecture processors, although other processors may implement similar or identical registers. All e200 SPR definitions are compliant with the Freescale EIS specification definitions. MPC5510 Microcontroller Family Reference Manual, Rev. 1 11-10 Freescale Semiconductor...
Page 280: E200Z0 Core Complex Features Not Supported On The Mpc5510
Debug registers can be accessed only by external tools via the Nexus port. 11.4 Interrupt Types the interrupts implemented on the MPC5510 and the exception conditions that cause them are listed in Table 11-3. Table 11-3. Exceptions and Conditions Interrupt Vector...
Page 281: Bus Interface Unit (Biu)
The memory interface supports read and write transfers of 8, 16, 24, and 32 bits, supports misaligned transfers, and operates in a pipelined fashion. Single-beat and misaligned transfers are supported for read and write cycles. Incrementing burst transfers are supported for instruction prefetch operations. MPC5510 Microcontroller Family Reference Manual, Rev. 1 11-12 Freescale Semiconductor Preliminary...
Page 282: Introduction
(TCD) for the channels. This implementation minimizes the overall block size. 12.1.1 Block Diagram A simplified block diagram of the eDMA illustrates the functionality and interdependence of major blocks (see Figure 12-1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-1 Preliminary...
Page 283: Features
— Initiation via a channel-to-channel linking mechanism for continuous transfers — Peripheral-paced hardware requests (one per channel) All three methods require one activation per execution of the minor loop • Support for fixed-priority and round-robin channel arbitration MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-2 Freescale Semiconductor Preliminary...
Page 284: Modes Of Operation
Some registers are implemented as two 32-bit registers, and include H and L suffixes, signaling the high and low portions of the control function. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-3 Preliminary...
Page 285 EDMA_CPR8 — eDMA channel 8 priority register — 12.3.2.15/12-18 0x0109 EDMA_CPR9 — eDMA channel 9 priority register — 12.3.2.15/12-18 0x010A EDMA_CPR10 — eDMA channel 10 priority register — 12.3.2.15/12-18 MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-4 Freescale Semiconductor Preliminary...
Page 286: Register Descriptions
Table 12-2. eDMA 32-bit Memory Map—Graphical View Address Register 0xFFF4_4000 eDMA Control Register (EDMA_CR) 0xFFF4_4004 eDMA Error Status (EDMA_ESR) 0xFFF4_4008 Reserved 0xFFF4_400C Reserved eDMA Enable Request Low (EDMA_ERQRL, channels 15-00) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-5 Preliminary...
Page 287 0xFFF4_410C eDMA Channel 12 eDMA Channel 13 eDMA Channel 14 eDMA Channel 15 Priority Priority Priority Priority (EDMA_CPR12) (EDMA_CPR13) (EDMA_CPR14) (EDMA_CPR15) 0xFFF4_4110 Reserved 0xFFF4_5000 – TCD00-TCD15 0xFFF4_51FC 0xFFF4_5200 Reserved MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-6 Freescale Semiconductor Preliminary...
Page 288: Register Descriptions
1 The assertion of the system debug control input causes the eDMA to stall the start of a new channel. Executing channels are allowed to complete. Channel execution will resume when either the system debug control input is negated or the EDBG bit is cleared. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-7...
Page 289: Interrupt Requests
A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel will execute and terminate with the same error condition. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-8 Freescale Semiconductor...
Page 290 Destination Offset Error. 0 No destination offset configuration error. 1 The last recorded error was a configuration error detected in the TCD.DOFF field, indicating TCD.DOFF is inconsistent with TCD.DSIZE. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-9 Preliminary...
Page 291 The state of the eDMA enable request flag does not affect a channel service request made through software or a linked channel request. Offset: EDMA_BASE + 0x000E Access: User read/write R ERQ Reset Figure 12-4. eDMA Enable Request Low Register (EDMA_ERQRL) MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-10 Freescale Semiconductor Preliminary...
Page 292 EDMA_ERQRL to enable the eDMA request for a given channel. The data value on a register write causes the corresponding bit in the EDMA_ERQRL to be set. Setting bit 1 (SERQ[0]) provides a global set MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 293 EDMA_ERQRL to be zeroed, disabling all eDMA request inputs. Reads of this register return all zeroes. Offset: EDMA_BASE + 0x0019 Access: User write only CERQ[0:6] Reset Figure 12-7. eDMA Clear Enable Request Register (EDMA_CERQR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-12 Freescale Semiconductor Preliminary...
Page 294 EDMA_EEIRL to be cleared. Setting bit 1 (CEEI[0]) provides a global clear function, forcing the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of this register return all zeroes. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-13...
Page 295 0 Reserved. CINT[0:6] Clear Interrupt Request. 0–15 Clear corresponding bit in EDMA_IRQRL 16–63 Reserved 64–127 Clear all bits in EDMA_IRQRL Note: Bits 2 and 3(CIRQR[1:2]) are not used. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-14 Freescale Semiconductor Preliminary...
Page 296 Setting bit 1 (SSB[0]) provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes. Offset: EDMA_BASE + 0x001E Access: User write only SSB[0:6] Reset Figure 12-12. eDMA Set START Bit Register (EDMA_SSBR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-15 Preliminary...
Page 297 Typically, a write to the EDMA_CIRQR in the interrupt service routine is used for this purpose. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-16 Freescale Semiconductor...
Page 298 EDMA_ERL, a 1 in any bit position clears the corresponding channel’s error status. A 0 in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CER is provided so the error indicator for a single channel can be cleared. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-17...
Page 299 The reset value for the channel priority field, CHPRI[0–3], is equal to the corresponding channel number for each priority register; that is, EDMA_CPRI0[CHPRI] = 0b0000 and EDMA_CPR15[CHPRI] = 0b1111. Figure 12-16. eDMA Channel n Priority Register (EDMA_CPRn) MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-18 Freescale Semiconductor Preliminary...
Page 300 Last destination address adjustment / scatter-gather address (dlast_sga) 0x1000+(32 x n)+0x001c Beginning major iteration count (biter) Channel control/status Figure 12-17 Table 12-19 define the fields of the TCDn structure. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-19 Preliminary...
Page 301 For this circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-20 Freescale Semiconductor Preliminary...
Page 302 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. Note: This bit must be equal to the BITER.E_LINK bit otherwise a configuration error will be reported. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-21 Preliminary...
Page 303 Note: When the TCD is first loaded by software, this field must be set equal to the corresponding CITER field, otherwise a configuration error will be reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-22 Freescale Semiconductor...
Page 304 Channel active. This flag signals the channel is currently in execution. It is set when 0x1C [25] channel service begins, and is cleared by the DMA engine as the inner minor loop completes or if any error condition is detected. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-23 Preliminary...
Page 305: Functional Description
1 The channel is explicitly started via a software initiated service request. 12.4 Functional Description This section provides an overview of the microarchitecture and functional operation of the eDMA block. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-24 Freescale Semiconductor Preliminary...
Page 306 Transfer size is defined as: if (SSIZE < DSIZE) transfer size = destination transfer size (# of bytes) else transfer size = source transfer size (# of bytes) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-25 Preliminary...
Page 307: Edma Basic Data Flow
DMA engine address path channel{x,y} registers. The TCD memory is organized 64-bits in width to minimize the time needed to fetch the activated channel’s descriptor and load it into the eDMA engine address path channel{x,y} registers. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-26 Freescale Semiconductor...
Page 308 This source read/destination write processing continues until the inner minor byte count has been transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 309 TCD from memory using the scatter-gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 12-20. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-28 Freescale Semiconductor Preliminary...
Page 310: Initialization / Application Information
After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The DMA engine will read the entire TCD, including the MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 311 DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (biter). MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-30 Freescale Semiconductor...
Page 312: Dma Programming Errors
For all error types other than channel-priority errors, the channel number causing the error is recorded in the EDMA_ESR. If the error source is not removed before the next activation of the problem channel, the error will be detected and recorded again. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-31...
Page 313: Dma Request Assignments
Round-Robin Channel Arbitration In this mode, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the assigned channel priority levels. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-32 Freescale Semiconductor...
Page 314: Dma Transfer
→ first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004) → second iteration of the minor loop e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b) f) write_word(0x2008) → third iteration of the minor loop MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-33 Preliminary...
Page 315 5. The source to destination transfers are executed as follows: a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word(0x2000) → first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004) → second iteration of the minor loop MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-34 Freescale Semiconductor Preliminary...
Page 316 (0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the offset is set to 4 bytes and the mod field is set to 4, allowing for a 2 byte (16-byte) size queue. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-35...
Page 317: Tcd Status
4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (channel has completed the major loop and is idle). For both activation types, the major loop complete status is explicitly indicated via the TCD.DONE bit. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-36 Freescale Semiconductor...
Page 318: Channel Linking
TCD.MAJOR.E_LINK = 1 TCD.MAJOR.LINKCH = 0x7 will execute as: 1. Minor loop done → set channel 12 TCD.START bit 2. Minor loop done → set channel 12 TCD.START bit MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-37 Preliminary...
Page 319: Dynamic Programming
TCD.MAJOR.E_LINK bit at the same time the eDMA engine is retiring the channel. The TCD.MAJOR.E_LINK would be set in the programmer’s model, but it would be unclear whether the actual link was made before the channel retired. MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-38 Freescale Semiconductor...
Page 320 The user must clear the TCD.DONE bit before writing the TCD.MAJOR.E_LINK or TCD.E_SG bits. The TCD.DONE bit is cleared automatically by the eDMA engine after a channel begins execution. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 12-39 Preliminary...
Page 321 Enhanced Direct Memory Access (eDMA) MPC5510 Microcontroller Family Reference Manual, Rev. 1 12-40 Freescale Semiconductor Preliminary...
Page 322 DMA Channel #9 DMA Channel #10 DMA Channel #11 DMA Channel #12 DMA Channel #13 DMA Channel #14 Peripheral Source #55 DMA Channel #15 Figure 13-1. DMA_MUX Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 13-1 Preliminary...
Page 323: Memory Map And Registers
All registers are accessible via 8-bit, 16-bit, or 32-bit accesses. However, 16-bit accesses must be aligned to 16-bit boundaries and 32-bit accesses must be aligned to 32-bit boundaries. As an example, MPC5510 Microcontroller Family Reference Manual, Rev. 1 13-2 Freescale Semiconductor...
Page 324 Each of the 16 DMA channels can be independently enabled/disabled and associated with one of the 64 DMA sources in the system. Offset: DMA_MUX_BASE + n Access: User read/write ENBL TRIG SOURCE Reset Figure 13-2. Channel Configuration Registers (CHCONFIGn) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 13-3 Preliminary...
Page 325 LIN receive data ready DMA requests SCI_C_COMBTX 0x05 SCI_C.SCISR1[TDRE] || SCI_C combined DMA request of the transmit SCI_C.SCISR1[TC] || data register empty, transmit complete, and LIN SCI_C.LINSTAT1[TXRDY] transmit data ready DMA requests MPC5510 Microcontroller Family Reference Manual, Rev. 1 13-4 Freescale Semiconductor Preliminary...
Page 326 DSPI_B receive FIFO drain flag DSPI_C_SR_TFFF 0x15 DSPI_C.DSPI_SR[TFFF] DSPI_C transmit FIFO fill flag DSPI_C_SR_RFDF 0x16 DSPI_C.DSPI_SR[RFDF] DSPI_C receive FIFO drain flag DSPI_D_SR_TFFF 0x17 DSPI_D.DSPI_SR[TFFF] DSPI_D transmit FIFO fill flag MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 13-5 Preliminary...
Page 327 FIFO 0 fill flag eQADC_FISR1_RFDF1 0x33 eQADC.eQADC_FISR1[RFDF1] eQADC receive FIFO 1 drain flag eQADC_FISR1_CFFF1 0x34 eQADC.eQADC_FISR1[CFFF1] eQADC command FIFO 1 fill flag MLB_DMA_REQ 0x35 MLB.MSR[MDATRQS] MLB Data Request Reserved 0x36 Reserved Reserved MPC5510 Microcontroller Family Reference Manual, Rev. 1 13-6 Freescale Semiconductor Preliminary...
Page 328 Because of the dynamic nature of the system (i.e. DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 13-7...
Page 329 After the DMA request has been serviced, the peripheral negates its request, effectively resetting the gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means that MPC5510 Microcontroller Family Reference Manual, Rev. 1 13-8...
Page 330 Chapter 28, “Periodic Interrupt Timer and Real Time Interrupt (PIT_RTI).” 13.4.2 DMA Channels 8–15 Channels 8–15 of the DMA_MUX provide the normal routing functionality as described in Section 13.1.3, “Modes of Operation.” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 13-9 Preliminary...
Page 331: Always Enabled Dma Sources
In cases where software should initiate the start of a DMA transfer, an always enabled DMA source can be used to provide maximum flexibility. When activating a DMA channel via software, subsequent MPC5510 Microcontroller Family Reference Manual, Rev. 1 13-10...
Page 332: Initialization/Application Information
2. Configure channel 2 in the DMA, including enabling the channel. 3. Configure timer 3 in the periodic interrupt timer (PIT) for the desired trigger interval. 4. Write 0xC5 to CHCONFIG2 (base address + 0x02). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 13-11...
Page 333 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); MPC5510 Microcontroller Family Reference Manual, Rev. 1 13-12 Freescale Semiconductor Preliminary...
Page 334 *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 13-13...
Page 335: Interrupts
*CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include “registers.h” *CHCONFIG8 = 0x00; *CHCONFIG8 = 0x87; 13.6 Interrupts The DMA channel mux does not generate interrupts. MPC5510 Microcontroller Family Reference Manual, Rev. 1 13-14 Freescale Semiconductor Preliminary...
Page 336: Terminology
A bus transaction consists of an address transfer (address phase) and one or more data transfer(s) (data phase). 14.1.2 Block Diagram A simplified block diagram of the AIPS-lite illustrates the functionality and interdependence of major blocks (see Figure 14-1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 14-1 Preliminary...
Page 337 The AIPS-lite does not contain any user-programmable registers. 14.4 Functional Description The AIPS-lite serves as an interface between an AHB 2.v6 system bus and the peripheral interface bus. It functions as a protocol translator. MPC5510 Microcontroller Family Reference Manual, Rev. 1 14-2 Freescale Semiconductor Preliminary...
Page 338: Read Cycles
Two-clock write accesses are possible with the AIPS-Lite when the reference size is 32 bits or smaller. This module does not support any type of misaligned write access crossing a 32-bit boundary. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 339 Peripheral Bridge (AIPS-lite) MPC5510 Microcontroller Family Reference Manual, Rev. 1 14-4 Freescale Semiconductor Preliminary...
Page 340: Master Ports
The XBAR can be configured to use fixed priority arbitration by clearing the MCM_MUDCR[PRI] bit. Table 15-1 lists the master IDs for each of the possible bus masters on MPC5510. Table 15-1. Master IDs Master Master ID XBAR port...
Page 341 — Nexus 2+ pretending to be Z0 core (master ID = 9) — Nexus 2+ pretending to be Z1 core (master ID = 8) • Slaves — SRAM (XBAR s3) MPC5510 Microcontroller Family Reference Manual, Rev. 1 15-2 Freescale Semiconductor Preliminary...
Page 342 In this context, the transfer boundary is defined as the completion of any “single” transfer, the completion of each transfer within an undefined-length burst, the MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 343 When a slave bus is being idled by the XBAR, it is parked on a specific master port. On the MPC5510, the shared flash/AIPS/EBI slave port is parked on the e200z0, and the SRAM slave port is parked on the last master to access it.
Page 344 The ability to enable the high-priority request from the processors is programmable. This feature is enabled via the assertion of the appropriate HID1 control bits in the e200 core. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 15-5...
Page 345: Slave Port State Machine
If no master is currently making a request to the slave port then the slave port is parked on a given master port. When a slave port is parked on a master and that master accesses the slave port, the master does not MPC5510 Microcontroller Family Reference Manual, Rev. 1 15-6...
Page 346 Figure 15-3 illustrates parking on the last master. On MPC5510, the s0 port is “parked on the e200z0” and the s3 port is “parked on last”. This configuration is hardwired and cannot be changed by software. hclk...
Page 347: Dma Requests
There are no DMA requests associated with the XBAR. 15.6 Interrupt Requests There are no interrupt requests associated with the XBAR. 1. Hardwired and not user changeable configuration for slave port s3. MPC5510 Microcontroller Family Reference Manual, Rev. 1 15-8 Freescale Semiconductor Preliminary...
Page 348: Introduction
Software watchdog timer (SWT) with programmable interrupt response — The default state after reset of the SWT is enabled — The SWT count can be optionally held when system debug is enabled MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 16-1...
Page 349: Memory Map And Registers
16.2.2.5.5/16-12 0x0057 FEAT—Flash ECC Attributes 16.2.2.5.6/16-13 0x0058 Reserved 0x005C FEDR—Flash ECC Data 16.2.2.5.7/16-14 0x0060 REAR—RAM ECC Address 16.2.2.5.8/16-14 0x0066 REMR—RAM ECC Master 0x0U 16.2.2.5.9/16-15 0x0067 REAT—RAM ECC Attributes 16.2.2.5.10/16-15 MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-2 Freescale Semiconductor Preliminary...
Page 350 Flash ECC Data High (FEDRH) 0x005C Flash ECC Data Low (FEDRL) 0x0060 RAM ECC Address (REAR) RAM ECC Master RAM ECC Attributes 0x0064 Reserved (REMR) (REAT) 0x0068 Reserved 0x006C RAM ECC Data (REDR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 16-3 Preliminary...
Page 351: Register Descriptions
(either as the initial or secondary response), the MCM generates a watchdog timer reset output signal, which is driven to the SIU and will cause a system reset. The watchdog timer logic also sends an interrupt request to the device’s interrupt controller. MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-4 Freescale Semiconductor...
Page 352 Note: Reserved bit 6 must never be set. SWRWH Software Watchdog Run While Halted. 0 SWT stops counting if the processor core is halted. 1 SWT continues to count even while the processor core is halted. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 16-5 Preliminary...
Page 353 Figure 16-2 illustrates the SWTSR. Offset: MCM_BASE_ADDR + 0x001B Access: User read/write SWSR Reset – – – – – – – – Figure 16-2. Software Watchdog Timer Service Register (SWTSR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-6 Freescale Semiconductor Preliminary...
Page 354 16.2.2.4 Miscellaneous User-Defined Control Register (MUDCR) The MUDCR provides a program-visible register. On MPC5510, one bit is implemented. The PRI bit determines whether the AXBS-lite uses a fixed or round robin priority arbitration scheme for masters requesting access to AXBS-lite slave ports. See...
Page 355 MCM captures specific information (memory address, attributes and data, bus master number, etc.) that may be useful for subsequent failure analysis. Figure 16-5 Table 16-6 for the ECC configuration register definition. MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-8 Freescale Semiconductor Preliminary...
Page 356 4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request. Figure 16-6 Table 16-7 for the ECC status register definition. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 16-9 Preliminary...
Page 357 Figure 16-7 Table 16-8 for the ECC error generation register definition. Offset: MCM_BASE_ADDR + 0x004A Access: User read/write FRCNCI FR1NCI ERRBIT Reset Figure 16-7. ECC Error Generation (EEGR) Register MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-10 Freescale Semiconductor Preliminary...
Page 358 The only allowable values for the 2 control bit enables {FRCNCI, FR1NCI} are {0,0}, {1,0} and {0,1}. All other values result in undefined behavior. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 16-11...
Page 359 ECC master number register definition. Offset: MCM_BASE_ADDR + 0x0056 Access: User read only FEMR Reset – – – – Figure 16-9. Flash ECC Master Number (FEMR) Register MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-12 Freescale Semiconductor Preliminary...
Page 360 010 32-bit access 011 64-bit access 1xx Reserved Protection Cache: 0xxx Non-cacheable 1xxx Cacheable Buffer: x0xx Non-bufferable x1xx Bufferable Mode: xx0x User mode xx1x Supervisor mode Type: xxx0 I-Fetch xxx1 Data MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 16-13 Preliminary...
Page 361 REAT, and REDR registers and also the appropriate flag (RNCE) in the ECC status register to be asserted. This register is read-only; any attempted write is ignored. See Figure 16-12 Table 16-13 for the RAM ECC address register definition. MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-14 Freescale Semiconductor Preliminary...
Page 362 The REAT is an 8-bit register for capturing the AXBS bus master attributes of the last, properly-enabled ECC event in the RAM memory. Depending on the state of the ECC configuration register, an ECC event MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 363 The data captured on a multi-bit non-correctable ECC error is undefined. This register is read-only; any attempted write is ignored. See Figure 16-15 Table 16-16 for the RAM ECC data register definition. MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-16 Freescale Semiconductor Preliminary...
Page 364: Functional Description
Reference Chapter 15, “Crossbar Switch (XBAR),” for information on priority elevation and the Z1 and Z0 Core Reference Manual for information on the use of the interrupts. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 16-17 Preliminary...
Page 365 Miscellaneous Control Module (MCM) MPC5510 Microcontroller Family Reference Manual, Rev. 1 16-18 Freescale Semiconductor Preliminary...
Page 366 A simplified block diagram illustrates how the MPU block is connected to the three AXBS-lite slave ports, one of them being the shared slave port splitter (see Figure 17-1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-1 Preliminary...
Page 367 — Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only MPC5510 Microcontroller Family Reference Manual, Rev. 1 17-2 Freescale Semiconductor...
Page 368 MPU_EAR0 — MPU error address register, slave port 0 — 17.3.2.2/17-6 0x0014 MPU_EDR0 — MPU error detail register, slave port 0 — 17.3.2.3/17-7 0x0018 MPU_EAR1 — MPU error address register, slave port 1 — 17.3.2.2/17-6 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-3 Preliminary...
Page 369 MPU_RGDAAC7 — MPU RGD alternate access control 7 — 17.3.2.5/17-12 0x0820 MPU_RGDAAC8 — MPU RGD alternate access control 8 — 17.3.2.5/17-12 0x0824 MPU_RGDAAC9 — MPU RGD alternate access control 9 — 17.3.2.5/17-12 MPC5510 Microcontroller Family Reference Manual, Rev. 1 17-4 Freescale Semiconductor Preliminary...
Page 370 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MPERR NRGD Reset 0 Figure 17-2. MPU Control/Error Status Register (MPU_CESR) Each MPERR bit can be cleared by writing a one to the bit location. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-5 Preliminary...
Page 371 Hardware Revision Level. This 4-bit read-only field specifies the MPU’s hardware and definition revision level. It can be read by software to determine the functional definition of the module. This field reads as 0 on MPC5510. Number of MPU/Slave Ports. This 4-bit read-only field specifies the number of MPU/slave ports [1–8] connected to the MPU.
Page 372 Each 128-bit (16 byte) region descriptor specifies a given memory space and the access attributes associated with that space. The descriptor definition is fundamental to the operation of the MPU. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-7...
Page 373 For these fields, the bus master number refers to the logical master number defined as the AHB signal. hmaster[3:0] MPC5510 Microcontroller Family Reference Manual, Rev. 1 17-8 Freescale Semiconductor Preliminary...
Page 374 Bus Master ID 4 Read Enable. If set, this flag allows bus master ID 4 to perform read operations. If cleared, any attempted read by bus master ID 4 terminates with an access error and the read is not performed. Note: Bus Master 4 (EBI) is available for Factory Test only. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-9...
Page 375 Bus Master ID 0 Process Identifier Enable. If set, this flag specifies that the process identifier and mask defined in MPU_RGDn.Word3 are to be included in the region hit evaluation. If cleared, the region hit evaluation does not include the process identifier. MPC5510 Microcontroller Family Reference Manual, Rev. 1 17-10 Freescale Semiconductor...
Page 376 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PIDMASK Reset – – – – – – – – – – – – – – – – Figure 17-8. MPU Region Descriptor, Word 3 Register (MPU_RGDn.Word3) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-11 Preliminary...
Page 377 Bus Master ID 4 Read Enable. If set, this flag allows bus master ID 4 to perform read operations. If cleared, any attempted read by bus master ID 4 terminates with an access error and the read is not performed. MPC5510 Microcontroller Family Reference Manual, Rev. 1 17-12...
Page 378 Bus Master 0 Process Identifier Enable. If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not include the process identifier. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-13...
Page 379: Access Evaluation Macro
Figure 17-10. MPU Access Evaluation Macro Figure 17-10 is not a schematic of the actual access evaluation macro, but a generalized block diagram showing the major functions included in this logic block. MPC5510 Microcontroller Family Reference Manual, Rev. 1 17-14 Freescale Semiconductor Preliminary...
Page 380 — — no, access is allowed data write — — — yes, no w permission data write — — — no, access is allowed MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-15 Preliminary...
Page 381: Putting It All Together And Ahb Error Terminations
This state also minimizes the power dissipation of the MPU. The power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when MPU_CESR[VLD] = 0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 17-16 Freescale Semiconductor...
Page 382: Application Information
In the overlapping memory space, the protection rights of the corresponding region descriptors are logically summed together (the boolean OR operator). In the following example of a dual-core system, there are four MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 17-17...
Page 383 (RGD7) accessible to both processors and the traditional eDMA master. This example is intended to show one possible application of the capabilities of the memory protection unit in a typical system. MPC5510 Microcontroller Family Reference Manual, Rev. 1 17-18 Freescale Semiconductor Preliminary...
Page 384 In the diagram, the register blocks named gate0, gate1, ..., gate 15 include the finite state machines implementing the semaphore gates plus the interrupt notification logic. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 18-1...
Page 385 — Each hardware gate appears as a three-state, 2-bit state machine, with all 16 gates mapped as an array of bytes – Three-state implementation if gate = 0b00, then state = unlocked MPC5510 Microcontroller Family Reference Manual, Rev. 1 18-2 Freescale Semiconductor Preliminary...
Page 386 SEMA4_Gate02 — Semaphores gate 2 0x00 18.3.2.1/18-4 0x0003 SEMA4_Gate03 — Semaphores gate 3 0x00 18.3.2.1/18-4 0x0004 SEMA4_Gate04 — Semaphores gate 4 0x00 18.3.2.1/18-4 0x0005 SEMA4_Gate05 — Semaphores gate 5 0x00 18.3.2.1/18-4 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 18-3 Preliminary...
Page 387 The hardware uses the bus master number in conjunction with the data patterns to validate all attempted write operations. Only processor bus masters can modify the gate registers. After it is locked, a gate must be opened (unlocked) by the locking processor core. MPC5510 Microcontroller Family Reference Manual, Rev. 1 18-4 Freescale Semiconductor...
Page 388 SEMA4_BASE + 0x0048 (SEMA4_CP1INE) INE0 INE1 INE2 INE3 INE4 INE5 INE6 INE7 INE8 INE9 INE10 INE11 INE12 INE13 INE14 INE15 Reset Figure 18-3. Semaphores Processor n IRQ Notification Enable (SEMA4_CP{0,1}INE) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 18-5 Preliminary...
Page 389 (or all the gates) to be initialized by following a specific dual-write access pattern. Using a technique similar to that required for the servicing of a software MPC5510 Microcontroller Family Reference Manual, Rev. 1 18-6...
Page 390 (SEMA4_RSTGT[RSTGTN]). Reads of the SEMA4_RSTGT register do not affect the secure reset finite state machine in any manner. Offset: SEMA4_BASE + 0x0100 (SEMA4_RSTGT) Access: Read/write RSTGSM RSTGMS RSTGTN RSTGDP Reset Figure 18-5. Semaphores (Secure) Reset Gate n (SEMA4_RSTGT) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 18-7 Preliminary...
Page 391 1. A processor performs a 16-bit write to the SEMA4_RSTNTF memory location. The most significant byte (SEMA4_RSTNTF[RSTNDP]) must be 0x47; the least significant byte is a don’t_care for this reference. MPC5510 Microcontroller Family Reference Manual, Rev. 1 18-8 Freescale Semiconductor...
Page 392 The reset function requires that the two consecutive writes to this register be initiated by the same bus master to succeed. This field is updated each time a write to this register occurs. Master Master ID e200z1 e200z0 eDMA FlexRay MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 18-9 Preliminary...
Page 393 If the CPU and bus provide an atomic swap operation, programmers can create locks with the proper semantics. The adjective atomic is key, MPC5510 Microcontroller Family Reference Manual, Rev. 1 18-10...
Page 394: Semaphore Usage
3. The Z1 software interrupt ISR reads the data sent to the Z0, not the data sent from the Z0, and performs an incorrect operation. — Semaphores do not prevent this situation from occurring. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 18-11...
Page 395: Initialization Information
#define CP2_LOCK void gateLock (n) /* gate number to lock */ current_value; locked_value; i = processor_number(); /* obtain logical CPU number */ if (i == 0) locked_value = CP0_LOCK; MPC5510 Microcontroller Family Reference Manual, Rev. 1 18-12 Freescale Semiconductor Preliminary...
Page 396: Dma Requests
DMA Requests There are no DMA requests associated with the IPS_Semaphore block. 18.8 Interrupt Requests The semaphore interrupt requests are connected to the interrupt controller as described in Table 8-2. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 18-13 Preliminary...
Page 397 Semaphores MPC5510 Microcontroller Family Reference Manual, Rev. 1 18-14 Freescale Semiconductor Preliminary...
Page 398: Introduction
Test access port (TAP) reset controller 1-bit bypass register 32-bit device identification register Boundary scan register 5-bit TAP instruction decoder 5-bit TAP instruction register Figure 19-1. JTAGC Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 19-1 Preliminary...
Page 399: Features
TMS and JCOMP are not shown for clarity. NPC TAP also not shown for clarity. e200z0 OnCE TAP Figure 19-2. JTAG/Nexus Daisy Chain of the MPC5510 e200z1 and e200z0 Cores 19.1.2 Features The JTAGC is compliant with the IEEE 1149.1-2001 standard and has these major features: •...
Page 400 When the access instruction for an auxiliary TAP is loaded, control of the JTAG pins is transferred to the selected TAP controller. Any data input via TDI and TMS is passed to the selected TAP controller, and any MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 401: External Signal Description
BYPASS, CLAMP, HIGHZ, or reserve instructions are active. After entry into the capture-DR state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 19-4 Freescale Semiconductor...
Page 402: Device Identification Register
Design Center. Indicates the Freescale design center. For the MPC5510 family this value is 0x20. Part Identification Number. Contains the part number of the device. For the MPC5510 family, this value is 0x116. Manufacturer Identity Code. Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID for Freescale, 0xE.
Page 403: Ieee 1149.1-2001 (Jtag) Test Access Port
TMS signal sampled on the rising edge of the TCK signal. As Figure 19-6 shows, holding TMS at logic 1 while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the test-logic-reset state. MPC5510 Microcontroller Family Reference Manual, Rev. 1 19-6 Freescale Semiconductor Preliminary...
Page 404 NOTE: The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK. Figure 19-6. IEEE 1149.1-2001 TAP Controller Finite State Machine MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 19-7...
Page 405: Jtagc Instructions
Grants the Nexus e200z0 core interface ownership of the TAP ACCESS_AUX_TAP_MULTI 11100 Daisy chaining the e200z1 and e200z0 cores—allows instructions to be clocked into both the e200z0 and e200z1 serially. BYPASS 11111 Selects bypass register for data operations MPC5510 Microcontroller Family Reference Manual, Rev. 1 19-8 Freescale Semiconductor Preliminary...
Page 406 SAMPLE/PRELOAD instruction before the selection of EXTEST. EXTEST asserts the internal system reset for the MCU to force a predictable internal state while performing external boundary scan operations. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 19-9...
Page 407: Boundary Scan
TDI and TDO when the EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded. The shift-register chain contains a serial input and serial output, as well as clock and control signals. MPC5510 Microcontroller Family Reference Manual, Rev. 1 19-10 Freescale Semiconductor...
Page 408: E200Z0 And E200Z1 Once Controllers
Figure 19-7. e200z0 OnCE Block Diagram 19.5.2 e200z0 OnCE Controller Functional Description The functional description for the e200z0 OnCE controller is the same as for the JTAGC, with the differences described below. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 19-11 Preliminary...
Page 409: E200Z0 Once Controller Register Descriptions
GO command at the same time for example. 19.5.3 e200z0 OnCE Controller Register Descriptions Most e200z0 OnCE debug registers are fully documented in the e200z0 Reference Manual. The MPC5510 implements a new shared nexus control register (SNC) which is defined in Section 19.5.3.2, “OnCE Shared Nexus Control Register (SNC).”...
Page 410 ID is used during Nexus2+ DMA access, and if the Nexus EVTI debug request is used as a debug request to either or both cores. This register is only available on the e200z0 core. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 411: Initialization/Application Information
To initialize the JTAGC module and enable access to registers, the following sequence is required: 1. Set the JCOMP signal to logic 1, thereby enabling the JTAGC TAP controller. 2. Load the appropriate instruction for the test or action to be performed. MPC5510 Microcontroller Family Reference Manual, Rev. 1 19-14 Freescale Semiconductor...
Page 412: Introduction
(LSB=0 convention). The Nexus Development Interface (NDI) block provides real-time development support capabilities for the MPC5510 MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility.
Page 413: Block Diagram
Ownership trace snoop queue formatter e200z0 trace Watchpoint trace Arbiter information Input Control registers to trace blocks controller JCOMP Power-on Reset reset control EVTI Figure 20-1. NDI Functional Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 20-2 Freescale Semiconductor Preliminary...
Page 414: Features
Figure 20-2. NDI Implementation Block Diagram 20.2.1 Features The NDI module of the MPC5510 is compliant with Class 2 of the IEEE-ISTO 5001-2003 standard, with additional Class 3 and Class 4 features available. The following features are implemented: • Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to...
Page 415: Modes Of Operation
Nexus client in the JTAGC controller (JTAGC) block when JCOMP is asserted. The NPC transitions out of the reset state immediately following negation of power-on reset. MPC5510 Microcontroller Family Reference Manual, Rev. 1 20-4 Freescale Semiconductor...
Page 416 After the acknowledgment, the system clock input are shut off by the clock driver on the device. While the clocks are shut off, the development tool cannot access NDI registers via the JTAG port. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 20-5...
Page 417: External Signal Description
Table 20-2. Nexus Debug Interface Registers Client Select Index Register Client-Independent Registers 0bxxxx Device ID (DID) 0bxxxx Client select control (CSC) 0bxxxx Port configuration register (PCR) e200z0 Control/Status Registers 0b0000 e200z0 development control1 (DC1) MPC5510 Microcontroller Family Reference Manual, Rev. 1 20-6 Freescale Semiconductor Preliminary...
Page 418: Register Descriptions
Part Revision Number. Contains the revision number of the part. This field changes with each revision of the device or module. Design Center. Indicates the Freescale design center. This value is 0x20. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 20-7...
Page 419 Table 20-3. DID Field Descriptions (continued) Field Description Part Identification Number. Contains the part number of the device. The PIN value for the MPC5510 family is 0x0116. Manufacturer Identity Code. Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID for Freescale, 0x00E.
Page 420 Low Power Debug Enable. The LP_DBG_EN bit enables debug functionality to support entry and exit from low power sleep and stop modes. 0 Low power debug disabled. 1 Low power debug enabled. bits 14–10 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 20-9 Preliminary...
Page 421 1 Stop mode entry pending bits 7–1 Reserved. PSTAT_EN Processor Status Mode Enable. MPC5510 does not support the PSTAT mode. Setting PSTAT_EN will drive zeros to the MDO and MSEO pins. 20.4.2.3 Development Control Register 1, 2 (DC1, DC2) The development control registers are used to control the basic development features of the Nexus module.
Page 422: Debug Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reset 0 Figure 20-6. Development Control Register 2 (DC2) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 20-11...
Page 423 0 CPU not in debug mode. 1 CPU in debug mode. bits 30–28 Reserved. CPU Low-Power Mode Status. 00 Normal (run) mode. 01 CPU in halted state. 10 CPU in stopped state. 11 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 20-12 Freescale Semiconductor Preliminary...
Page 424 Word Size. 000 8-bit (byte.) 001 16-bit (halfword). 010 32-bit (word). 011 64-bit (doubleword—only in burst mode). 100–111 Reserved (default to word). MAP Select. 000 Primary memory map. 001-111 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 20-13 Preliminary...
Page 425 Figure 20-9. Read/Write Access Address Register (RWA) 20.4.2.7 Read/Write Access Data (RWD) The read/write access data register provides the data to/from system bus memory-mapped locations when initiating a read or a write access. MPC5510 Microcontroller Family Reference Manual, Rev. 1 20-14 Freescale Semiconductor Preliminary...
Page 426 100 Use watchpoint #3 (IAC4 from Nexus1). 101 Use watchpoint #4 (DAC1 from Nexus1). 110 Use watchpoint #5 (DAC2 from Nexus1). 111 Use watchpoint #6 or #7 (DCNT1 or DCNT2 from Nexus1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 20-15 Preliminary...
Page 427: Functional Description
1 (DC1) have not already been set to enable program and data trace, respectively. 20.5 Functional Description The NDI block is implemented by integrating the following blocks on the MPC5510: • Nexus e200z0 development interface (OnCE and Nexus2p sub-blocks) •...
Page 428: Configuring The Ndi For Nexus Messaging
NDI configuration options. Table 20-13. NDI Configuration Options MCKO_EN bit of the FPM bit of the JCOMP Asserted Configuration Port Configuration Register Port Configuration Register Reset Disabled MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 20-17 Preliminary...
Page 429: Switching Ownership Of Nexus2+
20.5.3 Switching Ownership of Nexus2+ On MPC5510, the Nexus2+ is shared by the e200z1 and e200z0 cores. Out of reset, the default ownership of the Nexus2+ belongs to the e200z0 core. To switch the trace between cores, without a system reset, requires a software reset of the Nexus2+ registers to clear the previously programmed values.
Page 430: Nexus Messaging
MPC5510. These values are specific to the MPC5510. The size of the SRC field in transmitted messages is 4 bits. This value is also specific to the MPC5510. The same values are used for the client select values written to the client select control register.
Page 431 Nexus Event-Out Generated Break Request On MPC5510, the Nexus2+ event-out signal has been connected to the external debug event 2 input to both cores. This allows the assertion of a Nexus event-out signal to trigger a debug request to either or both cores.
Page 432 - Set DR bit (request debug mode right - Set DR bit (request debug mode right out of reset). out of reset). Negate System Reset Figure 20-12. Nexus Event-Out Generated Break Request (5510) — Part 1 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 20-21 Preliminary...
Page 433: Nexus Reset Control
Nexus blocks. The single bit reset signal functions much like the IEEE 1149.1-2001 defined TRST signal but has a default value of disabled (JCOMP is pulled low during reset) The IEEE 1149.1-2001 defines TRST to be pulled up (enabled) by default. MPC5510 Microcontroller Family Reference Manual, Rev. 1 20-22 Freescale Semiconductor...
Page 434: Introduction
Chapter 21 Internal Static RAM (SRAM) 21.1 Introduction The MPC5510 provides 80 KB of general-purpose system SRAM, that is implemented using ten 8 KB arrays. This implementation allows a configurable number of arrays to remain powered during low-power sleep modes. 21.1.1...
Page 435: Features
Configurable number of 8 KB blocks powered during low-power sleep • Byte, halfword, and word addressable • Error correcting code (ECC) performs single bit correction, double bit detection on a 32-bit boundary MPC5510 Microcontroller Family Reference Manual, Rev. 1 21-2 Freescale Semiconductor Preliminary...
Page 436: Modes Of Operation
8 KB RAM array F 0x4000_C000–0x4000_DFFF 8 KB RAM array G 0x4000_E000–0x4000_FFFF 8 KB RAM array H 0x4001_0000–0x4001_1FFF 8 KB RAM array I 0x4000_2000–0x4001_3FFF 8 KB RAM array J MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 21-3 Preliminary...
Page 437: Register Descriptions
Previous is the SRAM access during the previous clock. Table 21-2. Wait States During SRAM Access Current Previous Wait States Read Idle Read 32-bit write 8/16-bit write 32-bit write Idle Read 32-bit write 8/16-bit write MPC5510 Microcontroller Family Reference Manual, Rev. 1 21-4 Freescale Semiconductor Preliminary...
Page 438: Reset Operation
You must initialize the ECC check bits after the device is powered on before you can use the SRAM. The write transfer must be 32 or 64 bits, on a 32-bit boundary. If not, a read/modify/write operation is generated that checks the ECC value upon the read. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 21-5...
Page 439: Example Code
// size to clear asm ("lis r13,0x4000"); // RAM base address asm ("clear_mem:"); asm ("subi r14,r14,0x20"); asm ("dcbz r14,r13"); asm ("dcbf r14,r13"); asm ("cmpwi r14,0x0"); asm ("beq continue"); asm ("b clear_mem"); MPC5510 Microcontroller Family Reference Manual, Rev. 1 21-6 Freescale Semiconductor Preliminary...
Page 440: Introduction
16 KB blocks and two 64 KB blocks. The mid and high memory will be implemented using ten 128 KB blocks. Figure 22-1 shows the segmentation for the flash on MPC5510. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 441: Block Diagram
(see Section 22.3, “External Signal Description.”) Figure 22-2. Flash System Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-2 Freescale Semiconductor Preliminary...
Page 442: Features
The other flash supplies are tied to the appropriate supply pads in the package. Refer to Table 2-1 Section 2.7, “Detailed External Signal Descriptions,” and the MPC5510 Microcontroller Family Data Sheet. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 443: Memory Map And Registers
(0x0000_0000) 0x0000_0000 Low-address space 0x0000_4000 0x0000_8000 0x0000_C000 0x0001_0000 0x0001_4000 0x0001_8000 0x0001_C000 0x0002_0000 0x0003_0000 0x0004_0000 Mid-address space 0x0006_0000 0x0008_0000 High-address space 0x000A_0000 0x000C_0000 0x000E_0000 0x0010_0000 0x0012_0000 0x0014_0000 0x0016_0000 0x0018_0000–0xF0_FFFF Reserved MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-4 Freescale Semiconductor Preliminary...
Page 444: Register Descriptions
0x0028 – 0x3FFF Reserved Some bits are read only. 22.4.2 Register Descriptions This section lists the flash registers in address order and describes the registers and their bit fields. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-5 Preliminary...
Page 445 Special Flash Sector. For MPC5510, this read-only bit field is 0b0 indicating no special flash sector size. SIZE The value of the SIZE field depends on the size of the flash module. For MPC5510, this bit field is 0b0101 indicating a 1.5 MB array size (with 1 MB in high-address space).
Page 446 PGM can be cleared by the user only when PSUS and EHV are low and DONE is high. PGM is cleared on reset. 0 Flash is not executing a program sequence 1 Flash is executing a program sequence MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-7...
Page 447 This should be avoided due to reliability implications. Aborting a high voltage operation will leave flash core addresses in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-8 Freescale Semiconductor...
Page 448 An “OR” of LML and SLL determine the final lock status. See Section 22.4.2.4, “Secondary Low-/Mid-Address Space Block Locking Register (SLL),” for more information on SLL. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-9 Preliminary...
Page 449 (assuming the corresponding shadow row bit is erased) would be locked. SLOCK is not writable unless LME is high. 0 Shadow row is available to receive program and erase pulses. 1 Shadow row is locked for program and erase. bits 12–13 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-10 Freescale Semiconductor Preliminary...
Page 450 For HBE, the password 0xB2B2_2222 must be written to HBL. 0 High address locks are disabled, and cannot be modified 1 High address locks are enabled to be written MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-11...
Page 451 Secondary Shadow Lock. An alternative method that may be used to lock the shadow row from programs and erases. SSLOCK has the same description as SLOCK in Section 22.4.2.2, “Low-/Mid-Address Space Block Locking Register.” SSLOCK is not writable unless SLE is high. bits 12–13 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-12 Freescale Semiconductor Preliminary...
Page 452 Space Block Locking Register.” 0b00 Mid-address space blocks are not selected for erase 0b01 One mid-address space block is selected for erase 0b11 Two mid-address space blocks are selected for erase MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-13 Preliminary...
Page 453 The ADR provides the first failing address in the event of ECC event error (MCR[EER] set) and the address of a failure that may have occurred in a state machine operation (MCR[PEG] cleared). ECC event MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-14...
Page 454 PFLASH2P_H7Fb. This register also has two bits (ARB and PRI) to control arbitration between the p0/p1 ports. The PFLASH configuration register for port 1 (PFCRP1) is used to specify operation of port p1 of the PFLASH2P_H7Fb MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-15 Preliminary...
Page 455 0 Port p0 is given highest fixed priority. 1 Port p1 is given highest fixed priority. Note: This bit is only available in PFCRP0. For PFCRP1, treat this bit as reserved. bits 6–10 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-16 Freescale Semiconductor Preliminary...
Page 456 Instruction Prefetch Enable. Enables or disables prefetching initiated by an instruction read access. This field is cleared by hardware reset. 0 No prefetching is triggered by an instruction read access 1 Prefetching may be triggered by any instruction read access bit 28 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-17 Preliminary...
Page 457: Functional Description
Data coherency can be an issue after a program, erase, or shadow row operations. In flash user mode, registers can be written. Array can be written to do interlock writes. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-18 Freescale Semiconductor...
Page 458: Read While Write (Rww)
Ensure the block that contains the address to be programmed is unlocked. Section 22.4.2.2, “Low-/Mid-Address Space Block Locking Register,” Section 22.4.2.3, “High-Address Space Block Locking Register (HBL),” Section 22.4.2.4, “Secondary Low-/Mid-Address Space Block Locking Register (SLL),” for more information. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-19 Preliminary...
Page 459 Aborting a program operation will leave the flash core addresses being programmed in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-20 Freescale Semiconductor Preliminary...
Page 460 Note: PEG will remain valid under this condition until EHV is set high or PGM is cleared. Step 9 Write MCR PGM = 0 ESUS User mode read state Erase suspend Figure 22-12. Program Sequence MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-21 Preliminary...
Page 461: Flash Erase
If the shadow row is to be erased, this step may be skipped, and LMS and HBS are ignored. For shadow row erase, see section Section 22.5.6, “Flash Shadow Block,” for more information. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-22 Freescale Semiconductor Preliminary...
Page 462 MCR[ERS] and MCR[EHV] are high and MCR[PGM] is low. A 0 to 1 transition of MCR[ESUS] causes the flash module to start the sequence which places it in erase suspend. The user must MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 463 This can extend the time required for the erase operation. CAUTION In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt flash core data. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-24 Freescale Semiconductor Preliminary...
Page 464: Flash Shadow Block
The user must terminate the shadow erase operation to program or erase the main address space. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 465: Flash Stop Mode
After reset is negated, register accesses can be performed, although it should be noted that registers that require updating from shadow information, or other inputs, cannot read updated until flash exits reset. 22.6 DMA Requests The flash has no DMA requests. MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-26 Freescale Semiconductor Preliminary...
Page 466: Interrupt Requests
Flash Array and Control 22.7 Interrupt Requests The flash has no interrupt requests. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 22-27 Preliminary...
Page 467 Flash Array and Control MPC5510 Microcontroller Family Reference Manual, Rev. 1 22-28 Freescale Semiconductor Preliminary...
Page 468: Introduction
Introduction The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the MPC5510 and external devices. The DSPI supports pin-count reduction through serialization and deserialization of eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. There are up to four identical DSPI blocks: DSPI_A, DSPI_B, DSPI_C, and DSPI_D;...
Page 469: Features
Programmable SPI transfer attributes on a per-frame basis: — Eight clock and transfer attribute registers — Serial clock with programmable polarity and phase — Programmable delays: – PCS to SCK delay MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-2 Freescale Semiconductor Preliminary...
Page 470: Features
Debug and STOP (with STOP ack) are supported. • The reset value of the MDIS register bit is 1 and thus the DSPI is disabled by default after reset. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-3 Preliminary...
Page 471: Modes Of Operation
The address of each register is given as an offset to the DSPI base address. Registers are listed in address order, identified by complete name and mnemonic, and list the type of accesses allowed. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-4...
Page 472: Register Descriptions
The DSPI_MCR contains bits which configure various attributes associated with DSPI operation. The HALT and MDIS bits can be changed at any time but will take effect on the next frame boundary only. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 473 Modified Timing Format Enable. Enables a modified transfer format to be used. See Section 23.4.8.4, “Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1),” for more information. 0 Modified SPI transfer format disabled 1 Modified SPI transfer format enabled MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-6 Freescale Semiconductor Preliminary...
Page 474 Clear RX FIFO. Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX counter. The CLR_RXF bit is always read as zero. 0 Do not clear the RX FIFO counter 1 Clear the RX FIFO counter MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-7 Preliminary...
Page 475 The user must not write to the DSPI_TCR while the DSPI is running. Offset: DSPI_BASE + 0x0008 Access: Read/Write SPI_TCNT Reset Reset Figure 23-3. DSPI Transfer Count Register (DSPI_TCR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-8 Freescale Semiconductor Preliminary...
Page 476 CSI configuration follow the protocol described for DSI configuration. CSI configuration is only valid with master mode. See Section 23.4.5, “Combined Serial Interface (CSI) Configuration,” for more details. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-9 Preliminary...
Page 477 0x0014 (DSPI_CTAR2) 0x0018 (DSPI_CTAR3) 0x001C (DSPI_CTAR4) 0x0020 (DSPI_CTAR5) 0x0024 (DSPI_CTAR6) 0x0028 (DSPI_CTAR7) FMSZ CPOL CPHA PCSSCK PASC Reset CSSCK Reset Figure 23-4. DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTARn) MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-10 Freescale Semiconductor Preliminary...
Page 478 The table below lists the frame sizes. FMSZ Framesize FMSZ Framesize 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-11 Preliminary...
Page 479 PCSx. This field is only used in master mode. The table below lists the prescaler values. The description for bitfield ASC in Table 23-4 details how to compute the after SCK delay. After SCK Delay PASC Prescaler Value MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-12 Freescale Semiconductor Preliminary...
Page 480 The baud rate prescaler values are listed in the table below. The description for Section 23.4.7.1, “Baud Rate Generator,” details how to compute the baud rate. Baud Rate Prescaler Value MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-13 Preliminary...
Page 481 The PCS to SCK delay is a multiple of the system clock period and it is computed according to the following equation: × × ------------- - t CSC PCSSCK Prescaler value CSSCK Scaler value f SYS Note: See Section 23.4.7.2, “PCS to SCK Delay (tCSC),” for more details. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-14 Freescale Semiconductor Preliminary...
Page 482 The after SCK delay is a multiple of the system clock period, and it is computed according to the following equation: × × t ASC ------------- - PASC Prescaler value ASC Scaler value f SYS Note: See Section 23.4.7.3, “After SCK Delay (tASC),” for more details. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-15 Preliminary...
Page 483 The delay after transfer is a multiple of the system clock period and it is computed according to the following equation: × × ------------- - t DT PDT Prescaler value DT Scaler value f SYS Note: See Section 23.4.7.4, “Delay after Transfer (tDT),” for more details MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-16 Freescale Semiconductor Preliminary...
Page 484 DSPI_SR by writing a 1 to it. Writing a 0 to a flag bit has no effect. NOTE This register cannot be written in MDIS Mode, owing to the use of power saving mechanisms. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-17 Preliminary...
Page 485 1 to it or by an acknowledgement from the eDMA controller when the TX FIFO is full. 0 TX FIFO is full 1 TX FIFO is not full MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-18 Freescale Semiconductor...
Page 486 The DSPI_RSER also selects the type of request to be generated. See the individual bit descriptions for information on the types of requests the bits support. NOTE The user must not write to the DSPI_RSER while the DSPI is running. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-19 Preliminary...
Page 487 Receive FIFO Overflow Request Enable. Enables the RFOF flag in the DSPI_SR to generate an interrupt requests. 0 RFOF interrupt requests are disabled 1 RFOF interrupt requests are enabled bit 13 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-20 Freescale Semiconductor Preliminary...
Page 488 Only the TXDATA field is used for DSPI slaves. Offset: DSPI_BASE + 0x0034 Access: Read/Write CONT CTAS PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 Reset TXDATA Reset Figure 23-7. DSPI PUSH TX FIFO Register (DSPI_PUSHR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-21 Preliminary...
Page 489 1 Assert the PCSn signal Note: This bitfield is used in SPI master mode only. TXDATA Transmit Data. Holds SPI data to be transferred according to the associated SPI command. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-22 Freescale Semiconductor...
Page 490 TX FIFO. The registers are read-only and cannot be modified. Reading the DSPI_TXFRn registers does not alter the state of the TX FIFO. The MCU uses four registers to implement the TX FIFO, that is DSPI_TXFR0–DSPI_TXFR3 are used. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-23...
Page 491 RX FIFO. The DSPI_RXFR registers are read-only. Reading the DSPI_RXFRn registers does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO, that is DSPI_RXFR0–DSPI_RXFR3 are used. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-24 Freescale Semiconductor...
Page 492 The user must not write to the DSPI_DSICR while the DSPI is running. Offset: DSPI_BASE + 0x00BC Access: Read/Write TXSS Reset R DCO DPCS DPCS DPCS DPCS DPCS DPCS DSICTAS Reset Figure 23-11. DSPI DSI Configuration Register (DSPI_DSICR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-25 Preliminary...
Page 493 The DSPI_SDR contains the signal states of the parallel input signals from the eMIOS. The pin states of the parallel input signals are latched into the DSPI_SDR on the rising edge of every system clock. The MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-26...
Page 494 DSPI_DSICR is set, the data in the DSPI_ASDR is the source of the serialized data. Writes to the DSPI_ASDR take effect on the next frame boundary. Offset: DSPI_BASE + 0x00C4 Access: Read/Write Reset ASER_DATA [15:0] Reset Figure 23-13. DSPI DSI Alternate Serialization Data Register (DSPI_ASDR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-27 Preliminary...
Page 495 23.3.2.14 DSPI DSI Deserialization Data Register (DSPI_DDR) The DSPI_DDR holds the signal states for the parallel output signals. The DSPI_DDR is read-only and is memory mapped so that host software can read the incoming DSI frames. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-28 Freescale Semiconductor...
Page 496: Functional Description
DSI data is transferred. The type of data transferred (whether DSI or SPI) dictates which CTAR the CSI configuration will use. See Section 23.3.2.3, “DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTARn),” for information on DSPIx_CTAR fields. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-29 Preliminary...
Page 497: Modes Of Operation
The SPI and DSI configurations are valid in slave mode. CSI configuration is not available in slave mode. In SPI slave mode the slave transfer attributes are set in the DSPIx_CTAR0. In DSI slave mode the slave MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-30...
Page 498: Start And Stop Of Dspi Transfers
The transitions are described in Table 23-16. Reset Running TXRXS = 1 Power-on-Reset Stopped TXRXS = 0 Figure 23-16. DSPI Start and Stop State Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-31 Preliminary...
Page 499: Serial Peripheral Interface (Spi) Configuration
The main difference is that in master mode the DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-32...
Page 500 Section 23.3.2.6, “DSPI PUSH TX FIFO Register (DSPI_PUSHR).” TX FIFO entries can be removed from the TX FIFO only by being shifted out or by flushing the TX FIFO. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-33 Preliminary...
Page 501 RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is copied from the shift register to the RX FIFO. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-34 Freescale Semiconductor...
Page 502: Deserial Serial Interface (Dsi) Configuration
The DSI frames can be from four to 16 bits long. Figure 23-18 shows an example of how a master DSPI connects to a SPI slave in DSI configuration. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-35 Preliminary...
Page 503 Figure 23-18 shows the DSI serialization logic. Section 23.3.2.13, “DSPI DSI Transmit Comparison Register (DSPI_COMPR),” contains details on the DSPIx_COMPR. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-36 Freescale Semiconductor Preliminary...
Page 504 The transfer initiation conditions are selected by the CID bit in the DSPIx_DSICR. Table 23-17 lists the two transfer initiation conditions. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-37 Preliminary...
Page 505 Set by SIU IMUX2. See Table 6-23. eMIOS output channel 7 Set by SIU IMUX2. See Table 6-23. eMIOS output channel 8 Set by SIU IMUX2. See Table 6-23. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-38 Freescale Semiconductor Preliminary...
Page 506 Set by SIU IMUX2. See Table 6-23. eMIOS output channel 12 Set by SIU IMUX2. See Table 6-23. eMIOS output channel 13 Set by SIU IMUX2. See Table 6-23. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-39 Preliminary...
Page 507 Set by SIU IMUX2. See Table 6-23. eMIOS output channel 14 Set by SIU IMUX2. See Table 6-23. eMIOS output channel 15 Set by SIU IMUX2. See Table 6-23. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-40 Freescale Semiconductor Preliminary...
Page 508: Combined Serial Interface (Csi) Configuration
SPI commands and data from the TX FIFO. The data returned from the bus slave is either used to drive the parallel output signals (to the eMIOS) or is stored in the RX FIFO. CSI configuration MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 509 The transfer attributes for the DSI frames are determined by the DSPIx_CTAR selected by the DSICTAS field in the DSPIx_DSICR. Figure 23-25 shows the CSI serialization logic. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-42 Freescale Semiconductor Preliminary...
Page 510 Control logic RX FIFO Transfer Shift register priority logic 0 1 • • • • • 15 Parallel DSI deserialization outputs data register (P_OUT) Figure 23-26. CSI Deserialization Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-43 Preliminary...
Page 511: Buffered Spi Operation
DSPI TX FIFO RX FIFO Shift register Figure 23-27. DSPI Queue Transfer Control in MPC5510 23.4.7 DSPI Baud Rate and Clock Delay Generation The SCKx frequency and the delay values for serial transfer are generated by dividing the system clock frequency by a prescaler and a scaler with the option of doubling the baud rate.
Page 512 DSPIx_CTARn registers select the after SCK delay. The relationship between these variables is given in the following formula: × × PASC Table 23-24 shows an example of the computed after SCK delay. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-45 Preliminary...
Page 513 PCSSCK At the end of the transfer the delay between PCSS negation and PCSx negation is selected by the PASC field in the DSPIx_CTAR based on the following formula: MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-46 Freescale Semiconductor Preliminary...
Page 514: Transfer Formats
Section 23.4.8.3, “Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 0),” and Section 23.4.8.4, “Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1).” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-47 Preliminary...
Page 515 For the CPHA=0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial clock edge of the frame (edge 16) of Figure 23-30. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-48 Freescale Semiconductor Preliminary...
Page 516 SPI mode to allow for delays in device pads and board traces. These delays become a more significant fraction of the SCK period as the SCK period decreases with increasing baud rates. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 517 Master SOUT System clock System clock = PCS to SCK delay. = After SCK delay. Figure 23-32. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, Fsck = Fsys/4) MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-50 Freescale Semiconductor Preliminary...
Page 518 The idle states of the chip select signals are selected by the PCSIS field in the DSPIx_MCR. Figure 23-34 shows the timing diagram for two four-bit transfers with CPHA = 1 and CONT = 0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-51...
Page 519 When the CONT bit = 1 and the PCS signals for the next transfer are different from the present transfer, the PCS signals behave as if the CONT bit was not set. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-52...
Page 520: Continuous Serial Communications Clock
Switching clock polarity between frames while using continuous SCK can cause errors in the transfer. Continuous SCK operation is not guaranteed if the DSPI is put into module disable mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-53...
Page 521: Peripheral Chip Select Expansion And Deglitching
32 peripheral chip select signals can be used if deglitching is desired. The PCSS signal provides the appropriate timing to enable and disable the demultiplexer for the PCS[0:4] signals. Figure 23-39 shows how an external 5-to-32 demultiplexer (decoder) can be connected to the DSPI. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-54 Freescale Semiconductor Preliminary...
Page 522: Dma And Interrupt Conditions
TX FIFO is less than the maximum number of possible entries, and the TFFF_RE bit in the DSPIx_RSER is asserted. The TFFF_DIRS bit in the DSPIx_RSER selects whether a DMA request or an interrupt request is generated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-55...
Page 523: Power Saving Features
DSPI. If there is no serial transfer in progress, the DSPI immediately asserts an acknowledge signal to the system, allowing the clocks to be disabled. If a serial transfer is in progress when the request is received, MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-56...
Page 524: Initialization/Application Information
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in the eDMA controller. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-57...
Page 525: Baud Rate Settings
PBR and the baud rate scaler BR in the DSPIx_CTARs. The values calculated assume a 66 MHz system frequency. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-58 Freescale Semiconductor...
Page 526: Delay Settings
) and CS to SCK delay (t ) that can be generated based on the prescaler values and the scaler values set in the DSPIx_CTARs. The values calculated assume a 66 MHz system frequency. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-59 Preliminary...
Page 527: Calculation Of Fifo Pointer Addresses
FIFO counter. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO. See Section 23.4.3.4, “Transmit First-In First-Out (TX FIFO) Buffering Mechanism,” and Section 23.4.3.5, “Receive First-In First-Out (RX FIFO) Buffering Mechanism,” for details on the FIFO operation. MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-60 Freescale Semiconductor Preliminary...
Page 528 Last-in entry address = RX FIFO base + 4*[(RXCTR + POPNXTPTR - 1) modulo RX FIFO depth] RX FIFO base: base address of RX FIFO RXCTR: RX FIFO counter POPNXTPTR: pop next pointer RX FIFO depth: receive FIFO depth MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 23-61 Preliminary...
Page 529 Deserial Serial Peripheral Interface (DSPI) MPC5510 Microcontroller Family Reference Manual, Rev. 1 23-62 Freescale Semiconductor Preliminary...
Page 530: Introduction
Peripheral BAUD ÷16 Data format control bus clock generator Transmit control TDRE generation Transmit shift register TC IRQ eSCI data register TX data out Figure 24-1. eSCI Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-1 Preliminary...
Page 531: Features
(receive data input of eSCI_x). Refer to Table 2-1 Section 2.7, “Detailed External Signal Descriptions,” for detailed signal descriptions. 24.3 Memory Map and Registers This section provides a detailed description of all eSCI registers. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-2 Freescale Semiconductor Preliminary...
Page 532: Module Memory Map
This section lists the eSCI registers in address order and describes the registers and their bit fields. 24.3.2.1 eSCI Control Register 1 (ESCIx_CR1) Offset: Base + 0x0000 Access: Read/Write Reset LOOPS RSRC WAKE TCIE ILIE Reset Figure 24-2. eSCI Control Register 1 (ESCIx_CR1) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-3 Preliminary...
Page 533 Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-4 Freescale Semiconductor Preliminary...
Page 534 Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters. 0 No break characters 1 Transmit break characters MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-5 Preliminary...
Page 535 Single-Wire mode of operation. This bit is only relevant in the Single-Wire mode of operation. 0 TXD pin to be used as an input in Single-Wire mode 1 TXD pin to be used as an output in Single-Wire mode MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-6 Freescale Semiconductor Preliminary...
Page 536 ESCIx_DR[8–15] (provided that SCI communication was successful). Writing to ESCIx_DR [8–15] provides bits 7–0 for SCI transmission. NOTES ESCIx_DR should not be used in LIN mode, writes to this register are blocked in LIN mode (ESCIx_LCR[LIN] = 1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-7 Preliminary...
Page 537 0 Receiver input is either active now or has never become active because the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-8 Freescale Semiconductor...
Page 538 Transmit Data Ready. The LIN FSM can accept another write to ESCIx_LTR. This bit is set when the ESCIx_LTR register becomes free. Clear TXRDY by writing it with 1. 0 ESCIx_LTR register is not free 1 ESCIx_LTR register is free MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-9 Preliminary...
Page 539 LIN bus. Set when the condition is detected and cleared by writing 1 to it. 0 No overflow 1 Overflow detected 24.3.2.5 LIN Control Register (ESCIx_LCR) ESCIx_LCR can be written when there are no ongoing transmissions only. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-10 Freescale Semiconductor Preliminary...
Page 540 LIN RXREG Ready Interrupt Enable. Generates an interrupt when new data is available in the LIN RXREG. TXIE LIN TXREG Ready Interrupt Enable. Generates an interrupt when new data can be written to the LIN TXREG. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-11...
Page 541 It is also possible to flush the ESCIx_LTR by setting the ESCIx_LCR[LRES] bit. NOTE Not all values written to the ESCIx_LTR will generate valid LIN frames. The values are determined according to the LIN specification. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-12 Freescale Semiconductor Preliminary...
Page 542 8–31 Reserved. The values 3C, 3D, 3E, and 3F of the ID-field (ID0-5) indicate command and extended frames. Refer to LIN specification revision 2.0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-13 Preliminary...
Page 543 The time is specified in multiples of bit times. The timeout period starts with the transmission of the LIN break character. bits 8–31 Reserved. Table 24-11. ESCIx_LTR Tx Frame Fourth+ Byte/ Rx Frame Fifth+ Byte Field Description Field Description Data bits for transmission. bits 8–31 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-14 Freescale Semiconductor Preliminary...
Page 544 Note: The data must be collected and the LIN frame finished (including CRC and checksum if applicable) before a wakeup character can be sent. bits 8–31 Reserved. 24.3.2.8 LIN CRC Polynomial Register (ESCIx_LPR) ESCIx_LPRn can be written when there are no ongoing transmissions. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-15 Preliminary...
Page 545: Functional Description
The CPU monitors the status of the eSCI, writes the data to be transmitted, and processes received data. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-16 Freescale Semiconductor...
Page 546: Data Format
Bit M in ESCIx_CR1 set data bit START START Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 STOP Figure 24-12. eSCI Data Formats MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-17 Preliminary...
Page 547: Baud Rate Generation
(Hz) clock (Hz) rate 0x0012 3,666,667 229,167 230,400 –0.54 0x0024 1,833,333 114,583 115,200 –0.54 0x0048 916,667 57,292 57,600 –0.54 0x006B 616,822 38,551 38,400 +0.39 0x00D7 306,977 19,186 19,200 –0.07 MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-18 Freescale Semiconductor Preliminary...
Page 548: Transmitter
The eSCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in eSCI control register 1 (ESCIx_CR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in the eSCI data register (ESCIx_DR) is the ninth bit (bit 8). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-19...
Page 549 A logic 1 stop bit goes into the most significant bit position. The eSCI hardware supports odd or even parity. When parity is enabled, the most significant bit (msb) of the data character is the parity bit. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-20 Freescale Semiconductor Preliminary...
Page 550 May set the overrun flag, OR, noise flag, NF, parity error flag, PF, or the receiver active flag, RAF. For more detail, see Section 24.3.2.4, “eSCI Status Register (ESCIx_SR).” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-21 Preliminary...
Page 551 If SBSTP is 0, the remainder of the byte will be transmitted normally. • If SBSTP is 1, the remaining bits in the byte after the error bit are transmitted as 1s (idle). MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-22 Freescale Semiconductor...
Page 552: Receiver
H 8 7 6 5 4 3 2 1 0 L All 1s LOOP control LOOPS RSRC WAKE Wakeup Logic Parity Checking IDLE IDLE interrupt ILIE request RDRF RDRF/OR interrupt request Figure 24-16. eSCI Receiver Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-23 Preliminary...
Page 553 To verify the start bit and to detect noise, the eSCI data recovery logic takes samples at RT3, RT5, and RT7. Table 24-17 summarizes the results of the start bit verification samples. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-24 Freescale Semiconductor Preliminary...
Page 554 To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 24-19 summarizes the results of the stop bit samples. Table 24-19. Stop Bit Recovery RT8, RT9, and RT10 samples Framing error flag Noise flag MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-25 Preliminary...
Page 555 As the receiver samples an incoming frame and re-synchronizes the RT clock on any valid falling edge within the frame. Re-synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-26 Freescale Semiconductor...
Page 556 Figure 24-20 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but remains sampled at RT8, RT9, and RT10. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-27...
Page 557 The transmitting device can address messages to selected receivers by including addressing information (address bits) in the initial frame or frames of each message. See section Section 24.4.1, “Data Format,” for an example of address bits. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-28 Freescale Semiconductor Preliminary...
Page 558: Single-Wire Operation
Normally, the eSCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the eSCI. The eSCI uses the TXD pin for both receiving and transmitting. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 559: Loop Operation
Each of the eSCI modules can be independently disabled by setting ESCIx_CR2[MDIS] = 1. Disabling the module turns off the clock to the module, although some of the module registers may be accessed by the MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-30...
Page 560: Interrupt Operation
(ESCIx_DR) is empty and that a new data can be written to the ESCIx_DR for transmission. The TDRE bit is cleared by writing a 1 to the TDRE bit location in the ESCIx_SR. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 561 The BERR flag is cleared by writing a 1 to the bit. A bit error will cause the LIN FSM to reset. Writing a 1 to the bit clears the BERR flag. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-32...
Page 562 RX frame is received. Writing a 1 to the bit clears the FRC flag. NOTE The last byte of a TX frame being sent or an RX frame being received indicates that the checksum comparison has taken place. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 24-33 Preliminary...
Page 563: Using The Lin Hardware
This feature supports LIN slaves with different LIN revisions. The LIN control register allows the user to decide whether the parity bits in the ID field should be calculated automatically and whether double MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-34...
Page 564 (the ESCIx_LTR). After transmission is complete, either the DMA controller or the LIN hardware can generate an interrupt to the CPU. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 565 RX frame has been stored, the DMA controller can indicate completion to the CPU. NOTE It is also possible to set up a whole sequence of RX and TX frames, and generate a single event at the end of that sequence. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-36 Freescale Semiconductor Preliminary...
Page 566 15 cycles, after a transmission has started, the LIN hardware will set the PBERR flag in the LIN status register. In addition a bit error may be generated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 567 Initially a wakeup character may need to be transmitted on the LIN bus, so that the LIN slaves activate. Other settings such as baud rate, length of break character etc., depend on the LIN slaves to which the eSCI is connected. MPC5510 Microcontroller Family Reference Manual, Rev. 1 24-38 Freescale Semiconductor Preliminary...
Page 568: Introduction
25.1 Introduction The MPC5510 contains six controller area network (FlexCAN) blocks. Each FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B and ISO Standard 11898. The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth.
Page 569: Features
— Content-related addressing • 64 flexible message buffers (MBs) of zero to eight bytes data length • Each message buffer configurable as Rx or Tx, all supporting standard and extended messages MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-2 Freescale Semiconductor Preliminary...
Page 570: Modes Of Operation
HALT bit in CANx_MCR is set, or if debug mode is requested by either core. In freeze mode no transmission or reception of frames is done, and synchronicity to the CAN bus is lost. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 571: External Signal Description
The Rx global mask (CANx_RXGMASK), Rx buffer 14 mask (CANx_RX14MASK) and the Rx buffer 15 mask (CANx_RX15MASK) registers are provided for backwards compatibility, and are not used when the BCC bit in CANx_MCR is asserted. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-4 Freescale Semiconductor...
Page 572 CANx_IFLAG1 — Interrupt Flags 1 Note1 25.3.4.10/25-2 0x0034–0x007F Reserved 0x0080–0x017F MB0–MB15 — Message Buffers Note1 25.3.2/25-6 0x0180–0x027F MB16–MB31 — Message Buffers Note1 0x0280–0x047F MB32–MB63 — Message Buffers Note1 0x0480-087F Reserved MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-5 Preliminary...
Page 573: Message Buffer Structure
The message buffer structure used by the FlexCAN module is represented in Figure 25-2. Both extended and standard frames (29-bit identifier and 11-bit identifier, respectively) used in the CAN specification (version 2.0 Part B) are represented. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-6 Freescale Semiconductor Preliminary...
Page 574 Data Field. Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from the CAN bus. For Tx frames, the CPU prepares the data field to be transmitted within the frame. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-7...
Page 575 Transmit data frame unconditionally once. After transmission, the MB automatically returns to the INACTIVE state. 1100 0100 Transmit remote frame unconditionally once. After transmission, the MB automatically becomes and Rx MB with the same ID. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-8 Freescale Semiconductor Preliminary...
Page 576: Rx Fifo Structure
ID table can assume, depending on the IDAM field of the CANx_MCR. Note that all elements of the table must have the same format. See Section 25.4.6, “Rx FIFO,” for more information. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-9 Preliminary...
Page 577 (Standard = 29-19, Extended = 29-16) (Standard = 13-3, Extended = 13-0) RXIDC_0 RXIDC_1 RXIDC_2 RXIDC_3 (Std/Ext = 31-24) (Std/Ext = 23-16) (Std/Ext = 15-8) (Std/Ext = 7-0) Figure 25-4. ID Table 0–7 MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-10 Freescale Semiconductor Preliminary...
Page 578: Register Descriptions
MAXMB field, which should only be changed while the module is in freeze mode. Offset: Base + 0x0000 Access: User read/write NOT_ FRZ_ LPM_ SOFT SRX_ MDIS FRZ HALT _RST Reset LPRIO IDAM MAXMB Reset Figure 25-5. Module Configuration Register (CANx_MCR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-11 Preliminary...
Page 579 0 FlexCAN module is either in normal mode, listen-only mode or loop-back mode. 1 FlexCAN module is either disabled or freeze mode. bit 5 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-12 Freescale Semiconductor Preliminary...
Page 580 CPU can poll the MDISACK bit to know when FlexCAN has actually been disabled. See Section 25.4.8.2, “Module Disabled Mode,” for more information. 0 FlexCAN not disabled. 1 FlexCAN is disabled. bits 12–13 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-13 Preliminary...
Page 581 One full ID (standard or extended) per filter element. Two full standard IDs or two partial 14-bit extended IDs per filter element. Four partial 8-bit IDs (standard or extended) per filter element. All frames rejected. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-14 Freescale Semiconductor Preliminary...
Page 582 Offset: Base + 0x0004 Access: User read/write PRESDIV PSEG1 PSEG2 Reset R BOFF ERR_ CLK_ TWRN RWRN BOFF LBUF LOM PROPSEG _MSK _ MSK _MSK _REC Reset Figure 25-6. Control Register (CANx_CTRL) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-15 Preliminary...
Page 583 Status Register. This bit has no effect if the WRNEN bit in CANx_MCR is negated and it is read as zero when WRNEN is negated. 1 = Tx Warning Interrupt enabled 0 = Tx Warning Interrupt disabled MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-16 Freescale Semiconductor Preliminary...
Page 584 0–7. × Propagation Segment Time (PROPSEG + 1) Time Quanta Time Quantum = one S clock period One time quantum is equal to the S clock period. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-17 Preliminary...
Page 585 Locked frames which had matched a MB through a mask may be transferred into the MB (upon release) but may no longer match. Table 25-9 shows some examples of ID masking for standard and extended message buffers. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-18 Freescale Semiconductor Preliminary...
Page 586 25.3.4.4.1 Rx Global Mask (CANx_RXGMASK) This register is provided for legacy support. On MPC5510, setting the BCC bit in CANx_MCR causes the CANx_RXGMASK Register to have no effect on the module operation. CANx_RXGMASK is used as acceptance mask for all Rx MBs, excluding MBs 14 15, which have –...
Page 587 25.3.4.4.2 Rx 14 Mask (CANx_RX14MASK) This register is provided for legacy support. On MPC5510, setting the BCC bit in CANx_MCR causes the CANx_RX14MASK Register to have no effect on the module operation. CANx_RX14MASK is used as acceptance mask for the Identifier in Message Buffer 14. When the FEN bit in CANx_MCR is set (FIFO enabled), the CANx_RX14MASK also applies to element 6 of the ID filter table.
Page 588 If the RXECTR increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. At the next successful message reception, the counter is set to a value between 119 and 127 to resume to ‘error active’ state. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-21...
Page 589 Offset: Base + 0x0020 Access: User read/write TWRN_ RWRN_ Reset R BIT1_ BIT0_ ACK_ CRC_ FRM_ STF_ IDLE TXRX FLT_CONF BOFF_ ERR_ Reset Figure 25-10. Error and Status Register (CANx_ESR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-22 Freescale Semiconductor Preliminary...
Page 590 0 No such occurrence 1 TXECTR ≥ 96 RXWRN Rx Error Counter. This status bit indicates when repetitive errors are occurring during messages reception. 0 No such occurrence 1 RXECTR ≥ 96 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-23 Preliminary...
Page 591 (that is, when the corresponding CANx_IFLAG2 bit is set). Offset: Base + 0x0024 Access: User read/write R BUF Reset R BUF Reset Figure 25-11. Interrupt Masks 2 Register (CANx_IMASK2) MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-24 Freescale Semiconductor Preliminary...
Page 592 This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding CANx_IFLAG2 bit. If the corresponding MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 593 When the FEN bit in the CANx_MCR is set (FIFO enabled), the function of the eight least significant interrupt flags (BUF7I - BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I and BUF5I indicate operating conditions of the FIFO, while BUF4I to BUF0I are not used. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-26 Freescale Semiconductor...
Page 594 These registers are used as acceptance masks for ID filtering in Rx MBs and the FIFO. If the FIFO is not enabled, one mask register is provided for each available message buffer, providing ID masking capability MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 595: Functional Description
MB with a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides the prioritization of MBs to be transmitted based on the message ID (optionally augmented by 3 local priority bits) or the MB ordering. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-28 Freescale Semiconductor...
Page 596: Transmit Process
1. If LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 597: Receive Process
Section 25.3.2, “Message Buffer Structure”) • A status flag is set in the interrupt flag register and an interrupt is generated if allowed by the corresponding interrupt mask register bit MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-30 Freescale Semiconductor Preliminary...
Page 598: Matching Process
8-entry ID table from FIFO is scanned first and then, if a match is not found within the FIFO table, the other MBs are scanned. In the event that the FIFO is full, the matching algorithm will always look for a matching MB outside the FIFO region. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-31...
Page 599 FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK, CANx_RX14MASK, and CANx_RX15MASK) for backwards compatibility. This alternate masking scheme is enabled when the BCC bit in the CANx_MCR Register is negated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-32 Freescale Semiconductor...
Page 600: Data Coherence
CANx_IFLAG is reset, the CPU must wait for it to be set, and then the CPU must read the CODE field to check if the MB was aborted (CODE=1001) or it was transmitted (CODE=1000). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-33...
Page 601 (‘0100’). Also, Tx MBs can not be locked. 1.In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honoured when the BCC bit is negated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-34 Freescale Semiconductor Preliminary...
Page 602: Rx Fifo
A powerful filtering scheme is provided to accept only frames intended for the target application, thus reducing the interrupt servicing work load. The filtering criteria is specified by programming a table of 8 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 603: Can Protocol Related Features
IDs, it will be stored in the FIFO and presented to the CPU. Note that for filtering formats A and B, it is possible to select whether remote frames are accepted or not. For format C, remote frames are always accepted (if they match the ID). MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-36 Freescale Semiconductor...
Page 604 Number of Time Quanta 1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-37...
Page 605 5 .. 10 1 .. 2 4 .. 11 1 .. 3 5 .. 12 1 .. 4 6 .. 13 1 .. 4 7 .. 14 1 .. 4 MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-38 Freescale Semiconductor Preliminary...
Page 606: Modes Of Operation Details
Stops the prescaler, thus halting all CAN protocol activities • Grants write access to the CANx_ECR, which is read-only in other modes • Sets the NOTRDY and FRZACK bits in CANx_MCR MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-39 Preliminary...
Page 607 Sends a stop acknowledge signal to the CPU, so that it can shut down the clocks globally Exiting stop mode is done by the CPU resuming the clocks and removing the stop mode request. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-40...
Page 608: Interrupts
Unused MB space must not be used as general purpose RAM while FlexCAN is transmitting and receiving CAN frames. 25.5 Initialization and Application Information This section provides instructions for initializing the FlexCAN module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 25-41 Preliminary...
Page 609: Flexcan Initialization Sequence
(for bus off and error interrupts) and in CANx_MCR for wake-up interrupt • Negate the HALT bit in CANx_MCR Starting with this last event, FlexCAN attempts to synchronize with the CAN bus. MPC5510 Microcontroller Family Reference Manual, Rev. 1 25-42 Freescale Semiconductor Preliminary...
Page 610: Introduction
Channels 0 through 15 use channel type 1, channels 16 through 22 use channel type 2, and channel 23 uses channel type 3 (see Section 26.1.4, “Channel Types”). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-1 Preliminary...
Page 611: Features
Type 1 Output Disable Input[3:0] Figure 26-1. eMIOS200 Block Diagram 26.1.2 Features • 24 channels implemented using three channel types. • Channels features: — 16-bit registers for captured/match values MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-2 Freescale Semiconductor Preliminary...
Page 612: Modes Of Operation
26.1.4 Channel Types The 24 16-bit timer channels available on the MPC5510 are implemented using three different channel configurations. The available modes of operation for each channel type are listed in Table 26-1.
Page 613: External Signal Description
When the eMIOS function is not the primary function of the pin, then only the output functions are supported. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-4 Freescale Semiconductor...
Page 614: Output Disable Input — Emios200 Output Disable Input Signal
EMIOS_CCNTR[0] — Channel Counter Register 0x0000_0000 26.4.7/26-11 0x002C EMIOS_CCR[0] — Channel Control Register 0x0000_0000 26.4.8/26-11 0x0030 EMIOS_CSR[0] — Channel Status Register 0x0000_0000 26.4.9/26-16 0x0038–0x003F Reserved Unified Channel 1 Registers MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-5 Preliminary...
Page 615: Register Descriptions
The EMIOS_MCR contains global control bits for the eMIOS200 block. Offset: EMIOS_BASE + 0x0000 Access: User read/write MDIS FRZ GTBE GPREN Reset GPRE[0:7] Reset Figure 26-2. eMIOS200 Module Configuration Register (EMIOS_MCR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-6 Freescale Semiconductor Preliminary...
Page 616 1 Prescaler enabled bits 6–15 Reserved. GPRE Global Prescaler Bits. The GPRE bits select the clock divider value for the global prescaler. GPRE Divide Ratio 00000000 00000001 00000010 00000011 11111110 11111111 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-7 Preliminary...
Page 617: Emios200 Global Flag Register (Emios_Gfr)
0 Transfer enabled. Depending on the operation mode, transfer may occur immediately or in the next period. Unless stated otherwise, transfer occurs immediately. 1 Transfers disabled MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-8 Freescale Semiconductor Preliminary...
Page 618: Emios200 Disable Channel (Emiosucdis)
EMIOS_CADR[n]. A1 and A2 are cleared by reset. Table 26-8 summarizes the EMIOS_CADR[n] writing and reading accesses for all operation modes. For more information see Section 26.5.1.1, “Unified Channel Modes of Operation.” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-9 Preliminary...
Page 619: Emios200 B Register (Emios_Cbdr[N])
— — — — — — DAOC — — OPWFMB — OPWMCB — OPWMB — In these modes, the register EMIOS_CBDR[n] is not used, but B2 can be accessed. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-10 Freescale Semiconductor Preliminary...
Page 620: Emios200 Counter Register (Emios_Ccntr[N])
Figure 26-9. eMIOS200 Control Register (EMIOS_CCR[n]) The control register gathers bits reflecting the status of the unified channel input/output signals and the overflow condition of the internal counter, as well as several read/write control bits. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-11...
Page 621 Direct Memory Access Bit. The DMA bit selects if the FLAG generation will be used as an interrupt or as a DMA request. 0 FLAG assigned to interrupt request 1 FLAG assigned to DMA request MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-12 Freescale Semiconductor Preliminary...
Page 622 B, otherwise it has no effect. 0 Has no effect 1 Force a match at comparator B For input modes, the FORCMB bit is not used and writing to it has no effect. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-13 Preliminary...
Page 623 Note: If a reserved value is written to MODE the results are unpredictable. Table 26-10. MODE Bits MODE Mode of Operation 000_0000 GPIO (input) 000_0001 GPIO (output) 000_0010 SAIC 000_0011 SAOC 000_0100 IPWM 000_0101 MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-14 Freescale Semiconductor Preliminary...
Page 624 OPWMCB (flag in both edges, trail edge dead-time) 101_1111 OPWMCB (flag in both edges, lead edge dead-time) 110_0000 OPWMB (flag on B1 match) 110_0001 Reserved 110_0010 OPWMB (flag on A1or B1 matches) 110_0011– Reserved 111_1111 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-15 Preliminary...
Page 625: Emios200 Status Register (Emios_Csr[N])
The eMIOS200 block is reset at positive edge of the clock (synchronous reset). All registers are cleared on reset. 26.5.1 Unified Channel (UC) Figure 26-11 shows the unified channel block diagram. Each unified channel consists of: MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-16 Freescale Semiconductor Preliminary...
Page 626 Match Logic uc_rd_data[31:0] Mode Logic ips_byte[7:0] ips_byte[15:8] Control Signals ips_byte[23:16] ips_byte[31:24] channel_datapath ips_rwb uc_cnt_rd_data[n] ips_addr[29:27] Comparator A Counter Bus Comparator B emios_counter_bus[0] emios_counter_bus[1] uc_cnt_rd_data[n] Figure 26-11. Unified Channel Block Diagram MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-17 Preliminary...
Page 627 When changing MODE, the application software must go to GPIO mode first to reset the unified channel’s internal functions properly. Failure to do this could lead to invalid and unexpected output compare or input capture results or the FLAGs being set incorrectly. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-18 Freescale Semiconductor...
Page 628 EDPOL value being transferred to the output flip-flop and toggling the output flip-flop at each match, respectively. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-19...
Page 629 In order to guarantee coherent access, reading EMIOS_CADR[n] forces B1 to be updated with the content of register A1. At the same time transfers between B2 and B1 are disabled until the next read of MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-20...
Page 630 EMIOS_CBDR[n] read occurs. If EMIOS_CADR[n] read is performed, B1 is updated with A1 register content even if the B1 update is locked by a previous EMIOS_CADR[n] read operation. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-21...
Page 631 B2 and B1. These transfers are disabled until the next read of the EMIOS_CBDR[n] register. Reading EMIOS_CBDR[n] register forces A1 content to be transferred to B1 and re-enables transfers from B2 to B1, to take effect at the next edge capture. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-22 Freescale Semiconductor...
Page 632 EMIOS_CBDR[n] is read. After EMIOS_CBDR[n] is read, register A1 content is transferred to register B1 and the transfers from B2 to B1 are re-enabled to occur at the transfer edges, which is the leading edge in the Figure 26-19 example. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-23 Preliminary...
Page 633 B had occurred, i.e., the output pin will be set to the complement of EDPOL bit and the FLAG bit is set. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-24 Freescale Semiconductor...
Page 634 MCB mode. The internal counter must not reach 0x0 as consequence of a rollover.To avoid this the user must start MCB only if the value stored at internal counter is fewer than the value that EMIOS_CADR register stores. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-25...
Page 635 If A2 is written in cycle (n), this new value will be used in cycle (n+1) for A1 match. Flags are generated at A1 match only if MODE[5] is 0. If MODE[5] is set to 1 flags are also generated at the cycle boundary. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-26 Freescale Semiconductor...
Page 636 (n) in order to be used in cycle (n+1). Thus A1 receives this new value at the next cycle boundary. The update disable bits OUDIS[n] can be used to disable the update of A1 register. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 637 In the example shown in Figure 26-26 the internal counter prescaler is set to two. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-28 Freescale Semiconductor Preliminary...
Page 638 (n). This allows to use the A1 posedge match to mask the B1 negedge match when they occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty cycle is generated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 639 A2 or B2 data written on cycle (n) were loaded to A1 or B1, respectively, thus generating matches in cycle (n+1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-30...
Page 640 EDPOL bit value. This functionality targets applications that use active high signals and a high to low transition at A1 match. In this case EDPOL should be set to 0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 641 A1 match, thus the output flip-flop is set to the complement of EDPOL bit. This cycle corresponds to a 100% duty cycle signal. The same output signal can be generated for any A1 value greater or equal to B1. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-32 Freescale Semiconductor...
Page 642 This counter value defines the cycle boundary. Values written to A2 or B2 within cycle (n) are loaded into A1 or B1 registers, respectively, and used to generate matches in cycle (n+1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 643 PWM signal. Both A1 and B1 register values are changing within the same cycle, which allows to vary at the same time the duty cycle and dead-time values. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-34...
Page 644 B1 matches are enabled. When the match between register B1 and the selected time base occurs, the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 645 EDPOL bit value. NOTE FORCMA bit set does not set the internal time-base to 0x000001 as a regular A1 match. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-36 Freescale Semiconductor Preliminary...
Page 646 100% duty cycle output signal generated by setting A1=4 and B1=3. In this case the trailing edge is positioned at the boundary of cycle n+1, which is actually considered to belong to cycle n+2 and therefore does not cause the output flip-flip to transition. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-37...
Page 647 The A1 and B1 registers are double buffered and updated from A2 and B2, respectively, at the cycle boundary. The load operation is similar to the OPWFMB mode. Refer to Figure 26-28 for more information about A1 and B1 registers’ update. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-38 Freescale Semiconductor Preliminary...
Page 648 A1 Match Negedge Detection Detection B1 Match B1 Match Negedge B1 Match Negedge Detection Detection Output Pin FLAG Bit Set EDPOL = 0 Figure 26-35. OPWMB Mode Matches and Flags MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-39 Preliminary...
Page 649 A1 or B1 match. The output disable does not modify the flag bit behavior. There is one system clock delay between the assertion of the output disable signal and the transition of the output pin to EDPOL. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-40 Freescale Semiconductor...
Page 650 EDPOL bit at B1 match. If B1 is set to 0x000009, for instance, B1 match does not occur, thus a 0% duty cycle signal is generated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 651 Counting is enabled by setting the UCPREN bit in the EMIOS_CCR[n]. The counter can be stopped at any time by clearing this bit, thereby stopping the internal counter in the unified channel. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-42...
Page 652: Ip Bus Interface Unit (Biu)
The MDIS bit in the EMIOS_MCR register and the UCDIS bits in the EMIOSUCDIS registers are cleared during reset. On resetting the eMIOS200 all unified channels enter GPIO input mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-43...
Page 653: Interrupts
SAIC mode. When an output disable condition happens, the software interrupt routine must service the output channels before servicing the channels running SAIC. This procedure avoids glitches in the output pins. MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-44 Freescale Semiconductor...
Page 654: Coherent Accesses
Reading the EMIOS_CADR[n] register again in the same period of the last read of EMIOS_CBDR[n] register may lead to incoherent results. This will occur if the last read of EMIOS_CBDR[n] register occurred after a disabled B2 to B1 transfer. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 26-45...
Page 655 Enhanced Modular I/O Subsystem (eMIOS200) MPC5510 Microcontroller Family Reference Manual, Rev. 1 26-46 Freescale Semiconductor Preliminary...
Page 656 The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. 27.1.1 Block Diagram A simplified block diagram of the I C illustrates the functionality and interdependence of major blocks (see Figure 27-1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-1 Preliminary...
Page 657 The DMA interface is only valid when the I C module is configured for master mode and the DMA channel mux has selected the I C DMA request signals to be inputs to a DMA channel. MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-2 Freescale Semiconductor Preliminary...
Page 658 • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-3 Preliminary...
Page 659 C memory map. The address of each register is given as an offset to the I C base address. Registers are listed in address order, identified by complete name and mnemonic, and lists the type of accesses allowed. There are no MPC5510-specific register definitions for the I C module. Table 27-1. I...
Page 660 Reserved, must be cleared; will always read 0. 27.3.2.2 C Bus Frequency Divider Register (IBFD) Offset: 0x0001 Access: Read/write any time MULT Reset Figure 27-4. I C Bus Frequency Divider Register (IBFD) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-5 Preliminary...
Page 661 SCL Stop hold time = bus period (s) * mul * SCL Stop hold value Eqn. 27-4 SCL Hold(stop) SCL Hold(start) START condition STOP condition Figure 27-5. SCL Divider and SDA Hold MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-6 Freescale Semiconductor Preliminary...
Page 662 Divider Value Value Value Value Value 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-7 Preliminary...
Page 663 This bit is always read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, results in loss of arbitration. 0 No effect. 1 Generate repeat start cycle. MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-8 Freescale Semiconductor Preliminary...
Page 664 • A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of zero has no effect. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 665 In master-transmit mode, the first byte of data written to IBDR following assertion of MS is used for the address transfer and should comprise the calling address (in position D0–D6) concatenated with the required R/W bit (in position D7). MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-10 Freescale Semiconductor...
Page 666: I-Bus Protocol
Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer, and STOP signal. They are described briefly in the following sections and illustrated in Figure 27-10. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-11 Preliminary...
Page 667 (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. START condition STOP condition Figure 27-11. Start and Stop conditions MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-12 Freescale Semiconductor Preliminary...
Page 668 SCL is at logical 1 (see Figure 27-10). The master can generate a STOP even if the slave has generated an acknowledge, at which point the slave must release the bus. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-13 Preliminary...
Page 669 The first device to complete its high period pulls the SCL line low again. Start Counting High Period WAIT SCL1 SCL2 Internal Counter Reset Figure 27-12. I C Bus Clock Synchronization MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-14 Freescale Semiconductor Preliminary...
Page 670: Interrupts
C control register. It must be cleared by writing 1 to the IBIF bit in the interrupt service routine. The bus going idle interrupt needs to be additionally enabled by the BIIE bit in the IBIC register. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-15...
Page 671: Initialization/Application Information
Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The I C Bus interrupt bit (IBIF) is set also; an interrupt will be generated if the MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-16 Freescale Semiconductor...
Page 672 Before reading the last byte of data, a STOP signal must first be generated. The following example shows how a STOP signal is generated by a master receiver. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 673 CPU, and sets the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set. MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-18 Freescale Semiconductor...
Page 674 Read Data Dummy Read Generate Dummy Read Dummy Read From IBDR From IBDR Stop Signal From IBDR From IBDR And Store Figure 27-13. Flowchart of Typical I C Interrupt Routine MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-19 Preliminary...
Page 675: Dma Application Information
The first byte (the slave calling address) is always transmitted by the CPU. All subsequent data bytes (apart from the last data byte) can be transferred by the DMA controller. The last data byte must be transferred by the CPU. MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-20 Freescale Semiconductor...
Page 676 The first byte (the slave calling address) is always transmitted by the CPU. All subsequent data bytes (apart from the two last data bytes) can be read by the DMA controller. The last two data bytes must be transferred by the CPU. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-21...
Page 677 C module, disable the DMAEN bit in the IBCR register. The trigger to exit the DMA mode is that the programmed DMA transfer control descriptor (TCD) has completed all its transfers to/from the I C module. MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-22 Freescale Semiconductor Preliminary...
Page 678 I C IBCR register to disable the DMAEN bit. This TCD also has scatter-gather activated and is programmed to reload the initial TCD upon completion, MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 27-23...
Page 679 19.5 μs for additional system delays. The slow reaction case can be prevented in this way. The system user must decide which usage model suits his overall requirements best. MPC5510 Microcontroller Family Reference Manual, Rev. 1 27-24 Freescale Semiconductor...
Page 680 (RTI) timer, which runs on a separate clock and can be used for system wakeup. 28.1.1 Block Diagram A simplified block diagram of the PIT_RTI illustrates the functionality and interdependence of major blocks (see Figure 28-1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 28-1 Preliminary...
Page 681 All interrupts are maskable and can be initiated even when the bus clock is switched off • Power saving with a separate input clock for the RTI timer (all other timers share one common core clock) • Independent timeout periods for each timer MPC5510 Microcontroller Family Reference Manual, Rev. 1 28-2 Freescale Semiconductor Preliminary...
Page 682 28-2. The address of each register is given as an offset to the PIT_RTI base address. Registers are listed in address order, identified by complete name and mnemonic, and lists the type of accesses allowed. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 28-3...
Page 683 This section lists the PIT_RTI registers in address order and describes the registers and their bit fields. NOTE The RTI registers should be set when the RTI clock is running only. MPC5510 Microcontroller Family Reference Manual, Rev. 1 28-4 Freescale Semiconductor...
Page 684 These registers indicate the current timer position. In the case of the RTI, this will show a value which is several cycles old, since it originates from a potentially different clock domain. Offset: 0x0080–0x00A0 Access: User read Reset Reset Figure 28-3. PIT Current Timer Values (TVAL0–8) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 28-5 Preliminary...
Page 685 1 only. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred 1 RTI time-out has occurred 28.3.2.4 PIT Interrupt Enable Register (PITINTEN) This register enables PIT interrupts. MPC5510 Microcontroller Family Reference Manual, Rev. 1 28-6 Freescale Semiconductor Preliminary...
Page 686 This register decides whether a channel generates an interrupt or is used for DMA triggering. Offset: 0x0108 Access: User read/write Reset ISEL8 ISEL7 ISEL6 ISEL5 ISEL4 ISEL3 ISEL2 ISEL1 Reset Figure 28-6. PIT Interrupt/DMA Select Registers (PITINTSEL) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 28-7 Preliminary...
Page 687 This register controls whether the clock for the timers 1–8 is enabled. The RTI timer (timer 0) runs on a separate clock (XOSC) that is controlled by the CRP and PLL. MPC5510 Microcontroller Family Reference Manual, Rev. 1 28-8 Freescale Semiconductor...
Page 688 If desired, the current counter value of the timer can be read via the TVAL registers. The value of the RTI counter can be delayed considerably, as it is synchronized to the bus clock from the RTI clock domain. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 689 (e.g. the timer values), and then continue the operation. 28.4.3 Interrupts The interrupts generated by the PIT are listed in Table 28-10. Refer to the MCU specification for related vector addresses and priorities. MPC5510 Microcontroller Family Reference Manual, Rev. 1 28-10 Freescale Semiconductor Preliminary...
Page 690: Example Configuration
30 ms/20 ns = 1500000 cycles. The value for the TVAL register trigger would be calculated as (period / clock period) –1. This means that TVAL0 will be written with 004C4B3F hex, TVAL1 with 0x0003_E7FF, and TVAL8 with 0x0016_E35F. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 28-11 Preliminary...
Page 691 PIT_REG_P->pit_TLVAL8 = 0x0016E35F; // setup timer 8 for 1500000 cycles // timer 8 can’t generate interrupts -> no settings needed for trigger PIT_REG_P->pit_EN |= 1<<8; // start timer 8 MPC5510 Microcontroller Family Reference Manual, Rev. 1 28-12 Freescale Semiconductor Preliminary...
Page 692: Introduction
It supports up to four regions (via chip selects), each with its own programmed attributes. 29.1.1 Block Diagram A simplified block diagram of the EBI illustrates the functionality and interdependence of major blocks (see Figure 29-1). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-1 Preliminary...
Page 693: Features
In the 144-pin and 176-pin packages, there are 24 address bits with only 16 bits of data and four chip selects • Memory controller with support for various memory types: — Synchronous burst SDR flash and SRAM — Asynchronous/legacy flash and SRAM MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-2 Freescale Semiconductor Preliminary...
Page 694: Modes Of Operation
External Bus Interface (EBI) • Burst support (wrapped only) NOTE Because the MPC5510 has no cache, the core does not generate any burst accesses; therefore the only burst accesses possible to the EBI are from the DMA. • Bus monitor •...
Page 695 Non-chip-select transfers of non-32-bit size are supported in standard non-burst fashion. 16-bit data bus mode is entered when DBM=1 in the EBI_MCR. On MPC5510, the default value of the DBM bit out of reset is 0. Thus the EBI operates in 32-bit data bus mode by default.
Page 696: Signal Description
CS [0:3] — Chip Selects 0-3 CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the Primary external bus. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-5 Preliminary...
Page 697 TS is asserted by the current bus owner to indicate the start of a transaction on the external bus TS is only asserted for the first clock cycle of the transaction, and is negated in the successive clock cycles until the end of the transaction. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-6 Freescale Semiconductor...
Page 698: Signal Function And Direction By Mode
Read_Write (Output) non-EBI function Transfer acknowledge (I/O) non-EBI function Transfer error acknowledge (I/O) non-EBI function Transfer start (Output) non-EBI function Address latch enable (Output) WE[0:3] non-EBI function Write/Byte enables (Output) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-7 Preliminary...
Page 699: Signal Pad Configuration By Mode
29-3. The address of each register is given as an offset to the EBI base address. Registers are listed in address order, identified by complete name and mnemonic, and lists the type of accesses allowed. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-8 Freescale Semiconductor...
Page 700: Register Descriptions
The EBI registers are accessed with a clock signal separate from the clock used by the rest of the EBI. In module disable mode, the clock used by the non-register portion of the EBI is disabled to reduce power MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 701 0 External master mode is inactive (single master mode). 1 External master mode is active. Note: EXTM=1 is not supported on MPC5510. EARB External Arbitration. When EXTM = 0, the EARB bit is a don’t care, and is treated as 0.
Page 702 0 Only data on data pins for non-CS accesses. 1 Address on data multiplexing mode is used for non-CS accesses. Data Bus Mode. Controls whether the EBI is in 32-bit or 16-bit data bus mode. On MPC5510, the default value of DBM is 0.
Page 703 (treated as 0) for chip-select accesses with internal TA (SETA=0). 0 Disable bus monitor. 1 Enable bus monitor (for external TA accesses only). bits 25–31 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-12 Freescale Semiconductor Preliminary...
Page 704 Address on Data Bus Multiplexing. The AD_MUX bit controls whether accesses for this chip select have the address driven on the data bus in the address phase of a cycle. On MPC5510, the default value of AD_MUX is 1. 0 Address on data multiplexing mode is disabled for this chip select.
Page 705 An 8-word burst length is only supported for SoC’s using 64-bit data bus width. Because the MPC5510 uses a 32-bit data bus width, the value of the BL bit is a don’t care, and all burst transfers use a 4-word length.
Page 706 These bits are ignored when SETA=1. The total cycle length for the first beat (including the TS cycle): (2 + SCY) external clock cycles Section 29.5.3.1, “Example Wait State Calculation”. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-15 Preliminary...
Page 707: Functional Description
External Bus Interface Features 29.4.1.1 Multiplexed 32-bit Address/Data Bus (Single Master) This is the default mode of operation for MPC5510. See Section 29.1.3.6, “Multiplexed Address on Data Mode.” A 16-bit data bus mode is available via the DBM bit in EBI_MCR. See Section 29.1.3.5,...
Page 708 Burst inhibited Don’t care since external TA is used BSCY Don’t care since external TA is used AD_MUX Address on data multiplexing SETA Select external TA to terminate access MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-17 Preliminary...
Page 709 Each chip select can be configured (via the SETA bit) to have TA driven internally (by the EBI), or externally (by an external device). See Section 29.3.2.6, “EBI Base Registers 0–3 (EBI_BRn),” for more details on SETA bit usage. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-18 Freescale Semiconductor Preliminary...
Page 710 — — — — — — — — — — — — — — 16-bit — — — — — — — — 32-bit — — Burst — — MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-19 Preliminary...
Page 711 Program Size and Address Data Bus Byte Strobes HSIZE HUNALIGN byte offset [30:31] Half @0x1 0110 Half @0x3 0001 — (2 AHB transfers) 1000 Word @0x1 0111 (2 AHB transfers) 1000 MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-20 Freescale Semiconductor Preliminary...
Page 712 Table 29-12. Misalignment Cases Supported by a 32-bit EBI (external bus) Program Size ADDR[30:31] WE[0:3] and byte offset Half @0x1 1001 1011 0111 Half @0x3 1110 (2 AHB — 0111 transfers) 1011 — 0111 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-21 Preliminary...
Page 713: External Bus Operations
CLKOUT signal, and they are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. 29.4.2.2 Reset Upon detection of internal reset, the EBI immediately terminates all transactions. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-22 Freescale Semiconductor Preliminary...
Page 714 The flow and timing diagrams in this section assume that the EBI is configured in single master mode. 29.4.2.4.1 Single Beat Read Flow The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-23 Preliminary...
Page 715 Figure 29-9. Basic Flow Diagram of a Single Beat Read Cycle CLKOUT ADDR[8:31] RD_WR BDIP DATA[0:31] DATA is valid Figure 29-10. Single Beat 32-Bit Read Cycle, CS Access, Zero Wait States MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-24 Freescale Semiconductor Preliminary...
Page 716 The EBI drives address and control signals an extra cycle because it uses a latched version of the external TA (1 cycle delayed) to terminate the cycle. Figure 29-12. Single Beat 32-Bit Read Cycle, Non-CS Access, Zero Wait States MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-25...
Page 717 CS access and !SETA Asserts transfer acknowledge (TA) Asserts transfer acknowledge (TA) Waits 1 clock stops driving data Figure 29-13. Basic Flow Diagram of a Single Beat Write Cycle MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-26 Freescale Semiconductor Preliminary...
Page 718 Figure 29-14. Single Beat 32-Bit Write Cycle, CS Access, Zero Wait States CLKOUT ADDR[8:31] RD_WR BDIP DATA is valid DATA[0:31] Wait state WE[0:3] Figure 29-15. Single Beat 32-Bit Write Cycle, CS Access, One Wait State MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-27 Preliminary...
Page 719 In some cases, CS remains asserted during this dead cycle, such as the cases of back-to-back writes or read-after-write to the same chip-select. See Figure 29-20 Figure 29-21. The following diagrams show a few examples of back-to-back accesses on the external bus. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-28 Freescale Semiconductor Preliminary...
Page 720 Figure 29-17. Back-to-Back 32-Bit Reads to the Same CS Bank CLKOUT ADDR[8:31] RD_WR BDIP DATA[0:31] DATA is valid DATA is valid Figure 29-18. Back-to-Back 32-Bit Reads to Different CS Banks MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-29 Preliminary...
Page 721 External Bus Interface (EBI) CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA is valid DATA[0:31] DATA is valid Figure 29-19. Write After Read to the Same CS Bank MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-30 Freescale Semiconductor Preliminary...
Page 722 External Bus Interface (EBI) CLKOUT ADDR[8:31] RD_WR BDIP DATA is valid DATA is valid DATA[0:31] Figure 29-20. Back-to-Back 32-Bit Writes to the Same CS Bank MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-31 Preliminary...
Page 723 16-byte read accesses to external devices that use the chip selects . Accesses from an external master or to devices operating without a chip select are always single beat. If an internal request MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-32 Freescale Semiconductor...
Page 724 “Non-Chip-Select Burst in 16-bit Data Bus Mode.” 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 29.4.2.10, “Non-Chip-Select Burst in 16-bit Data Bus Mode.” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-33 Preliminary...
Page 725 Next to last data beat Negate BDIP Drives last data Asserts transfer acknowledge (TA) receives last data Figure 29-22. Basic Flow Diagram of a Burst Read Cycle MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-34 Freescale Semiconductor Preliminary...
Page 726 (BSCY). Figure 29-25 shows an example of the TBDIP = 0 timing for a 4-beat burst with BSCY = 1. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-35 Preliminary...
Page 727 In this context, a small access refers to an access whose burst length and port size are such that the number of bytes requested by the internal master cannot all be fetched (or written) in one external transaction. This MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-36...
Page 728 16-bit (8 beats), 32-bit (4 beats) The MPC5510 bus masters do not generate any 32-byte requests so these cases cannot occur. In 32-bit data bus mode (DBM=0 in EBI_MCR), two accesses are performed. In 16-bit data bus mode (DBM=1), one 2-beat burst access is performed and this is not considered a small access case. See Section 29.4.2.10, “Non-Chip-Select Burst in 16-bit Data Bus...
Page 729 64-bit boundary. In this case, an extra cycle is required between TA and the next TS in order to get the next 64-bits of write data internally and RD_WR negates during this extra cycle. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-38 Freescale Semiconductor...
Page 730 Even though misaligned non-burst transfers from internal masters are supported, the EBI naturally aligns the accesses when it sends them out to the external bus, splitting them into multiple aligned accesses if necessary. See Section 29.4.1.13, “Misaligned Access Support,” for these cases. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-39 Preliminary...
Page 731 The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of the access. The convention can be seen in Figure 29-29. 32-Bit 16-Bit Byte Figure 29-29. Internal Operand Representation Figure 29-30 shows the device connections on the AD[0:31] bus. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-40 Freescale Semiconductor Preliminary...
Page 732 — 32-bit OP0/OP2 OP1/OP3 TSIZ is not enabled on the MPC5510. Also applies when DBM=1 for 16-bit data bus mode. This case consists of two 16-bit external transactions, the first fetching OP0 and OP1, the second fetching OP2 and OP3.
Page 733 32-bit OP0/OP2 OP1/OP3 TSIZ is not enabled on the MPC5510. Also applies when DBM=1 for 16-bit data bus mode. This case consists of two 16-bit external transactions, the first writing OP0 and OP1, the second writing OP2 and OP3. 29.4.2.8 Arbitration The MPC5510 does not support arbitration.
Page 734 EBI recognizes the termination signals provided from an external device. Table 29-18. Termination Signals Protocol Action Negated Negated No termination Asserted Transfer error termination Negated Asserted Normal transfer termination MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-43 Preliminary...
Page 735 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit accesses. Figure 29-32 shows a 32-bit non-chip-select read in 16-bit data bus mode. Figure 29-33 shows a 32-bit non-chip-select write in 16-bit data bus mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-44 Freescale Semiconductor Preliminary...
Page 736 Compared to the normal EBI specification (e.g. 24 address pins+32 data pins), only 32 data pins are required. Compared to a 16-bit bus implementation, only 24 pins are required (e.g. ADDR[8:15] + ADDR[16:31]/DATA[16:31]). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-45...
Page 737 In general, timing diagrams in A/D multiplexing mode are similar to other diagrams in this document, excepting behavior of the ADDR and DATA busses, which can be seen in Figure 29-34. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-46 Freescale Semiconductor Preliminary...
Page 738 DATA[16:31] (or DATA[0:15]) are used for address and data on an external muxed device. ** Or DATA[0:15], based on D16_31 bit in EBI_MCR. Figure 29-34. Small Access (32-Bit Read to 16-Bit Port) on Address/Data Multiplexed Bus MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-47...
Page 739: Initialization/Application Information
The data timing is controlled by setting the SCY bits in the appropriate option register to the proper number of wait states to work with the access time of the asynchronous memory, exactly as done for a synchronous memory. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-48 Freescale Semiconductor...
Page 740 16-bit asynchronous memory using three wait states. Figure 29-38 shows a timing diagram of a write operation to a 16-bit asynchronous memory using three wait states. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 29-49 Preliminary...
Page 741: Connecting An Mcu To Multiple Memories
Connecting an MCU to Multiple Memories The MCU can be connected to more than one memory at a time. Figure 29-39 shows an example of two memories connected to one MCU. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-50 Freescale Semiconductor Preliminary...
Page 742: Dual-Mcu Operation With Reduced Pinout Mcus
More than one section may apply if the applicable pins are not present on one or both MCUs. NOTE The MPC5510 does not have TSIZ[0:1] or arbitration pins (BB, BR, BG). 29.5.5.1 Connecting 16-Bit MCU to 32-Bit MCU (Master/Master or Master/Slave) This scenario is straightforward.
Page 743 Therefore, the EBI bus monitor must be disabled when no TEA pin exists. MPC5510 Microcontroller Family Reference Manual, Rev. 1 29-52 Freescale Semiconductor...
Page 744: Introduction
Message Buffer Number: Position of message buffer configuration registers within the register map. For example, Message Buffer Number 5 corresponds to the MBCCS5 register. Microcontroller Unit μT Microtick Macrotick Media Access Test Symbol Network Idle Time MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-1 Preliminary...
Page 745: Color Coding
Controller host interface (CHI) • Protocol engine (PE) • Clock domain crossing unit (CDC) A block diagram of the FlexRay block with its surrounding modules is given in Figure 30-1. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-2 Freescale Semiconductor Preliminary...
Page 746 All FRM related offsets are stored in offset registers. The physical address pointer into the FRM window of the MCU system memory is calculated using the offset values the FlexRay memory base address. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-3...
Page 747: Features
1. Due to the tight timing requirements and overall system requirements of FlexRAY systems, usage of the PLL as the clock source has not been fully evaluated. It is recommended to use a 40 MHz crystal for the clock source. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-4...
Page 748: Modes Of Operation
The FlexRay block leaves the disabled mode and enters the normal mode, when the application writes 1 to the module enable bit MEN in the Module Configuration Register (MCR) NOTE When the FlexRay block was enabled, it cannot be disabled the later on. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-5 Preliminary...
Page 749: External Signal Description
This section provides a detailed description of the FlexRay block signals, connected to external pins. 30.2.1.1 FR_A_RX — Receive Data Channel A The FR_A_RX signal carries the receive data for channel A from the corresponding FlexRay bus driver. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-6 Freescale Semiconductor Preliminary...
Page 750: Controller Host Interface Clocking
1. Due to the tight timing requirements and overall system requirements of FlexRAY systems, usage of the PLL as the clock source has not been fully evaluated. It is recommended to use a 40 MHz crystal for the clock source. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 751: Oscillator Clocking
1. Due to the tight timing requirements and overall system requirements of FlexRAY systems, usage of the PLL as the clock source has not been fully evaluated. It is recommended to use a 40 MHz crystal for the clock source. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-8...
Page 752 Network Management Vector Length Register (NMVLR) Timer Configuration 0x005A Timer Configuration and Control Register (TICCR) 0x005C Timer 1 Cycle Set Register (TI1CYSR) 0x005E Timer 1 Macrotick Offset Register (TI1MTOR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-9 Preliminary...
Page 753 Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR) 0x0098 Receive FIFO Range Filter Configuration Register (RFRFCFR) 0x009A Receive FIFO Range Filter Control Register (RFRFCTR) Dynamic Segment Status 0x009C Last Dynamic Transmit Slot Channel A Register (LDTXSLAR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-10 Freescale Semiconductor Preliminary...
Page 754: Register Descriptions
Write one to clear. A flag bit that can be read, is cleared by writing a one, writing 0 has no effect. Reset Value Resets to zero. Resets to one. – Not defined after reset and not affected by reset. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-11 Preliminary...
Page 755 For some of the registers, a 16-bit wide write access is required to ensure correct operation. This write access requirement is stated in the detailed register description for each register affected 30.5.2.2.3 Internal Register Access The following memory-mapped registers are used to access multiple internal registers. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-12 Freescale Semiconductor Preliminary...
Page 756 Write: MEN, SCM, CHB, CHA, CLKSEL, BITRATE: Disabled Mode SFFE: Disabled Mode or POC:config CLKS CHA SFFE BITRATE Reset Figure 30-3. Module Configuration Register (MCR) This register defines the global configuration of the FlexRay block. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-13 Preliminary...
Page 757 PE channel 1 active ports FR_A_RX, FR_A_TX, and FR_A_TX_EN driven by FlexRay block ports FR_B_RX, FR_B_TX, and FR_A_TX_EN driven by FlexRay block PE channel 0 active PE channel 1 active MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-14 Freescale Semiconductor Preliminary...
Page 758 Write: Disabled Mode SYS_MEM_BASE_ADDR[31:16] Reset Figure 30-4. System Memory Base Address High Register (SYMBADHR) Base + 0x0006 Write: Disabled Mode SYS_MEM_BASE_ADDR[15:4] Reset Figure 30-5. System Memory Base Address Low Register (SYMBADLR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-15 Preliminary...
Page 759 Strobe Signal Select. This control field selects one of the strobe signals given in Table 30-13 to be enabled or disabled and assigned to one of the four strobe ports given in Table 30-13. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-16 Freescale Semiconductor Preliminary...
Page 760 0x18 FR_B_RX 0x19 FR_A_RX potential frame start channel pulse 0x1A FR_B_RX 0x1B FR_A_RX wakeup collision detected pulse 0x1C FR_B_RX 0x1D FR_A_RX content error detected level 0x1E FR_B_RX MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-17 Preliminary...
Page 761 0x46 slot count[5] value MT start 0x47 slot count[6] 0x48 slot count[7] 0x49 slot count[8] 0x4A slot count[9] 0x4B slot count[10] 0x4C cycle start pulse MT start MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-18 Freescale Semiconductor Preliminary...
Page 762 Figure 30-8. Message Buffer Segment Size and Utilization Register (MBSSUTR) This register is used to define the last individual message buffer that belongs to the first message buffer segment and the number of the last used individual message buffer. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-19...
Page 763 Protocol Configuration Register 29 (PCR29). 00 do not apply external offset correction value 01 reserved 10 subtract external offset correction value 11 add external offset correction value MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-20 Freescale Semiconductor Preliminary...
Page 764 Additional to FlexRay Communications System Protocol Specification, Version 2.1 Rev A After sending the RESET command, it is mandatory to execute the command sequence described in Section 30.7.5, “Protocol Reset Command” immediately, to reach the DEFAULT CONFIG state correctly. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-21 Preliminary...
Page 765 Receive FIFO B Not empty interrupt if the FNEBIE flag is asserted. 0 Receive FIFO B is empty or interrupt is disabled 1 Receive FIFO B is not empty and interrupt enabled MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-22 Freescale Semiconductor...
Page 766 Receive FIFO Channel A Not Empty Interrupt Enable. This flag controls if the receive FIFO A interrupt line is asserted when the FNEAIF flag is set. 0 Disable interrupt line 1 Enable interrupt line MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-23 Preliminary...
Page 767 Protocol Operation Control Register (POCR). If the value of listen_timeout is equal to zero, the protocol configuration setting is considered as illegal. 0 No such event. 1 Illegal protocol configuration detected. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-24 Freescale Semiconductor Preliminary...
Page 768 B crosses the slot boundary. This is related to the transmission across slot boundary violation as described in the FSP process of the FlexRay protocol. 0 No such event. 1 Transmission across boundary violation occurred on channel B. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-25 Preliminary...
Page 769 Protocol State Changed Interrupt Flag. This flag is set when the protocol state in the PROTSTATE field in the Protocol Status Register 0 (PSR0) has changed. 0 No such event. 1 Protocol state changed. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-26 Freescale Semiconductor Preliminary...
Page 770 0 interrupt request generation disabled 1 interrupt request generation enabled MOC_IE Missing Offset Correction Interrupt Enable. This bit controls MOC_IF interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-27 Preliminary...
Page 771 Figure 30-14. Protocol Interrupt Enable Register 1 (PIER1) This register defines whether or not the individual interrupt flags defined in Protocol Interrupt Flag Register 1 (PIFR1) can generate a protocol interrupt request. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-28 Freescale Semiconductor Preliminary...
Page 772 This register holds the CHI related error flags. The interrupt generation for each of these error flags is controlled by the CHI interrupt enable bit CHIE in the Global Interrupt Flag and Enable Register (GIFER). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-29 Preliminary...
Page 773 In this case, the FlexRay block does not grant the lock to the transmit side of a double transmit message buffer. 0 No such event 1 Double transmit buffer lock error occurred MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-30 Freescale Semiconductor Preliminary...
Page 774 0 No such event. 1 Illegal system memory access occurred. 30.5.2.16 Message Buffer Interrupt Vector Register (MBIVEC) Base + 0x0022 TBIVEC RBIVEC Reset Figure 30-16. Message Buffer Interrupt Vector Register (MBIVEC) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-31 Preliminary...
Page 775 30.5.2.18 Channel B Status Error Counter Register (CBSERCR) Base + 0x0026 Additional Reset: RUN Command STATUS_ERR_CNT Reset Figure 30-18. Channel B Status Error Counter Register (CBSERCR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-32 Freescale Semiconductor Preliminary...
Page 776 10 ALL 11 reserved PROTSTATE Protocol State. Protocol related variable: vPOC!State. This field indicates the state of the protocol. POC:default config POC:config POC:wakeup POC:ready POC:normal passive POC:normal active POC:halt POC:startup MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-33 Preliminary...
Page 777 30.5.2.20 Protocol Status Register 1 (PSR1) Base + 0x002A Additional Reset: CSAA, CSP, CPN: RUN Command Write: Normal Mode R CSAA CSP REMCSAT APTAC W w1c Reset Figure 30-20. Protocol Status Register 1 (PSR1) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-34 Freescale Semiconductor Preliminary...
Page 778 Window and the clock synchronization. The NIT related status bits NBVB, NSEB, NBVA, and NSEA are updated by the FlexRay block after the end of the NIT and before the end of the first slot of the next MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 779 A This status bit is set if there was a transmission conflicts during the symbol window on channel A. 0 No such event 1 Transmission conflict detected MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-36 Freescale Semiconductor Preliminary...
Page 780 Aggregated Boundary Violation on Channel B. This flag is set when a boundary violation has been detected on channel B. Boundary violations are detected in the communication slots, the symbol window, and the NIT. 0 No boundary violation detected 1 Boundary violation detected MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-37 Preliminary...
Page 781 Aggregated Valid Frame on Channel A. This flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel A. 0 No syntactically valid frames received 1 At least one syntactically valid frame received MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-38 Freescale Semiconductor Preliminary...
Page 782 Base + 0x0034 SLOTCNTA Reset Figure 30-25. Slot Counter Channel A Register (SLTCTAR) This register provides the number of the current slot in the current communication cycle for channel A. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-39 Preliminary...
Page 783 (PIFR0). Note: If the FlexRay block was not able to calculate a new rate correction term due to a lack of synchronization frames, the RATECORR value is not updated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-40 Freescale Semiconductor Preliminary...
Page 784 (GIFER). NOTE The meanings of the combined status bits MIF, PRIF, CHIF, RBIF, and TBIF are different from those mentioned in the Global Interrupt Flag and Enable Register (GIFER). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-41 Preliminary...
Page 785 If the number of wait states is greater than twice the TIMEOUT value, data will be lost, and the System Bus Communication Failure Error Flag SBCF_EF is set in the CHI Error Flag Register (CHIERFR). MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-42 Freescale Semiconductor Preliminary...
Page 786 This field provides the size of the internal list of frame IDs of received synchronization frames used for clock synchronization. 30.5.2.32 Sync Frame Table Offset Register (SFTOR) Base + 0x0042 Write: POC:config SFT_OFFSET[15:1] Reset Figure 30-32. Sync Frame Table Offset Register (SFTOR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-43 Preliminary...
Page 787 Tables for the even cycle are valid. The FlexRay block clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 Tables are not valid (update is ongoing) 1 Tables are valid (consistent). MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-44 Freescale Semiconductor Preliminary...
Page 788 Sync Frame Rejection ID. This field defines the frame ID of a frame that must not be used for clock synchronization. For details see Section 30.6.15.2, “Sync Frame Rejection Filtering”. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-45 Preliminary...
Page 789 Base + 0x004E (NMVR1) Base + 0x0050 (NMVR2) Base + 0x0052 (NMVR3) Base + 0x0054 (NMVR4) Base + 0x0056 (NMVR5) NMVP[15:8] NMVP[7:0] Reset Figure 30-37. Network Management Vector Registers (NMVR0–NMVR5) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-46 Freescale Semiconductor Preliminary...
Page 790 Description NMVL Network Management Vector Length. protocol related variable: gNetworkManagementVectorLength This field defines the length of the Network Management Vector in bytes. Legal values are between 0 and 12. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-47 Preliminary...
Page 791 Timer T1 State. This status bit provides the current state of timer T1. 0 timer T1 is idle 1 timer T1 is running NOTE Both timers are deactivated immediately when the protocol enters a state different from POC:normal active POC:normal passive. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-48 Freescale Semiconductor Preliminary...
Page 792 If the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer T1 will expire according to the changed value. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-49 Preliminary...
Page 793 30.5.2.43 Timer 2 Configuration Register 1 (TI2CR1) Base + 0x0062 Write: Anytime T2_MTOFFSET T2_MTCNT[15:0] Reset Figure 30-43. Timer 2 Configuration Register 1 (TI2CR1) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-50 Freescale Semiconductor Preliminary...
Page 794 Write Mode. This control bit defines the write mode of this register. 0 Write to all fields in this register on write access. 1 Write to SEL field only on write access. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-51...
Page 795 Slot Status Counter Registers (SSCR0–SSCR3). The correspondence is given in Table 30-55. For a detailed description of slot status counters, refer to Section 30.6.18.4, “Slot Status Counter Registers”. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-52 Freescale Semiconductor Preliminary...
Page 796 STATUSMASK[0] – This bit enables the counting for slots with the transmission conflict indicator bit set to 1. Table 30-55. Mapping between internal SSCCRn and SSCRn Condition Register Condition Defined for Register SSCCR0 SSCR0 SSCCR1 SSCR1 SSCCR2 SSCR2 SSCCR3 SSCR3 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-53 Preliminary...
Page 797 B vSS!ContentError vSS!ContentError Boundary Violation on Channel B. Protocol related variable: vSS!BViolation channel B vSS!BViolation vSS!BViolation Transmission Conflict on Channel B. Protocol related variable: vSS!TxConflict channel B vSS!TxConflict vSS!TxConflict MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-54 Freescale Semiconductor Preliminary...
Page 798 SSCCRn, which can be programmed by using the Slot Status Counter Condition Register (SSCCR). For more details, see Section 30.6.18.4, “Slot Status Counter Registers”. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-55 Preliminary...
Page 799 CYCCNTVAL Cycle Counter Value. This field provides the filter value for the MTS cycle count filter. 30.5.2.49 MTS B Configuration Register (MTSBCFR) Base + 0x0082 Write: MTE: Anytime CYCCNTMSK,CYCCNTVAL:POC:config CYCCNTMSK CYCCNTVAL Reset Figure 30-49. MTS B Configuration Register (MTSBCFR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-56 Freescale Semiconductor Preliminary...
Page 800 FlexRay block: Updates the message buffer header index after successful reception. Application: Provides initial message buffer header index. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-57 Preliminary...
Page 801 Write: POC:config SIDX Reset Figure 30-52. Receive FIFO Start Index Register (RFSIR) This register defines the message buffer header index of the first message buffer of the selected FIFO. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-58 Freescale Semiconductor Preliminary...
Page 802 FNEAIF flag in the Global Interrupt Flag and Enable Register (GIFER). The index wraps back to the first message buffer header index if the end of the FIFO was reached. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-59 Preliminary...
Page 803 This register defines the filter value for the message ID acceptance filter of the selected receive FIFO. For details on message ID filtering see Section 30.6.9.5, “Receive FIFO filtering.” MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-60 Freescale Semiconductor Preliminary...
Page 804 ID filtering see Section 30.6.9.5, “Receive FIFO filtering.” Table 30-69. RFFIDRFVR Field Descriptions Field Description FIDRFVAL Frame ID Rejection Filter Value. Filter value for the frame ID rejection filter. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-61 Preliminary...
Page 805 01 select frame ID range filter 1. 10 select frame ID range filter 2. 11 select frame ID range filter 3. Slot ID. Defines the IBD-selected frame ID boundary value for the SEL-selected range filter. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-62 Freescale Semiconductor Preliminary...
Page 806 0 range filter 0 disabled 1 range filter 0 enabled 30.5.2.62 Last Dynamic Transmit Slot Channel A Register (LDTXSLAR) Base + 0x009C LASTDYNTXSLOTA Reset Figure 30-62. Last Dynamic Slot Channel A Register (LDTXSLAR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-63 Preliminary...
Page 807 Table 30-75. Protocol Configuration Register Fields (Sheet 1 of 3) Name Description Unit coldstart_attempts gColdstartAttempts number action_point_offset gdActionPointOffset cas_rx_low_max gdCASRxLowMax gdBit dynamic_slot_idle_phase gdDynamicSlotIdlePhase minislot minislot_action_point_offset gdMinislotActionPointOffset minislot_after_action_point gdMinislot gdMinislotActionPointOffset static_slot_length gdStaticSlot MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-64 Freescale Semiconductor Preliminary...
Page 808 μT listen_timeout pdListenTimeout 14/15 key_slot_id pKeySlotId number key_slot_used_for_startup pKeySlotUsedForStartup bool key_slot_used_for_sync pKeySlotUsedForSync bool latest_tx gNumberOfMinislots pLatestTx minislot sync_node_max gSyncNodeMax number μT micro_initial_offset_a pMicroInitialOffset[A] μT micro_initial_offset_b pMicroInitialOffset[B] MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-65 Preliminary...
Page 809 Reset Figure 30-64. Protocol Configuration Register 0 (PCR0) 30.5.2.64.2 Protocol Configuration Register 1 (PCR1) Base + 0x00A2 Write: POC:config macro_after_first_static_slot Reset Figure 30-65. Protocol Configuration Register 1 (PCR1) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-66 Freescale Semiconductor Preliminary...
Page 810 Reset Figure 30-69. Protocol Configuration Register 5 (PCR5) 30.5.2.64.7 Protocol Configuration Register 6 (PCR6) Base + 0x00AC Write: POC:config symbol_window_after_action_point macro_initial_offset_a Reset Figure 30-70. Protocol Configuration Register 6 (PCR6) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-67 Preliminary...
Page 811 Figure 30-73. Protocol Configuration Register 9 (PCR9) 30.5.2.64.11 Protocol Configuration Register 10 (PCR10) Base + 0x00B4 Write: POC:config R single wake _slot macro_per_cycle chan abled Reset Figure 30-74. Protocol Configuration Register 10 (PCR10) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-68 Freescale Semiconductor Preliminary...
Page 812 Reset Figure 30-77. Protocol Configuration Register 13 (PCR13) 30.5.2.64.15 Protocol Configuration Register 14 (PCR14) Base + 0x00BC Write: POC:config rate_correction_out listen_timeout[20:16] Reset Figure 30-78. Protocol Configuration Register 14 (PCR14) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-69 Preliminary...
Page 813 Reset Figure 30-82. Protocol Configuration Register 18 (PCR18) 30.5.2.64.20 Protocol Configuration Register 19 (PCR19) Base + 0x00C6 Write: POC:config decoding_correction_a payload_length_static Reset Figure 30-83. Protocol Configuration Register 19 (PCR19) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-70 Freescale Semiconductor Preliminary...
Page 814 Figure 30-87. Protocol Configuration Register 23 (PCR23) 30.5.2.64.25 Protocol Configuration Register 24 (PCR24) Base + 0x00D0 Write: POC:config micro_per_cycle_min cluster_drift_damping max_payload_length_dynamic [19:16] Reset Figure 30-88. Protocol Configuration Register 24 (PCR24) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-71 Preliminary...
Page 815 Figure 30-91. Protocol Configuration Register 27 (PCR27) 30.5.2.64.29 Protocol Configuration Register 28 (PCR28) Base + 0x00D8 Write: POC:config R dynamic_slot macro_after_offset_correction _idle_phase Reset Figure 30-92. Protocol Configuration Register 28 (PCR28) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-72 Freescale Semiconductor Preliminary...
Page 816 1 Immediate commit mode Message Buffer Type. This bit applies only to transmit message buffers and defines the buffering type. 0 Single buffered transmit message buffer 1 Double buffered transmit message buffer MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-73 Preliminary...
Page 817 Section 30.6.6.3.3, “Message Buffer Status Update” for a detailed description of the update condtions. 0 Frame Header and Message buffer data field not updated. 1 Frame Header and Message buffer data field updated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-74 Freescale Semiconductor Preliminary...
Page 818 This register contains message buffer configuration data for the transmission mode, the channel assignment, and for the cycle counter filtering. For detailed information on cycle counter filtering, refer to Section 30.6.7.1, “Message Buffer Cycle Counter Filtering.” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-75...
Page 819 30.5.2.67 Message Buffer Frame ID Registers (MBFIDRn) Base + 0x0104 (MBFIDR0) Write: POC:config or MB_DIS Base + 0x010C (MBFIDR1) Base + 0x02FC (MBFIDR63) Reset Figure 30-97. Message Buffer Frame ID Registers (MBFIDRn) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-76 Freescale Semiconductor Preliminary...
Page 820 The application writes the index of the initially associated message buffer header field into this register. The FlexRay block updates this register after frame reception or transmission. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-77...
Page 821: Functional Description
Frame Header The frame header occupies the first six bytes in the message buffer header field. It contains all FlexRay frame header related information according to the FlexRay Communications System Protocol MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-78 Freescale Semiconductor...
Page 822: Message Buffer Types
The FlexRay block supports three types of individual message buffers, which are described in Section 30.6.6, “Individual Message Buffer Functional Description”. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-79 Preliminary...
Page 823 2 * MBDSR.MBSEG1DS bytes • the minimum length of the message buffer data field for individual message buffers assigned to the second segment is 2 * MBDSR.MBSEG2DS bytes. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-80 Freescale Semiconductor Preliminary...
Page 824 A receive FIFO consists of a set of physical message buffers in the FRM and a set of receive FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in Figure 30-102. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-81 Preliminary...
Page 825 Slot Status[i] SADR_MBHF[1] Frame Header[1] Data Field Offset[1] Slot Status[1] Message Buffer Header Fields RFDSR[A] RFSIR[A] RFARIR RFDSR[B] RFSIR[B] RFBRIR Receive FIFO Control Register Figure 30-102. Receive FIFO Structure MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-82 Freescale Semiconductor Preliminary...
Page 826 During normal operation, each individual message buffer can be controlled by the control and trigger bits CMT, LCKT, EDT, and MBIE in the Message Buffer Configuration, Control, Status Registers (MBCCSRn). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-83 Preliminary...
Page 827: Flexray Memory Layout
The FRM starts at a 16 byte boundary. The FRM contains three areas: the message buffer header area, the message buffer data area, and the sync frame table area. The areas are described in this section. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-84 Freescale Semiconductor...
Page 828 Message Buffer Data Area The message buffer data area contains all the message buffer data fields of the physical message buffers. Each message buffer data field must start at a 16-bit boundary. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-85...
Page 829: Physical Message Buffer Description
The structure of the frame header in the message buffer header field is given in Figure 30-104. A detailed description of the frame header fields is given in Table 30-83. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-86 Freescale Semiconductor Preliminary...
Page 830 The PE generates a syntactically and semantically correct frame with payload_length_static payload words and the payload length field in the frame header set to payload_length_static. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-87...
Page 831 ID error flag FID_EF in the CHI Error Flag Register (CHIERFR). The value of the FID field will be ignored and replaced by the value provided in the Message Buffer Frame ID Registers (MBFIDRn). MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-88 Freescale Semiconductor Preliminary...
Page 832 FIFOs. The content of the slot status structure for receive message buffers depends on the message buffer type and on the channel assignment for individual receive message buffers as given by Table 30-84. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-89 Preliminary...
Page 833 B vRF!Header!SyFIndicator vRF!Header!SyFIndicator Null Frame Indicator Channel B. Protocol related variable: vRF!Header!NFIndicator channel B vRF!Header!NFIndicator vRF!Header!NFIndicator Startup Frame Indicator Channel B. Protocol related variable: vRF!Header!SuFIndicator channel B vRF!Header!SuFIndicator vRF!Header!SuFIndicator MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-90 Freescale Semiconductor Preliminary...
Page 834 All other status bits in this structure are related to a receive process that may have occurred. The content of the slot status structure for transmit message buffers depends on the channel assignment as given by Table 30-86. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-91 Preliminary...
Page 835 Syntax Error on Channel B — protocol related variable: vSS!SyntaxError channel B vSS!SyntaxError vSS!SyntaxError Content Error on Channel B — protocol related variable: vSS!ContentError channel B vSS!ContentError vSS!ContentError MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-92 Freescale Semiconductor Preliminary...
Page 836 Receive Shadow Buffer in Segment 1 MBDSR.MBSEG1DS Individual Message Buffer in Segment 2 MBDSR.MBSEG2DS Receive Shadow Buffer in Segment 2 MBDSR.MBSEG2DS Receive FIFO for channel A RFDSR.ENTRY_SIZE (RFSR.SEL = 0) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-93 Preliminary...
Page 837 For receive message buffers, receive shadow buffers, and receive FIFOs, the application must not write to the message buffer data field. For transmit message buffers, the application must follow the write access restrictions given in Table 30-89. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-94 Freescale Semiconductor Preliminary...
Page 838: Individual Message Buffer Functional Description
The application configures the number of utilized individual message buffers by writing the message buffer number of the last utilized message buffer into the LAST_MB_UTIL field in the Message Buffer Segment Size and Utilization Register (MBSSUTR). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-95 Preliminary...
Page 839 A single transmit message buffer is used by the application to provide message data to the FlexRay block that will be transmitted over the FlexRay Bus. The FlexRay block uses the transmit message buffers to MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-96...
Page 840 The trigger bits MBCCSRn.EDT and MBCCSRn.LCKT, and the interrupt enable bit MBCCSRn.MBIE are not under access control and can be accessed from the application at any time. The status bits MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-97...
Page 841 – Disabled and Locked - Message Buffer under configuration. Excluded from message buffer search. HLck Locked - Applications access to data, control, and status. Included in message buffer search. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-98 Freescale Semiconductor Preliminary...
Page 842 Table 30-94. Single Transmit Message Buffer Application Transitions Transition Command Condition Description MBCCSRn.EDS = 0 Application triggers message buffer enable. MBCCSRn.EDT:= 1 MBCCSRn.EDS = 1 Application triggers message buffer disable. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-99 Preliminary...
Page 843 Idle, HLck SA > HD Slot Assigned > Message Buffer Disable MA > HD Message Available > Message Buffer Disable CCMa TX > HL Transmission Start > Message Buffer Lock MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-100 Freescale Semiconductor Preliminary...
Page 844 30-114. In this example, the message buffer with message buffer number n is Idle at the start of the search slot, matches the slot and cycle number of the next slot, and message buffer data are valid, i.e. MBCCSRn.CMT = 1. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-101...
Page 845 As a result of the message buffer search described in Section 30.6.7, “Individual Message Buffer Search”, the FlexRay block triggers the slot assigned transition SA for up to two transmit message buffers if at least MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-102 Freescale Semiconductor Preliminary...
Page 846 Since the null frame transmission will not use the message buffer data, the application can lock/unlock the message buffer during null frame transmission. A transmit message buffer timing and state change diagram for null frame transmission for this case is given in Figure 30-119. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-103 Preliminary...
Page 847 In any of these two cases, the status of the message buffer is not changed at all with the SU transition. The slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-104...
Page 848 Message Buffer Header Field: Frame Header Message Buffer Header Field: Slot Status Message Buffer Data Field: DATA[0-N] MBIDXRn.MBIDX MBCCSRn.DVAL/DUP MBCCSRn.MTD MBCCFRn.CHA/CHB/CCF* MBFIDRn.FID Figure 30-120. Receive Message Buffer Access Regions MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-105 Preliminary...
Page 849 LCKS Appl. Module Idle – Idle - Message Buffer is idle. Included in message buffer search. HDis – Disabled - Message Buffer under configuration. Excluded from message buffer search. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-106 Freescale Semiconductor Preliminary...
Page 850 MBCCSRn.EDS = 0 Application triggers message buffer enable. MBCCSRn.EDT:= 1 MBCCSRn.EDS = 1 Application triggers message buffer disable. MBCCSRn.LCKS = 0 Application triggers message buffer lock. MBCCSRn.LCKT:= 1 MBCCSRn.LCKS = 1 Application triggers message buffer unlock. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-107 Preliminary...
Page 851 If more than one matching message buffers assigned to a certain channel, then only the message buffer with the lowest message buffer number is in one of the states mentioned above. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-108 Freescale Semiconductor...
Page 852 Note: An empty dynamic slot is indicated by the following frame and slot status bit values: vSS!ValidFrame = 0 and vSS!SyntaxError = 0 and vSS!ContentError = 0 and vSS!BViolation = 0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-109 Preliminary...
Page 853 The receive shadow buffer concept applies only to individual receive message buffers. The intention of this concept is to ensure that only syntactically and semantically valid received non-null frames are MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-110 Freescale Semiconductor...
Page 854 Application Internal Message FlexRay Bus Transfer MB# 2n MB# 2n+1 message data message data message data Commit Side Transmit Side Figure 30-123. Double Transmit Buffer Structure and Data Flow MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-111 Preliminary...
Page 855 Message Buffer Data and Control access read/write Internal Message Transfer. write-only Slot Status Update Transmit Side read/write Message Buffer Configuration read-only Message Buffer Search read-only Internal Message Transfer, Message Transmission MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-112 Freescale Semiconductor Preliminary...
Page 856 A description of the states of the commit side of a double transmit message buffer is given in Table 30-104. Table 30-104. Double Transmit Message Buffer State Description (Sheet 1 of 2)(Commit Side) MBCCSR[2n] Access Region State Description LCKS Appl. Module common states MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-113 Preliminary...
Page 857 Disabled - Message Buffer under configuration. Excluded from message buffer search. CCITx – Internal Message Transfer - Message Buffer Data transferred from commit side to transmit side. transmit side specific states MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-114 Freescale Semiconductor Preliminary...
Page 858 LCKS bit. The lock and unlock commands will only affect the commit side. If the application triggers the lock transition HL while the commit side is in the state CCITx, the message buffer MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 859 The priorities among the FlexRay block transitions and the related states are given in the second part of Table 30-108. These priorities apply only to the transmit side. The internal message transmit start transition IS has tho lowest priority. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-116 Freescale Semiconductor Preliminary...
Page 860 The FlexRay block will not start the Internal Message Transfer for a message buffer as long as the message data on the transmit side is not transmitted at least once. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 861 The message buffer does not match the next slot. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-118...
Page 862: Individual Message Buffer Search
The message buffer search is a sequential algorithm which is invoked at the following protocol related events: 1. NIT start 2. slot start in the static segment 3. minislot start in the dynamic segment MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-119 Preliminary...
Page 863 Depending on the message buffer channel assignment the same message buffer can be found for both channel A and channel B. In this case, this message buffer is used as described in Section 30.6.3.1, “Individual Message Buffers”. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-120 Freescale Semiconductor Preliminary...
Page 864 In all other cases, the receive buffer will be found. Thus, if the block has no data to transmit in a dynamic slot, it is able to receive frames on that slot. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 865: Individual Message Buffer Reconfiguration
In the later case, the two single message buffers must have consecutive message buffer numbers and the smaller one must be even. Message Buffers can be RC3 reconfigured if they are in the HDis state. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-122 Freescale Semiconductor...
Page 866: Receive Fifo
Receive FIFO Depth and Size Register (RFDSR). • The length of the message buffer data field for the FIFO is written into the ENTRY_SIZE field in Receive FIFO Depth and Size Register (RFDSR). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-123 Preliminary...
Page 867 The FIFO will not receive invalid or null-frames. For each FIFO filter, the pass criteria is specified in the related section given below. Only frames that have passed all filters will be appended to the FIFO. The FIFO filter path is depicted in Figure 30-131. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-124 Freescale Semiconductor Preliminary...
Page 868 Consequently, a received valid frame with the frame ID FID passes the RX FIFO Frame ID Value-Mask Rejection Filter if Equation 30-11 is fulfilled. ∧ ≠ ∧ Eqn. 30-11 RFFIDRFMR FIDRFMSK RFFIDRFVR FIDRFVAL RFFIDRFMR FIDRFMSK MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-125 Preliminary...
Page 869 (RFMIAFMR). This filter applies only to valid frames received in the dynamic segment with the payload preamble indicator bit PPI set to 1. All other frames will pass this filter. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-126 Freescale Semiconductor...
Page 870: Channel Device Modes
FR_A_RX, FR_A_TX, and FR_A_TX_EN and can be connected to either the physical bus channel A (shown in Figure 30-133) or the physical bus channel B (shown in Figure 30-134). MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-127 Preliminary...
Page 871 A Channel A FR_A_TX_ cfg(A) Init Value for Frame CRC is cCrcInit[B] cCrcInit[A] FR_B_RX reg(B) FR_B_TX channel B FR_B_TX_ cfg(B) cCrcInit[B] Figure 30-134. Single Channel Device Mode (Channel B) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-128 Freescale Semiconductor Preliminary...
Page 872: External Clock Synchronization
FRM and ensures application access to consistent tables by means of table locking. Once the application has locked the table successfully, the FlexRay block will not overwrite these tables and the application can read a consistent snapshot. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-129...
Page 873 Sync Deviation ChB 14 Offset + $3A Sync Frame ID ChB 15 Sync Frame ID ChB 15 Sync Deviation ChB 15 Sync Deviation ChB 15 Figure 30-137. Sync Table Memory Layout MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-130 Freescale Semiconductor Preliminary...
Page 874 SFTCCSR.ELKS is set. This indicates that the application has successfully locked the even sync tables and the corresponding status information fields SFRA, SFRB in MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 875: Mts Generation
The application can configure the set of communication cycles in which the MTS will be transmitted over the FlexRay bus by programming the CYCCNTMSK and CYCCNTVAL fields in the MTS A Configuration Register (MTSACFR) MTS B Configuration Register (MTSBCFR). MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-132 Freescale Semiconductor Preliminary...
Page 876: Sync Frame And Startup Frame Transmission
POC:normal active In the POC:normal active state, the sync and startup frame transmission depends on the message buffer setup. If at least one of the indication bits PCR11.key_slot_used_for_sync or MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-133 Preliminary...
Page 877: Sync Frame Filtering
Eqn. 30-23 MCR SFFE ≠ FID 9:0 SFIDRFR SYNFRID 9:0 Eqn. 30-24 NOTE Sync frames are transmitted in the static segment only. Thus FID <= 1023. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-134 Freescale Semiconductor Preliminary...
Page 878: Strobe Signal Support
Other signals refer to events that occurred on the FlexRay Bus some cycles before the strobe signal is changed. These signals are listed in Table 30-13 with a positive clock offset. An example waveform is given in Figure 30-140. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-135 Preliminary...
Page 879: Timer Support
If timer T2 is configured as an absolute timer, it has the same functionality timer T1 but the configuration from Timer 2 Configuration Register 0 (TI2CR0) Timer 2 Configuration Register 1 (TI2CR1) is used. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-136 Freescale Semiconductor Preliminary...
Page 880: Slot Status Monitoring
Figure 30-141. Slot Status Vector Update NOTE The slot status for the NIT of cycle n is provided after the start of cycle n+1. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-137 Preliminary...
Page 881 NIT are taken into account. The counters wrap round after they have reached the maximum value. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-138...
Page 882 The increment condition for each slot status counter consists of two parts, the frame related condition part and the slot related condition part. The internal slot status counter SSCRn_INT is incremented if at least one of the conditions is fulfilled: 1. frame related condition: MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-139 Preliminary...
Page 883: Interrupt Support
MBCCSn.MBIE. The FlexRay block sets the interrupt flag when the slot status of the message buffer was updated. If the interrupt enable bit is asserted, an interrupt request is generated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-140 Freescale Semiconductor...
Page 884 The combined protocol interrupt request PRTIRQ is generated when at least one of the individual protocol interrupt sources generates an interrupt request and the interrupt enable bit GIFER.PRIE is set. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-141...
Page 885 30.6.19.2.5 Module Interrupt The combined module interrupt request MIRQ is generated if at least one of the combined interrupt sources generates an interrupt request and the interrupt enable bit GIFER.MIE is set. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-142 Freescale Semiconductor...
Page 886 GIFER.CHIF CHIIRQ GIFER.PRIF PRTIRQ & GIFER.PRIE GIFER.FNEAIF FNEAIRQ & GIFER.FNEAIE GIFER.FNEBIF FNEBIRQ & GIFER.FNEBIE GIFER.WUPIF WUPIRQ & GIFER.WUPIE GIFER.MIF MIRQ & GIFER.MIE Figure 30-143. Scheme of Cascaded Interrupt Request MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-143 Preliminary...
Page 887: Lower Bit Rate Support
Module Configuration Register (MCR). The protocol values are set internally. The available bit rates, the related BITRATE field configuration settings and related protocol parameter values are shown in Table 30-113. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-144 Freescale Semiconductor Preliminary...
Page 888: Application Information
1 to the module enable bit MEN in the Module Configuration Register (MCR) The FlexRay block now enters the Normal Mode. The application can commence with the protocol initialization described in Section 30.7.1.2, “Protocol Initialization”. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-145 Preliminary...
Page 889: Shut Down Sequence
This section describes the relationship between the number of message buffers that can be utilized and the required minimum CHI clock frequency. Additional constraints for the minimum CHI clock frequency are given in Section 30.3, “Controller Host Interface Clocking”. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-146 Freescale Semiconductor Preliminary...
Page 890: Protocol Control Command Execution
The PE maintains a protocol command vector. For each command that was accepted by the PE, the PE sets the corresponding command bit in the protocol command vector. If a command is issued while the corresponding command bit is set, the command is not queued and is lost. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-147...
Page 891: Protocol Reset Command
To overcome this message buffer internal lock situation, the application must put the protocol into the POC:default config state. This will release all internal message buffer locks. MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-148 Freescale Semiconductor Preliminary...
Page 892: Message Buffer Search On Simple Message Buffer Configuration
The availability of data in the transmit buffer is indicated by the commit bit MBCCSRt[CMT] and the lock bit MBCCSRt[LCKS]. The receive message buffer has the message buffer number r and has following configuration MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-149...
Page 893 When a slot occurs, if a slot is assigned to a node on a channel that node only transmits a frame on that channel if there is data ready and there is a match on relevant transmit filters (no null frames are sent). MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-150 Freescale Semiconductor...
Page 894 {4n+2}, which is assigned to the receive buffer only, the receive buffer will be found and the node can receive data. The receive and transmit cycles are shown in Figure 30-145 Figure 30-146. Transmit Data Not Available MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 30-151 Preliminary...
Page 895 FlexRay Communication Controller (FLEXRAY) MPC5510 Microcontroller Family Reference Manual, Rev. 1 30-152 Freescale Semiconductor Preliminary...
Page 896: Introduction
CFIFOs to the on-chip ADC. It also monitors the fullness of CFIFOs and RFIFOs, and accordingly generates DMA or interrupt requests to control data movement between the FIFOs and the system memory. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-1...
Page 897: Block Diagram
The ADC control logic performs the following functions: • Buffers command data for execution. • Decodes command data and accordingly generates control signals for the on-chip ADC. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-2 Freescale Semiconductor Preliminary...
Page 898: Features
DMAC. 2. VREF=VRH–VRL. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-3...
Page 899: Modes Of Operation
CFIFO. The message of the CFIFO that caused the abort of the previous serial transmission will only be transmitted after debug mode is exited. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-4 Freescale Semiconductor...
Page 900: External Signal Description
Refer to Table 2-1 Section 2.7, “Detailed External Signal Descriptions,” for detailed signal descriptions. 31.3 Memory Map and Registers This section provides a detailed description of all eQADC registers. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-5 Preliminary...
Page 901: Module Memory Map
CFIFO Control Register 1 (EQADC_CFCR1) 0x0054 eQADC CFIFO Control Register 2 (EQADC_CFCR2) 0x0056 eQADC CFIFO Control Register 3 (EQADC_CFCR3) 0x0058 eQADC CFIFO Control Register 4 (EQADC_CFCR4) 0x005A eQADC CFIFO Control Register 5 (EQADC_CFCR5) MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-6 Freescale Semiconductor Preliminary...
Page 902 FIFO and Interrupt Status Register 3 (EQADC_FISR3) 0x0080 eQADC FIFO and Interrupt Status Register 4 (EQADC_FISR4) 0x0084 eQADC FIFO and Interrupt Status Register 5 (EQADC_FISR5) 0x0088 Reserved 0x008C Reserved MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-7 Preliminary...
Page 903 0x01C0– 0x01CC eQADC CFIFO3 Registers (EQADC_CF3Rw) (w=0, .., 3) 31.3.3.12/31-23 0x01D0–0x01FC Reserved 0x0200– 0x020C eQADC CFIFO4 Registers (EQADC_CF4Rw) (w=0, .., 3) 31.3.3.12/31-23 0x0210–0x023C Reserved 0x0240–0x024C eQADC CFIFO5 Registers (EQADC_CF5Rw) (w=0, .., 3) 31.3.3.12/31-23 0x0250–0x02FC Reserved MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-8 Freescale Semiconductor Preliminary...
Page 904: Register Descriptions
The EQADC_MCR contains bits used to control how the eQADC responds to a debug mode entry request. Offset: Base+ 0x0000 Access: Read/Write Reset Reset Figure 31-2. eQADC Module Configuration Register (EQADC_MCR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-9 Preliminary...
Page 905 The digital filter length field specifies the minimum number of system clocks that the digital filter counter must count to recognize a logic state change. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-10 Freescale Semiconductor...
Page 906 45.45 0b0010 75.76 0b0011 136.36 0b0100 257.58 0b0101 500.00 0b0110 984.85 0b0111 1954.55 0b1000 3893.94 0b1001 7772.73 0b1010 1025 15530.30 0b1011 2049 31045.45 0b1100 4097 62075.76 0b1101 8193 124136.36 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-11 Preliminary...
Page 907 CF_PUSH that were not specifically designated as target locations for the write. 31.3.3.5 eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn) The eQADC_RFPRs provide a mechanism to retrieve data from RFIFOs. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-12 Freescale Semiconductor Preliminary...
Page 908 EQADC_BASE + 0x0052 (EQADC_CFCR1) EQADC_BASE + 0x0054 (EQADC_CFCR2) EQADC_BASE + 0x0056 (EQADC_CFCR3) EQADC_BASE + 0x0058 (EQADC_CFCR4); EQADC_BASE + 0x005A (EQADC_CFCR5) MODEn SSEn CFINVn Reset Figure 31-7. eQADC CFIFO Control Registers (EQADC_CFCRn) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-13 Preliminary...
Page 909 Software trigger, continuous scan 0b1010 Low-level gated external trigger, continuous scan 0b1011 High-level gated external trigger, continuous scan 0b1100 Falling-edge external trigger, continuous scan 0b1101 Rising-edge external trigger, continuous scan MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-14 Freescale Semiconductor Preliminary...
Page 910 Pause Interrupt Enable n. Enables the eQADC to generate an interrupt request when the corresponding PFx in EQADC_FISRn (See Section 31.3.3.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)” asserted. 0 Disable pause interrupt request 1 Enable pause interrupt request MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-15 Preliminary...
Page 911 RFOFn, CFUFn, and TORFn (assuming that all interrupts are enabled). See Section 31.4.7, “eQADC eDMA/Interrupt Request,” for details. 0 Disable overflow interrupt request 1 Enable overflow Interrupt request bit 13 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-16 Freescale Semiconductor Preliminary...
Page 912 Base + 0x0084 (EQADC_FISR5) R NCFn TORFn PFn EOQFn CFUFn SSSn CFFFn RFOFn RFDFn W w1c Reset CFCTRn TNXTPTRn RFCTRn POPNXTPTRn Reset Figure 31-9. eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-17 Preliminary...
Page 913 Note: In software or level trigger mode, when the eQADC completes the transfer of an entry from CFIFOn with an asserted pause bit, PFn will not be set and transfer of commands will continue without pausing. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-18...
Page 914 Note: When generation of interrupt requests is selected (CFFSn=0), CFFFn must only be cleared in the ISR after the CFIFOn push register is accessed. Note: CFFFn should not be cleared when CFFSn is asserted (eDMA requests selected). bits 7–11 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-19 Preliminary...
Page 915 POPNXTPTRn is wrapped to 0, else, it is incremented by 1. For details refer to Section 31.4.4.1, “RFIFO Basic Functionality.” Writing any value to POPNXTPTRn has no effect. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-20 Freescale Semiconductor Preliminary...
Page 916 EQADC_CFSSR register captures the status register before the status register changes, because of the transfer of the current command that is about to be popped from the CFIFO. The EQADC_CFSSR is read only. Writing to EQADC_CFSSR has no effect. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-21...
Page 917 This field has no meaning when LCFT0 is 0b1111. 31.3.3.11 eQADC CFIFO Status Register (EQADC_CFSR) The EQADC_CFSR contains the current CFIFO status. The EQADC_CFSRs are read only. Writing to the EQADC_CFSR has no effect. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-22 Freescale Semiconductor Preliminary...
Page 918 32-bit entries. Refer to Section 31.4.3, “eQADC Command FIFOs,” for more information on CFIFOs. These registers are read only. Data written to these registers is ignored. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-23 Preliminary...
Page 919 16-bit entries. Refer to Section 31.4.4, “Result FIFOs,” for more information on RFIFOs. These registers are read only. Data written to these registers is ignored. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-24 Freescale Semiconductor Preliminary...
Page 920: On-Chip Adc Registers
There are five non-memory-mapped registers for ADC0. The address, usage, and access privilege of each register is shown in Table 31-18. Data written to or read from reserved areas of the memory map is undefined. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-25 Preliminary...
Page 921 ADC0 Control Register (ADC0_CR) The ADC0 control register (ADC0_CR) is used to configure the on-chip ADC. Offset: 0x0001 Access: Read/Write R ADC0 ADC0_CLK_PS Reset Reset Figure 31-15. ADC0 Control Registers (ADC0_CR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-26 Freescale Semiconductor Preliminary...
Page 922 ADC0_EN. Table 31-20. System Clock Divide Factor for ADC Clock System Clock ADC0_CLK_PS Divide Factor 0b00000 0b00001 0b00010 0b00011 0b00100 0b00101 0b00110 0b00111 0b01000 0b01001 0b01010 0b01011 0b01100 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-27 Preliminary...
Page 923 It determines at what frequency the time base counter will run. ADC_TSCR can be accessed by configuration commands sent to ADC0. Offset: 0x0002 Access: Read/Write TBC_CLK_PS Reset Figure 31-16. ADC Time Stamp Control Register (ADC_TSCR) MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-28 Freescale Semiconductor Preliminary...
Page 924 31.3.4.3 ADC Time Base Counter Registers (ADC_TBCR) The ADC_TBCR contains the current value of the time base counter. ADC_TBCR can be accessed by configuration commands sent to ADC0. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-29 Preliminary...
Page 925 GCC_INT.GCC_FRAC binary format. The integer part of the gain constant (GCC_INT) contains a single binary digit while its fractional part (GCC_FRAC) contains 14 digits. For details about the GCC data format refer to Section 31.4.5.4.2, “MAC Unit and Operand Data Format.” MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-30 Freescale Semiconductor Preliminary...
Page 926: Functional Description
The eQADC can also in parallel and independently of the CFIFOs receive data from the on-chip ADC into multiple RFIFOs. Result data is moved from the RFIFOs to the user-defined result queues in system memory by the host CPU or by the eDMA. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-31...
Page 927: Data Flow In The Eqadc
While conversion results are returned, the eQADC is checking the number of entries in the RFIFO and generating requests to empty it. The process of pushing and popping ADC results to and from an RFIFO can occur simultaneously. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-32 Freescale Semiconductor Preliminary...
Page 928 = 0, 1, 2, 3, 4, 5 Result Message Figure 31-21. Result Flow During eQADC Operation 31.4.1.1 Message Format in eQADC This section explains the command and result message formats used for on-chip ADC operation MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-33 Preliminary...
Page 929 The lower byte of conversion commands is always set to 0 to distinguish it from configuration commands. EOQ PAUSE Reserved MESSAGE_TAG CFIFO Header ADC Command CHANNEL_NUMBER ADC Command Figure 31-22. Conversion Command Message Format for On-Chip ADC Operation MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-34 Freescale Semiconductor Preliminary...
Page 930 0b1010 Reserved for customer use. 0b1011–0b1111 Reserved These messages are treated as null messages. Therefore, they must obey the format for incoming null messages and return valid BUSY0/1 fields. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-35 Preliminary...
Page 931 R/W bit. EOQ PAUSE Reserved ADC_REGISTER HIGH BYTE (0b0) CFIFO Header ADC Command ADC_REGISTER LOW BYTE ADC_REG_ADDRESS ADC Command Figure 31-23. Write Configuration Command Message Format for On-chip ADC Operation MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-36 Freescale Semiconductor Preliminary...
Page 932 ADC. A read configuration command is used to read the contents of the on-chip ADC registers which are only accessible via command messages. Read configuration commands are differentiated from write configuration commands by an asserted R/W bit. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-37...
Page 933 Buffer Number. Indicates which buffer the message will be stored in. 0 Message stored in buffer 0. 1 Message stored in buffer 1. Read/Write. An asserted R/W bit indicates a read configuration command. 0 Write 1 Read MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-38 Freescale Semiconductor Preliminary...
Page 934 2-bit left-shift on the 12-bit data received from the ADC. When the CAL bit is asserted, this 14-bit data is the result of the calculations performed in the EQADC MAC unit using the12-bit MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 935 0b11 when CONVERSION_RESULT is negative. CONVERSION Conversion Result. A digital value corresponding to the analog input voltage in a channel when the conversion _RESULT command was initiated. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-40 Freescale Semiconductor Preliminary...
Page 936: Command/Result Queues
CPU, is generated when CFFS is negated, and a eDMA request, served by the eDMA, is generated when CFFS is asserted. The host CPU or the eDMA respond to these requests MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 937 CFIFO. The transfer of entries bound for the on-chip ADC is considered completed when they are stored in the appropriate ADC command buffer. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-42...
Page 938 CFIFO with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. In this example, CFIFOn with 16 entries is shown in sequence after pushing and transferring entries. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-43...
Page 939 • Its commands are bound for an internal command buffer that is not full, and it is the highest priority triggered CFIFO sending commands to that buffer. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-44 Freescale Semiconductor Preliminary...
Page 940 ETRIG1, GPIO206, or GPIO207), an eTPU channel, or an eMIOS channel. The input source for each eQADC external trigger is individually specified in the eQADC trigger input select register (SIU_ETISR) in the SIU block. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-45...
Page 941 CFIFO to detect new trigger events, upon detection of an asserted EOQ bit in the last transfer. Refer to Section 31.4.1.1, “Message Format in eQADC,” for details about command formats. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-46 Freescale Semiconductor Preliminary...
Page 942 The EQADC_FISRn[SSS] bit (see Section 31.3.3.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)”) is negated. The SSS bit can be set even if a 1 is written to the MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-47 Preliminary...
Page 943 CFIFO to become triggered. For example, if rising-edge trigger mode is selected, the CFIFO becomes triggered when a rising edge is sensed on the trigger signal. The CFIFO MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-48...
Page 944 EOQ bit, the EOQF is set and, if enabled, an EOQ interrupt request is generated. The pause bit has no effect in continuous-scan software trigger mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-49...
Page 945 Start/Restart Condition Pause Condition Trigger Events? Single Scan Not Applicable Asserted SSS bit. None. Software Single Scan A corresponding edge None. Edge occurs when the SSS bit is asserted. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-50 Freescale Semiconductor Preliminary...
Page 946 The last CFIFO to transfer a command to an on-chip ADC can be read from the LCFTn (n=0,1) fields (see Section 31.3.3.10, “eQADC CFIFO Status Snapshot Register (EQADC_CFSSR).” MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-51 Preliminary...
Page 947 • No trigger occurred. TRIGGER (0b10) TRIGGERED • Appropriate edge or level trigger occurred, OR (0b11) • CFIFO mode is programmed to single-scan software trigger mode and SSS bit is asserted. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-52 Freescale Semiconductor Preliminary...
Page 948 In single-scan modes, command transfers from the corresponding CFIFO will cease when the eQADC completes the transfer of a entry with an asserted EOQ. Software involvement is required to rearm the CFIFO so that it can detect new trigger events. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-53...
Page 949 Section 31.3.3.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn)”). When EQADC_CFCRn[TORIE] (see Section 31.3.3.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn)”) and EQADC_FISRn[TORF] are asserted, the eQADC generates a trigger overrun interrupt request. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-54 Freescale Semiconductor Preliminary...
Page 950 CFIFO which sends commands to the same CBuffer. The NCF flag becomes asserted immediately after the first command transfer from the pre-empting CFIFO, that is the higher priority CFIFO, to the ADC in use is completed. See Figure 31-43. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-55 Preliminary...
Page 951: Result Fifos
• RFIFOn_BASE_ADDRESS is the smallest memory mapped address allocated to an RFIFOn entry. • RFIFO_DEPTH is the number of entries contained in a RFIFO - four in this implementation. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-56 Freescale Semiconductor Preliminary...
Page 952 RFIFO with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. In this example, RFIFOn with 16 entries is shown in sequence after popping or receiving entries. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-57...
Page 953 Stores the 16-bit data into the appropriate RFIFO if the MESSAGE_TAG indicates a valid RFIFO number or • Ignores the data in case of a null or “reserved for customer use” MESSAGE_TAG MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-58 Freescale Semiconductor Preliminary...
Page 954: On-Chip Adc Configuration And Control
(ADC0_CR)”) The ADC0_CLK_PS field selects the clock divide factor by which the system clock will be divided as showed in Table 31-20. The ADC clock frequency is calculated as below and it must not exceed 12 MHz. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-59 Preliminary...
Page 955 The time base counter can be reset by writing 0x0000 to the ADC_TBCR (Section 31.3.4.3, “ADC Time Base Counter Registers (ADC_TBCR)”) with a write configuration command. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-60 Freescale Semiconductor Preliminary...
Page 956 31.4.5.4.2 MAC Unit and Operand Data Format The MAC unit diagram is shown in Figure 31-36. Each on-chip ADC has a separate MAC unit to calibrate its conversion results. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-61 Preliminary...
Page 957 Fractional part of the gain calibration constant for ADC0. GCC_FRAC is the fractional part of the gain calibration FRAC constant (GCC) for ADC0. GCC_FRAC can expresses decimal values ranging from 0 to 0.999938... MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-62 Freescale Semiconductor...
Page 958 If the time prior to and during sampling is not long enough to permit this settling, then the voltage on the sample capacitors will not accurately represent the voltage to be read. This is a problem in particular when external muxes are used. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-63...
Page 959 (16-bits) Result Format Stamp ADC0_Result0 Logic Time Stamp0 Calibration Submodule TBC_CLK_PS Configuration Register Fields NOTE: n = 0, 1, 2, 3, 4, 5 Figure 31-38. On-Chip ADC Control Scheme MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-64 Freescale Semiconductor Preliminary...
Page 960: Internal/External Multiplexing
Channel Number in Input Pins CHANNEL_NUMBER Field Analog Other Conversion Type Binary Decimal Pin Name Functions AN0 to AN39 Single-ended 0000_0000 to 0010_0111 0 to 39 Single-ended 0010_1000 Single-ended 0010_1001 MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-65 Preliminary...
Page 961 0100_0xxx 64 to 71 — Single-ended 0100_1xxx 72 to 79 — Single-ended 0101_0xxx 80 to 87 — Single-ended 0101_1xxx 88 to 95 Reserved 0110_0000 to 1101_1111 96 to 223 MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-66 Freescale Semiconductor Preliminary...
Page 962 0 means pin is driven LOW and 1 that pin is driven HIGH. When the external multiplexed mode is selected, the eQADC automatically creates the MA output signals from CHANNEL_NUMBER field of a command message. The eQADC also converts the proper input MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-67...
Page 963 (ANR, ANS, ANT, ANW, ANX, ANY, and ANZ) by interpreting the CHANNEL_NUMBER field. As a result, up to 56 externally multiplexed channels appear to the conversion queues as directly connected signals. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-68 Freescale Semiconductor...
Page 964 AN87 AN88 Channel Control AN89 Number 0 Logic AN90 AN91 AN92 AN93 AN94 AN95 AN0-AN7 AN12-AN15 AN19-AN39 AN232-AN239 AN224-AN231 AN240-AN247 MA0-2 MA0-2 MA0-2 Figure 31-40. Example of External Multiplexing MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-69 Preliminary...
Page 965: Eqadc Edma/Interrupt Request
Writing 1 to the CFFFn bit is not allowed while CFDS = 1. CFFFn = 1 For details refer to Section 31.3.3.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn),” and Section 31.3.3.7, “eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn).” MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-70 Freescale Semiconductor Preliminary...
Page 966: Analog Submodule
The reference bypass capacitor (REFBYPC) signal requires a 100 nF capacitor connected to VRL to filter noise on the internal reference used by the ADC. REFBYPC 100nF Figure 31-42. Reference Bypass Circuit MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-71 Preliminary...
Page 967 12-bit digital output. Figure 31-44 shows the transfer function for the RSD stage. Note how the digital value (AB) is dependent on the two comparator inputs. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-72 Freescale Semiconductor Preliminary...
Page 968 The array, s1 to s12,will be the digital output of the RSD ADC with s1 being the msb and s12 being the lsb (least significant bit). Carry • • • • • • • • • • • • • • • • • • Figure 31-45. RSD Adder MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-73 Preliminary...
Page 969: Initialization/Application Information
Set CFFE0 to enable the eQADC to generate an eDMA request to transfer commands from Queue0 to CFIFO0; Command transfers from the RAM to the CFIFO0 will start immediately. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-74 Freescale Semiconductor...
Page 970 At the end of the command queue, the “EOQ” bit is asserted as shown in Table 31-42. c) Results will be returned to RFIFO3 as specified in the MESSAGE_TAG field of commands. 2. Reserve memory space for storing results. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-75 Preliminary...
Page 971 Set CFINV1 to invalidate the contents of CFIFO1. d) Set RFDE3 and CFFE1 to enable the eQADC to generate eDMA requests. Command transfers from the RAM to the CFIFO1 will start immediately. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-76 Freescale Semiconductor...
Page 972: Eqadc/Edma Controller Interface
(cyclic queue), or the first command of any other command queue. This is desirable for CFIFOs in continuous scan mode, or in some cases, for CFIFOs in single scan mode. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-77...
Page 973: Sending Immediate Command Setup Example
In the eQADC, there is no immediate command register for sending a command immediately after writing to that register. However, a CFIFO can be configured to perform the same function as an immediate MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-78...
Page 974: Modifying Queues
Since all result data may not have being stored in the appropriate RFIFO at the time MODEn is changed to disable, wait for all expected results to be stored in the RFIFO/result queue before MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 975: Command Queue And Result Queue Usage
0 command was sent to result queue 1. This happens because the system can be configured so that several command queues can have results sent to a single result queue. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-80...
Page 976: Adc Result Calibration
This allows for calculations of more representative calibration constants. The eQADC provides these voltages via channel numbers 43 and 44. VREF=V MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-81...
Page 977 Section 31.3.4.4, “ADC0 Gain Calibration Constant Register (ADC0_GCCR)”) and the OCC value to ADC0 offset calibration constant register (see Section 31.3.4.5, “ADC0 Offset Calibration Constant Register (ADC0_OCCR)”) using write configuration commands. MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-82 Freescale Semiconductor Preliminary...
Page 978 Section 31.4.5.4, “ADC Calibration Feature.” The maximum absolute quantization error is reduced by half leading to an increase in accuracy. 1. This calculation is rounded down due to binary approximation. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 31-83 Preliminary...
Page 979 (12-bit A/D Resolution) Quantization Error Error for Shifted Transfer Curve Input Voltage (12-bit A/D Resolution) –2 Error for ADC Transfer Curve –4 Figure 31-50. Quantization Error Reduction During Calibration threeand MPC5510 Microcontroller Family Reference Manual, Rev. 1 31-84 Freescale Semiconductor Preliminary...
Page 980 32.1 Introduction The MPC5510 boot assist module (BAM) is a 4-KB block of read-only memory (ROM) that contains the BAM program. The BAM program is compiled to variable length encoding (VLE) code. The BAM program is executed by the e200z1 when the MPC5510 performs a power-on-reset (POR), or any other reset, when the CRP_Z1VEC register remains in its reset state.
Page 981 The BAM ROM module occupies the last 16 KB of the MCU memory space; however, only the last 4 KB is physically present. NOTE Attempting to execute instructions from addresses in the range 0xFFFF_C000–0xFFFF_EFFF may cause unpredictable results. Some important absolute addresses are presented in Table 32-1. MPC5510 Microcontroller Family Reference Manual, Rev. 1 32-2 Freescale Semiconductor Preliminary...
Page 982 Nexus port is enabled or disabled, and whether the password downloaded in serial boot mode is compared to a fixed public password or to a user program- MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor...
Page 983 (0xFEED_FACE_CAFE_BEEF) or to a flash value stored in the shadow row of internal flash at address 0x00FF_FDD8. MPC5510 Microcontroller Family Reference Manual, Rev. 1 32-4 Freescale Semiconductor...
Page 984 Global PID Internal flash 0x0000_0000 0x0000_0000 256 MB Big Endian Global PID 0x2000_0000 0x2000_0000 256 MB Big Endian Global PID SRAM 0x4000_0000 0x4000_0000 256 KB Big Endian Global PID MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 32-5 Preliminary...
Page 985 The BOOT_BLOCK_ADDRESS used in the register descriptions below is the first address from Table 32-4 where the BAM finds a valid RCHW. Figure 32-3 shows the fields of the RCHW. Boot Identifier = 0x005A BOOT_BLOCK_ADDRESS + 0x0000_0000 Figure 32-3. RCHW Fields MPC5510 Microcontroller Family Reference Manual, Rev. 1 32-6 Freescale Semiconductor Preliminary...
Page 986 FlexCAN and eSCI modules. The CNTX_A pad is configured as an output from the FlexCAN module.The TXD_A pad remains configured as GPIO input until a valid eSCI byte is received before a valid CAN message. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 32-7...
Page 987 CAN Baud Rate Time-out Frequency (baud) (baud) period (MHz) (seconds) / 833 / 40 extal extal extal extal 9600 200K 16.8 14400 300K 11.2 19200 400K 24000 500K 48000 MPC5510 Microcontroller Family Reference Manual, Rev. 1 32-8 Freescale Semiconductor Preliminary...
Page 988 A message with 0x0012 ID and 8-byte length is used to send the start address, length, and the VLE mode bit. The MCU echoes with a message with 0x002 ID. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 32-9...
Page 989 The VLE mode bit instructs the MCU to program MMU pages with VLE attribute. If it is 1, the downloaded code must be compiled to VLE instructions, if it is 0 the code contains classic Power Book E architecture instructions. 3. Download data. MPC5510 Microcontroller Family Reference Manual, Rev. 1 32-10 Freescale Semiconductor Preliminary...
Page 990 NOTE In the MPC5510, the SRAM is protected by 32-bit wide error correction code (ECC), but other MPC55XX devices protect SRAM with 64-bit wide ECC. In the general case, this means any write to uninitialized SRAM must be 64 bits wide, otherwise an ECC error may occur.
Page 991 The BAM returns IO pins to their reset state and disables the ESCI_A module. Then it branches to the first address the data was stored to (as specified in step 2). MPC5510 Microcontroller Family Reference Manual, Rev. 1 32-12 Freescale Semiconductor Preliminary...
Page 992 SoftMLB concept and shows the functionality and interdependence on the other major blocks in the SoC. 1. A software driver for MLB emulation will be available from freescale. Available date - TBD MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 33-1...
Page 993 Multiple pin out options to increase flexibility • MLBCLK clock adjust • Visibility of debug signals 33.1.3 Modes of Operation The SoftMLB Interface Logic has two modes of operation: Normal mode and Stop mode MPC5510 Microcontroller Family Reference Manual, Rev. 1 33-2 Freescale Semiconductor Preliminary...
Page 994 MLB_SLOT MLB Slot Debug 5-pin & 3-pin PE5, PF6 MLB_SIGOBS MLB Clock Adjust Observe Signal Output 5-pin & 3-pin MLB_DATOBS MLB Clock Adjust Observe Data Output 5-pin & 3-pin MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 33-3 Preliminary...
Page 995 MLB_RXICHAR – RX Isochronous Channel Address Register 0x0000_0000 33.3.1.11/33-16 0x2C MLB_TXICHAR – TX Isochronous Channel Address Register 0x0000_0000 33.3.1.12/33-17 Note: Unimplemented locations always read 0. Writes to unimplemented locations have no effect. MPC5510 Microcontroller Family Reference Manual, Rev. 1 33-4 Freescale Semiconductor Preliminary...
Page 996 MLB Bus. MLB_MSR[MSYSS] = 1 indicates that the logic has synchronized. 0 Enable the SoftMLB Interface Logic 1 Disable the SoftMLB Interface Logic – Default out of reset bits 1–15 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 33-5 Preliminary...
Page 997 0 SoftMLB Interface Logic does not trigger an eDMA request (default out of reset) 1 SoftMLB Interface Logic does trigger an eDMA request every MLBDATA word (32 MLBCLK cycles) bits 23–24 Reserved. MPC5510 Microcontroller Family Reference Manual, Rev. 1 33-6 Freescale Semiconductor Preliminary...
Page 998 0 Active High (default out of reset) 1 Active Low 33.3.1.2 MLB Blank Register (MLB_MBR) The MLB_MBR register contains the blank request bit to cancel data that has been queued in the DSPI FIFO. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 33-7 Preliminary...
Page 999 MLB Module Status Register (MLB_MSR) The MLB_MSR contains the status bits that are used to determine detection of the system channel and status flags for service and eDMA requests. MPC5510 Microcontroller Family Reference Manual, Rev. 1 33-8 Freescale Semiconductor Preliminary...
Page 1000 MSVRQS will only be set after MSYSS is set. 0 Service request not active 1 Service request active 33.3.1.4 RX Control Channel Address Register (MLB_RXCCHAR) The MLB_RXCCHAR contains the RX Control Channel Address for this device. MPC5510 Microcontroller Family Reference Manual, Rev. 1 Freescale Semiconductor 33-9 Preliminary...