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4.36
SYSTEM CONTROL BLOCK DIAGRAM
0
5
CN3003
CAP
MDA
CAP_REV ( L )
6
M
CAP_CTL_V
3
CAP_FG
2
CON1
CN3001
DRUM_CTL_V
DRUM MOTOR
3
3
D.PG
2
4
D.FG
1
5
M
4
LOADING
MOTOR
5 5
CN3002
LDM2
M
2
LDM1
1
ROT
AR Y
CN3004
ENCODER
LSB
1
3
LSC
2
LSA
3
1 2
A/C
HEAD
A/C
HEAD
CN1
CN2001
CTL HEAD ( - )
2
6
CTL
CTL HEAD ( + )
1
7
V.
PULSE
VIDEO_ENV
TO
V/STD/HS1.FF
VIDEO/AUDIO
A/HS2.FF
2
H.REC_ST(H)
N.REC_ST(H)
TO
A.MUTE(H)
AUDIO I/O
CN3009
HS2_FF
9
HS1_FF
8
REF30
7
TO DIGITAL
REF5
6
(HOST)
HOST_RESET
5
CN7001
KBUS_REQ
4
KBUS_CLK
3
KBUS_DATA
1
1
For ADJ.
CN3010
RESET
2
FWE
3
SIO
5
SII
6
Note : For the waveforms in this block diagram, refer to page 4-67.
A
B
MAIN ( SYSCON, MAIN-TERMINAL )
3
WF1
WF2
WF3
PC3001
PHOTO
SENSOR
PC3002
IC3004
PHOTO
( LOADING MOTOR
SENSOR
VOLTAGE CONTROL )
2
9
LDM2
LMC1
4
7
LDM1
LMC2
1
DRIVE
VOL T
AGE
Vref
CONTROL
TP4001
Q3001
CTL.P
WF4
Q4002
ES
NOT
USED
A/HS2.FF
V/STD/HS1.FF
D3004
2
RESET
AL6V
IC3002
3
( RESET )
Q3013
ES
SIO
SII
C
D
IC3001
( SYSTEM CONTROL MICRO PROCESSOR )
65
X1
X3001
TIMER
64
(32KHz)
X2
69
X3002
OSC2 ( OUT )
MAIN
67
CLOCK
28
CAP REV ( L )
OSC1 ( IN )
(10MHz)
58
REC_SAFETY
48
S.CLK
101
46
CAPPWM
S.DATA TOSYS
8
47
CFG
S.DATA FRSYS
42
D_CASS(H)
13
END SENSOR
SENSOR
17
START SENSOR
102
SENSOR
DRUMPWM
49
I2C DATA
107
DPG
50
I2C CLK
108
DFG
56
S_CASS(H)
S3002
S.CASS
83
54
SP FG
HS_RECST(H)
18
HS2_ENV
41
55
D_REC_LEVEL2
TU FG
40
D_REC_LEVEL1
20
D_ENV/HS1_ENV
74
CH1_RECST(H)
36
81
LMC1
CH2_RECST(H)
37
LMC2
38
LMC3
6
CTLAMPOUT
93
2
EXP_DATA1
DATA
26
3
LSB
92
CLK
EXP_CLK
27
LSC
25
LSA
106
HI_S_FF_REW
94
EXP_DATA2
3
CTL ( - )
1
CTL ( + )
WF6
WF5
104
M.PULSE
110
V.PULSE
98
19
C. SYNC
VIDEO_ENV
100
D.FF/STD.FF/HS1.FF
99
A.FF/HS2.FF
87
H.REC_ST(H)
88
N.REC_ST(H)
89
A.MUTE(H)
95
2
EXP_DATA3
DATA
90
REF30
3
CLK
91
REF5
103
HOST_RESET
57
K-BUS-REQ
53
K-BUS-CLK
52
K-BUS-OUT
51
( SERIAL MEMORY )
K-BUS-IN
1
66
5
RES
6
76
I2C_DATA2
71
MODE
75
I2C_CLK2
62
FWE
E
4-69
4-70
CLOCK
SIO
SYSTEM
SII
CN3008
END
Q3003
I2C_DATA_A/V
START
I2C_CLK_A/V
Q3002
CN3011
A/HS2.FF
V/STD/HS1.FF
4
DRECL
5
DVHSL
6
HSH
10
INSELC
11
INSELB
12
INSELA
13
AV2TRH
14
ACTL1
15
FLYRECH
6
VMUTEH
IC3005
2
DATA
3
CLK
12
TRICK(H)
IC3006
CN7104
I2C_DATA_A/V
I2C_CLK_A/V
IC3007
CN7103
4
NRECL
5
VHSH
7
L1INF_A/AV1
9
L1INF_B
8
L2INF0/RGB
12
VUP2L
REG.
13
CONTROL
VUPH
14
P.CTLH
Q3006-Q3010
CN7105
15
P.SAVEL
IC3003
CN5601
SDA
SCL
I2C_CLK2
I2C_DATA2
F
REC_SAFETY
3
4
S_CLK
TO DISPLAY
S_DATA_TOSYS
5
CN7002
6
S_DATA_FRSYS
10
D_CASS_SW
I2C_DATA_A/V
I2C_CLK_A/V
TO
D_VHS(L)
VIDEO/AUDIO
FLY_REC(H)
N.REC(L)
VHS(H)
HS_RECST(H)
14
A/HS2.FF
13
HS2_ENV
12
D_REC_LEVEL2
11
D_REC_LEVEL1
8
TO DIGITAL
D/HS1_ENV
7
(PRE/REC)
V/STD/HS1.FF
6
CN605
CH1_RECST(H)
5
CH2_RECST(H)
4
D_REC(L)
3
2
D_VHS(L)
HS(H)
1
A.IN_SEL_C
A.IN_SEL_B
TO
A.IN_SEL_A
AUDIO I/O
AV2THROUGH(L)
AUDIO_CTL1
TO
YU_V_MUTE(H)
TUNER
16
TRICK(H)
C.SYNC/V.REF
TO 3D DIGITAL/4M
14
I2C_DATA_A/V
CN1401
12
I2C_CLK_A/V
11
I2C_DATA_A/V
TO S-SUB
2
3
I2C_CLK_A/V
CN511
TO TERMINAL
LINE1INF0/I2C_DATA2
13
CN7102
LINE2INF0/I2C_CLK2
14
4
P.CTL(H)
TO SUB REG
P.SAVE(L)
3
CN5503
TO
I2C_DATA2
SYNC-DET/PDC
I2C_CLK2
G
H
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