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14
10.8.
Test 5 (Counter
and
counter
input control
test).
Settings signature analyser
Setting
Edge
Testpoint
Signalname
start
(neg)
TP14
P17
stop
J'
(pos)
TP14
P17
clock
if
(pos)
TP15
ALE
ground
—
TP1
logic
0
NOTE:
1.
Testrom placed
in
D
1909
socket (Both
ROMs
removed)
2.
Short
circuit
TP
10
and
TP
11
3.
Reading on
display:
L5
4.
Connect
point
1
of
D1910
to logic
0
5.
Adjust
with
R502
the signature
on
D
19
11
point
2
to
0000
6.
Select the signature
on
point 15 of
D
1903
with
the
+/—
button:
154H
7.
Reference
logic
0
=
0000
logic
1
=3UH7
[A
-
CLOCK AOC
s
01
IJ
C'<
L^3niAn.'\j
-1
I
'
=
JCI903
.
IToop
f
4
.11. .1.1
-
Sracii
ADC
u
R
'
IALEI
*0000
ICT/ADCPIOl
{
PFFQ
IaZC/P
PISI
COUNTER
INPUT
CONTROL
f
®
Ni
anaI
*—£2!dE_
ll3
0000
fC
nianaI
.
L7
J
»0000
LOGIC
0
=
0000
LOGIC
1
=
3UH7
'Apigii
74LS86
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