Page 1 Hitachi 16 Bit Single-Chip Microcomputer H8S/2378, H8S/2378R Series H8S/2377R F-ZTAT™ HD64F2377R H8S/2376R F-ZTAT™ HD64F2376R H8S/2377 F-ZTAT™ HD64F2377 H8S/2376 F-ZTAT™ HD64F2376 Hardware Manual ADE-602-260 Rev. 1.0 9/25/01 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are not connected to any of the internal circuitry; they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 4 Configuration of this Manual This manual comprises the following items: 1. Precautions in Relation to this Product 2. Configuration of this Manual 3. Overview 4. Table of Contents 5. Summary 6. Description of Functional Modules • CPU and System-Control Modules •...
Page 5 This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2378 Series in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Page 6 ADE No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor ADE-702-247 User's Manual H8S, H8/300 Series Simulator/Debugger User’s Manual ADE-702-037 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging ADE-702-231 Interface Tutorial Hitachi Embedded Workshop User's Manual ADE-702-201 Application note: Manual Title ADE No.
Page 7: Table Of Contents
Contents Section 1 Overview................... 1 Features ..........................1 Block Diagram ........................2 Pin Description........................3 1.3.1 Pin Arrangement ....................3 1.3.2 Pin Arrangement in Each Operating Mode ............4 1.3.3 Pin Functions......................10 Section 2 CPU....................17 Features ..........................17 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ........18 2.1.2 Differences from H8/300 CPU................19 2.1.3...
Page 8 Processing States.......................50 Usage Notes ........................51 2.9.1 Note on Bit Manipulation Instructions..............51 Section 3 MCU Operating Modes ..............53 Operating Mode Selection....................53 Register Descriptions ......................54 3.2.1 Mode Control Register (MDCR) .................54 3.2.2 System Control Register (SYSCR) ..............54 Operating Mode Descriptions ...................56 3.3.1 Mode 1 .........................56 3.3.2 Mode 2 .........................56...
Page 9 5.3.7 Software Standby Release IRQ Enable Register (SSIER) ........88 Interrupt Sources .......................88 5.4.1 External Interrupts....................88 5.4.2 Internal Interrupts....................89 Interrupt Exception Handling Vector Table ..............90 Interrupt Control Modes and Interrupt Operation .............95 5.6.1 Interrupt Control Mode 0 ..................95 5.6.2 Interrupt Control Mode 2 ..................97 5.6.3 Interrupt Exception Handling Sequence ..............98 5.6.4...
Page 10 6.5.2 Valid Strobes......................143 6.5.3 Basic Timing ......................143 6.5.4 Wait Control......................150 Read Strobe ( RD ) Timing ..................153 6.5.5 Extension of Chip Select ( CS ) Assertion Period..........154 6.5.6 DRAM Interface .......................155 6.6.1 Setting DRAM Space...................155 6.6.2 Address Multiplexing...................156 6.6.3 Data Bus.......................157 6.6.4 Pins Used for DRAM Interface................158 6.6.5...
Page 11 6.10 Write Data Buffer Function....................230 6.11 Bus Release ........................231 6.11.1 Operation......................231 6.11.2 Pin States in External Bus Released State............233 6.11.3 Transition Timing ....................234 6.12 Bus Arbitration........................236 6.12.1 Operation......................236 6.12.2 Bus Transfer Timing ....................236 6.13 Bus Controller Operation in Reset ..................238 6.14 Usage Notes ........................238 6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode .....238 6.14.2 External Bus Release Function and Software Standby ........238...
Page 12 7.5.12 Multi-Channel Operation ..................307 7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and EXDMAC .....................308 7.5.14 DMAC and NMI Interrupts..................309 7.5.15 Forced Termination of DMAC Operation............309 7.5.16 Clearing Full Address Mode ................310 Interrupt Sources .......................311 Usage Notes ........................312 7.7.1 DMAC Register Access during Operation............312 7.7.2...
Page 13 8.6.2 Module Stop State ....................376 EDREQ Pin Falling Edge Activation..............376 8.6.3 8.6.4 Activation Source Acceptance ................376 8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR........377 ETEND Pin and CBR Refresh Cycle ..............377 8.6.6 Section 9 Data Transfer Controller (DTC) ............379 Features ..........................379 Register Configuration ......................380 9.2.1...
Page 14 10.1 Port 1..........................408 10.1.1 Port 1 Data Direction Register (P1DDR) .............408 10.1.2 Port 1 Data Register (P1DR)................408 10.1.3 Port 1 Register (PORT1)..................409 10.1.4 Pin Functions .......................409 10.2 Port 2..........................419 10.2.1 Port 2 Data Direction Register (P2DDR) .............419 10.2.2 Port 2 Data Register (P2DR)................419 10.2.3 Port 2 Register (PORT2)..................420 10.2.4 Pin Functions .......................421 10.3 Port 3..........................429...
Page 15 10.9.5 Port A Open Drain Control Register (PAODR) ...........456 10.9.6 Port Function Control Register 1 (PFCR1) ............456 10.9.7 Pin Functions......................458 10.9.8 Port A MOS Input Pull-Up States ................459 10.10 Port B ..........................460 10.10.1 Port B Data Direction Register (PBDDR)............460 10.10.2 Port B Data Register (PBDR)................461 10.10.3 Port B Register (PORTB)..................461 10.10.4 Port B MOS Pull-Up Control Register (PBPCR)..........462 10.10.5 Pin Functions......................462...
Page 16 10.16 Port H ..........................488 10.16.1 Port H Data Direction Register (PHDDR) ............488 10.16.2 Port H Data Register (PHDR) ................490 10.16.3 Port H Register (PORTH) ..................490 10.16.4 Pin Functions .......................491 Section 11 16-Bit Timer Pulse Unit (TPU) ............493 11.1 Features ..........................493 11.2 Input/Output Pins ......................497 11.3 Register Descriptions ......................498 11.3.1 Timer Control Register (TCR) ................499...
Page 17 11.10.10 Contention between Buffer Register Write and Input Capture ......568 11.10.11 Contention between Overflow/Underflow and Counter Clearing ....569 11.10.12 Contention between TCNT Write and Overflow/Underflow ......570 11.10.13 Multiplexing of I/O Pins ..................570 11.10.14 Interrupts and Module Stop Mode ..............570 Section 12 Programmable Pulse Generator (PPG) ........... 571 12.1 Features ..........................571 12.2 Input/Output Pins ......................573 12.3 Register Descriptions ......................573...
Page 18 13.5.3 Timing of Timer Output when Compare-Match Occurs........601 13.5.4 Timing of Compare Match Clear .................602 13.5.5 Timing of TCNT External Reset................602 13.5.6 Timing of Overflow Flag (OVF) Setting .............603 13.6 Operation with Cascaded Connection ................603 13.6.1 16-Bit Counter Mode ...................603 13.6.2 Compare Match Count Mode................604 13.7 Interrupts ...........................604 13.7.1 Interrupt Sources and DTC Activation..............604...
Page 19 15.3.2 Receive Data Register (RDR) ................630 15.3.3 Transmit Data Register (TDR) ................630 15.3.4 Transmit Shift Register (TSR) ................630 15.3.5 Serial Mode Register (SMR)................630 15.3.6 Serial Control Register (SCR)................633 15.3.7 Serial Status Register (SSR).................638 15.3.8 Smart Card Mode Register (SCMR) ..............645 15.3.9 Bit Rate Register (BRR)..................646 15.3.10 IrDA Control Register (IrCR) ................655 15.3.11 Serial Extension Mode Register (SEMR) ............656...
Page 20 15.10.2 Break Detection and Processing................701 15.10.3 Mark State and Break Sending................701 15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)..............701 15.10.5 Relation between Writes to TDR and the TDRE Flag .........701 15.10.6 Restrictions on Use of DMAC or DTC ..............702 15.10.7 Operation in Case of Mode Transition..............702 Section 16 I C Bus Interface2 (IIC2) (Option) ............707...
Page 21 17.4.4 External Trigger Input Timing ................746 17.5 Interrupts ...........................747 17.6 A/D Conversion Precision Definitions................747 17.7 Usage Notes ........................749 17.7.1 Module Stop Mode Setting ..................749 17.7.2 Permissible Signal Source Impedance ..............749 17.7.3 Influences on Absolute Precision.................749 17.7.4 Setting Range of Analog Power Supply and Other Pins ........750 17.7.5 Notes on Board Design ..................750 17.7.6 Notes on Noise Countermeasures ................750 Section 18 D/A Converter.................
Page 22 20.9 Program/Erase Protection....................788 20.9.1 Hardware Protection ....................788 20.9.2 Software Protection....................788 20.9.3 Error Protection....................788 20.10 Programmer Mode ......................789 20.11 Power-Down States for Flash Memory ................789 20.12 Usage Notes ........................789 Section 21 Clock Pulse Generator ..............793 21.1 Register Description......................793 21.1.1 System Clock Control Register (SCKCR) ............793 21.1.2 PLL Control Register (PLLCR) ................795 21.2 Oscillator...........................795 21.2.1 Connecting a Crystal Oscillator ................796...
Page 23 Section 23 List of Registers ................815 23.1 Register Addresses (Address Order) .................815 23.2 Register Bits ........................827 23.3 Register States in Each Operating Mode................841 Section 24 Electrical Characteristics ..............851 24.1 Absolute Maximum Ratings....................851 24.2 DC Characteristics......................852 24.3 AC Characteristics......................855 24.3.1 Clock Timing .......................856 24.3.2 Control Signal Timing ..................858 24.3.3 Bus Timing......................860...
Page 24 Rev. 1.0, 09/01, page xxiv of xliv...
Page 25: Overview
Figures of Contents Section 2 Overview Figure 1.1 Internal Block Diagram ....................2 Figure 1.2 Pin Arrangement......................3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) ..............21 Figure 2.2 Stack Structure in Normal Mode .................21 Figure 2.3 Exception Vector Table (Advanced Mode) ..............22 Figure 2.4 Stack Structure in Advanced Mode ................23 Figure 2.5 Memory Map .......................24 Figure 2.6 CPU Internal Registers ....................25...
Page 26 Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access)..........128 Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) ....131 Figure 6.6 Area Divisions ......................136 Figure 6.7 CSn Signal Output Timing (n = 0 to 7) ..............141 Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)......142 Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space) ......142 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space ............144...
Page 27 Figure 6.41 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 (RAST = 0, CAST = 0) ...................178 Figure 6.42 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 (RAST = 0, CAST = 1) ....................179 Figure 6.43 Relationship between φ...
Page 28 Figure 6.72 Example of Synchronous DRAM Full Access after External Read (CAS Latency 2) ......................219 Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 0, CAS Latency 2)..................220 Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area) (IDLC = 1, CAS Latency 2)..................221 Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode (Write after Read) (IDLC = 0, CAS Latency 2)..................222...
Page 29 Figure 7.16 Example of Block Transfer Mode Setting Procedure ..........291 Figure 7.17 Example of DMA Transfer Bus Timing ..............292 Figure 7.18 Example of Short Address Mode Transfer ..............293 Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)...........294 Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ..........295 Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)......296 Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer ....297 Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer ..298...
Page 30 Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer........350 Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer......350 Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge ..351 Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge ......................352 Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level.....353 Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level.354...
Page 31 Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) .......369 Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) ......370 Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing) ..371 Figure 8.45 Transfer End Interrupt Logic ...................374 Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which...
Page 32 Figure 11.20 Example of PWM Mode Setting Procedure ............545 Figure 11.21 Example of PWM Mode Operation (1) ..............546 Figure 11.22 Example of PWM Mode Operation (2) ..............546 Figure 11.23 Example of PWM Mode Operation (3) ..............547 Figure 11.24 Example of Phase Counting Mode Setting Procedure ...........548 Figure 11.25 Example of Phase Counting Mode 1 Operation ............549 Figure 11.26 Example of Phase Counting Mode 2 Operation ............550 Figure 11.27 Example of Phase Counting Mode 3 Operation ............551...
Page 33 Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) ....587 Figure 12.10 Inverted Pulse Output (Example) ................588 Figure 12.11 Pulse Output Triggered by Input Capture (Example) ..........589 Section 13 8-Bit Timers (TMR) Figure 13.1 Block Diagram of 8-Bit Timer Module ..............592 Figure 13.2 Example of Pulse Output ..................600 Figure 13.3 Count Timing for Internal Clock Input..............600 Figure 13.4 Count Timing for External Clock Input..............601...
Page 34 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ........674 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ........675 Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First) ....676 Figure 15.15 Sample SCI Initialization Flowchart..............677 Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ....679 Figure 15.17 Sample Serial Transmission Flowchart ..............680 Figure 15.18 Example of SCI Operation in Reception ...............681 Figure 15.19 Sample Serial Reception Flowchart...............682...
Page 35 Figure 16.12 Slave Receive Mode Operation Timing 2..............728 Figure 16.13 Block Diagram of Noise Conceler.................729 Figure 16.14 Sample Flowchart for Master Transmit Mode............730 Figure 16.15 Sample Flowchart for Master Receive Mode ............731 Figure 16.16 Sample Flowchart for Slave Transmit Mode ............732 Figure 16.17 Sample Flowchart for Slave Receive Mode............733 Figure 16.18 Timing of the Bit Synchronous Circuit..............735 Section 17 A/D Converter...
Page 36: Electrical Characteristics
Figure 22.2 Software Standby Mode Application Example............811 Figure 22.3 Hardware Standby Mode Timing ................812 Section 24 Electrical Characteristics Figure 24.1 Output Load Circuit....................855 Figure 24.2 System Clock Timing ....................856 Figure 24.3 SDRAM φ Timing* ....................857 Figure 24.4 (1) Oscillation Stabilization Timing ................857 Figure 24.4 (2) Oscillation Stabilization Timing ................858 Figure 24.5 Reset Input Timing ....................859 Figure 24.6 Interrupt Input Timing .....................859...
Page 37 Figure 24.40 WDT Output Timing .....................888 Figure 24.41 SCK Clock Input Timing..................888 Figure 24.42 SCI Input/Output Timing: Synchronous Mode............888 Figure 24.43 A/D Converter External Trigger Input Timing ............889 Figure 24.44 I C Bus Interface Input/Output Timing (Option)...........889 Rev. 1.0, 09/01, page xxxvii of xliv...
Page 38 Rev. 1.0, 09/01, page xxxviii of xliv...
Page 39 Tables of Contents Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ..............4 Table 1.2 Pin Functions.......................10 Section 2 CPU Table 2.1 Instruction Classifcation....................33 Table 2.2 Operation Notation......................34 Table 2.3 Data Transfer Instructions...................35 Table 2.4 Arithmetic Operations Instructions (1) ...............36 Table 2.4 Arithmetic Operations Instructions (2) ...............37 Table 2.5...
Page 40 Table 6.6 DRAM Interface Pins....................158 Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM Space ......................180 Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing..181 Table 6.9 Synchronous DRAM Interface Pins................183 Table 6.10 Setting CAS Latency.....................186 Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM...
Page 41 Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.1 TPU Functions ......................494 Table 11.2 Pin Configuration ....................497 Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3)..............501 Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)............501 Table 11.5 TPSC2 to TPSC0 (Channel 0)................502 Table 11.6 TPSC2 to TPSC0 (Channel 1)................502 Table 11.7...
Page 42 Table 13.4 Timer Output Priorities ..................608 Table 13.5 Switching of Internal Clock and TCNT Operation ..........610 Section 14 Watchdog Timer Table 14.1 WDT Pin .......................614 Table 14.2 WDT Interrupt Source ..................620 Section 15 Serial Communication Interface (SCI, IrDA) Table 15.1 Pin Configuration....................628 Table 15.2 Relationships between N Setting in BRR and Bit Rate B ........646...
Page 43 Section 20 Flash Memory (F-ZTAT Version) Table 20.1 Differences between Boot Mode and User Program Mode........767 Table 20.2 Pin Configuration ....................772 Table 20.3 Erase Blocks......................775 Table 20.4 Setting On-Board Programming Modes..............778 Table 20.5 Boot Mode Operation....................780 Table 20.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible .........................780 Table 20.7 Flash Memory Operating States ................789...
Page 44 Rev. 1.0, 09/01, page xliv of xliv...
Page 45: Section 1 Overview
Section 1 Overview Features High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions Various peripheral functions DMA controller (DMAC) EXDMA controller (EXDMAC) Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG)
Page 46: Block Diagram
Block Diagram Port D Port E PA7/A23/ PA6/A22/ DCTL PA5/A21/ EXTAL PA4/A20/ XTAL PA3/A19 EMLE PA2/A18 PA1/A17 H8S/2000 CPU PA0/A16 Clock PB7/A15 pulse PB6/A14 generator PB5/A13 PB4/A12 PF7/øF Interrupt controller PB3/A11 PF6/ PB2/A10 PF5/ PB1/A9 PF4/ PB0/A8 PF3/ DMAC PC7/A7 PF2/ /DQML PC6/A6...
Page 47: Pin Description
Pin Description 1.3.1 Pin Arrangement PG2/ PG3/ PE7/D7 AVcc Vref PE6/D6 P40/AN0 PE5/D5 P41/AN1 PE4/D4 P42/AN2 PE3/D3 P43/AN3 PE2/D2 P44/AN4 PE1/D1 P45/AN5 PE0/D0 P46/AN6/DA0 DCTL P47/AN7/DA1 P85/( )/SCK3/ P90/AN8 P84/( P91/AN9 P83/( )/RXD3/ P92/AN10 P27/PO7/TIOCB5/( P93/AN11 P26/PO6/TIOCA5/( P94/AN12/DA2 P25/PO5/TIOCB4/( P95/AN13/DA3 LQFP-144 P24/PO4/TIOCA4/RXD4/( P96/AN14/DA4...
Page 48: Pin Arrangement In Each Operating Mode
1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode P80/(I RQ 0)/ P80/(I RQ 0)/ P80/(I RQ 0)/ P80/(I RQ 0)/...
Page 49 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode A20/I RQ 4 A20/I RQ 4 PA4/A20/I RQ 4 PA4/A20/I RQ 4 PA4/I RQ 4 PA5/A21/I RQ 5 PA5/A21/I RQ 5 PA5/A21/I RQ 5 PA5/A21/I RQ 5...
Page 50 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ TIOCB2/TCLKD/ED TIOCB2/TCLKD/ED TIOCB2/TCLKD/ED TIOCB2/TCLKD/ED TIOCB2/TCLKD/ED RA K 3 RA K 3 RA K 3 RA K 3 RA K 3...
Page 51 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode PE5/D5 PE5/D5 PE5/D5 PE6/D6 PE6/D6 PE6/D6 PE7/D7 PE7/D7 PE7/D7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 P60/TMRI0/ P60/TMRI0/...
Page 52 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode XTAL XTAL XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL STBY STBY STBY STBY STBY P63/TMCI1/ P63/TMCI1/...
Page 53 Pin Name Mode 7 Flash Memory Programmer Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0 Mode P93/AN11 P93/AN11 P93/AN11 P93/AN11 P93/AN11 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P94/AN12/DA2 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P95/AN13/DA3 P96/AN14/DA4 P96/AN14/DA4 P96/AN14/DA4 P96/AN14/DA4...
Page 54: Pin Functions
1.3.3 Pin Functions Table 1.2 Pin Functions Type Symbol Pin No. Function Power 4, 41, 72, Input For connection to the power supply. V pins should 98, 99 be connected to the system power supply. 2, 10, 18, Input For connection to ground. V pins should be 25, 50, 70, connected to the system power supply (0 V).
Page 55 Type Symbol Pin No. Function Address bus A23 to A0 31 to 26, Output These pins output an address. 24 to 19, 17 to 11, 9 to 5 Data bus D15 to 80 to 73, Input/ These pins constitute a bidirectional data bus. output 69 to 63 Bus control...
Page 56 Type Symbol Pin No. Function Bus control 109, 110, Output Row address strobe signal for the synchronous RA S/RA S 35, 36 DRAM interface. RA S3 to RA S signal is a row address strobe signal when RA S5 areas 2 to 5 are set to the continuous DRAM space. Output Row address strobe signal for the synchronous RA S DRAM of the synchronous DRAM interface.
Page 57 Type Symbol Pin No. Function EXDMA Output These signals indicate the end of EXDMAC data ETEN D 3, controller transfer. ETEN D 2 (EXDMAC) Output EXDMAC single address transfer acknowledge ED A CK 3, signals. ED A CK 2 Output These signals notify an external device of ED RA K 3, acceptance and start of execution of a DMA transfer ED RA K 2...
Page 58 Type Symbol Pin No. Function Serial commu- TxD4 Output Data output pins. nication TxD3 interface TxD2 133, (SCI)/smart TxD1 141, card interface TxD0/ (SCI_0 with IrTxD IrDA function) RxD4 Input Data input pins. RxD3 RxD2 134, RxD1 139, RxD0/ IrRxD SCK4 138, Input/...
Page 59 Type Symbol Pin No. Function I/O ports P17 to 49 to 42 Input/ Eight-bit input/output pins. output P27 to 58 to 51 Input/ Eight-bit input/output pins. output P35 to 137 to 142 Input/ Six-bit input/output pins. output P47 to 120 to 113 Input Eight-bit input pins.
Page 60 Rev. 1.0, 09/01, page 16 of 904...
Page 61: Section 2 Cpu
Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU.
Page 62: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
• Two CPU operating modes  Normal mode*  Advanced mode Note: For this LSI, normal mode is not available. • Power-down state  Transition to power-down state by SLEEP instruction  Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Page 63: Differences From H8/300 Cpu
2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added.
Page 64: Cpu Operating Modes
CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode.
Page 65: Advanced Mode
H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 Exception H'0007 vector table H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode) EXR* (16 bits) Reserved* SP *...
Page 66 • Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3).
Page 67 EXR* Reserved Reserved* (24 bits) (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack. SP when EXR is not used. Ignored when returning. Figure 2.4 Stack Structure in Advanced Mode Rev.
Page 68: Address Space
Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 69: Register Configuration
Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers...
Page 70: General Registers
2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 71: Program Counter (Pc)
Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
Page 72: Condition-Code Register (Ccr)
2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 73 Bit Name Initial Value R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller.
Page 74: Initial Register Values
2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized.
Page 75 Data Type Register Number Data Image Word data Word data Longword data Legend : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
Page 76: Memory Data Formats
2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 77: Instruction Set
Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classifcation Function Instructions Size Types Data transfer B/W/L POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG B/W/L...
Page 78: Table Of Instructions Classified By Function
2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register) (EAd)
Page 79 Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in this LSI. MOVTPE Cannot be used in this LSI.
Page 80 Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes.
Page 81 Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 82 Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 83 Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 84 Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
Page 85 Table 2.8 Branch Instructions Instruction Size Function – Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 86 Table 2.9 System Control Instructions Instruction Size* Function TRAPA – Starts trap-instruction exception handling. – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR.
Page 87: Basic Instruction Formats
Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B – Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: if R4 ≠ 0 then EEPMOV.W – Repeat @ER5+ → @ER6+ R4–1 →...
Page 88: Addressing Modes And Effective Address Calculation
(1) Operation field only NOP, RTS (2) Operation field and register fields ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples) Addressing Modes and Effective Address Calculation...
Page 89: Register Direct-Rn
2.7.1 Register Direct—Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the...
Page 90: Immediate-#Xx:8, #Xx:16, Or #Xx:32
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Normal Mode Advanced Mode Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16)
Page 91: Memory Indirect-@@Aa:8
In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area.
Page 92 Table 2.13 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct (Rn) Operand is general register contents. Register indirect (@ERn) General register contents General register contents Sign extension Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ General register contents...
Page 93 Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. Program-counter relative @(d:8,PC)/@(d:16,PC) PC contents Sign extension Memory indirect @@aa:8 • Normal mode* Memory contents •...
Page 94: Processing States
Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the 5(6 input goes low, all current processing stops and the CPU enters the reset state.
Page 95: Usage Notes
End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Exception Software standby handling state mode = High = High, = Low Hardware standby Reset state mode Reset state Power down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever goes low.
Page 96 Rev. 1.0, 09/01, page 52 of 904...
Page 97: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Operating Mode Selection The H8S/2378 Series has seven operating modes (modes 1 to 7). For each operating mode, pins are given with different functions. An operating mode is selected by the setting of mode pins (MD2 to MD0).
Page 98: Register Descriptions
Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of the H8S/2378 Series chip. Bit Name Initial Value Descriptions −...
Page 99 Bit Name Initial Value Descriptions − Reserved − The initial value should not be modified. − Reserved − The initial value should not be modified. FLSHE Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). If this bit is set to 1, the flash memory control registers can be read/written to.
Page 100: Operating Mode Descriptions
Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of ports F, G, and H carry bus control signals.
Page 101: Mode 6
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of ports F, G and H carry bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. The program in an external ROM connected to the first half of area 0 is executed.
Page 102: Pin Functions
3.3.8 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Mode Mode Mode Mode Mode Mode Mode Port Port A PA7 to PA4 to Port B Port C Port D Port E Port F PF7,...
Page 103: Memory Map In Each Operating Mode
Memory Map in Each Operating Mode Figures 3.1 to 3.4 show memory maps for each product. Mode 1 and 2 Mode 3 Mode 4 (Expanded mode with (Boot mode) (Expanded mode with on-chip ROM disabled) on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM...
Page 104 Mode 7 Mode 5 and 6 (External ROM activatin (Single-chip activation expanded mode, expanded mode, with on-chip enabled) with on-chip ROM enabled) H'000000 H'000000 External address External adderss space space H'060000 H'100000 On-chip ROM External address space/ reserved area H'160000 External address space H'FF4000...
Page 105 Mode 1 and 2 Mode 3 Mode 4 (Expanded mode with (Boot mode) (Expanded mode with on-chip ROM disabled) on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External address space H'060000 H'060000 External address External address space/ space Reserved area H'FF4000 H'FF4000...
Page 106 Mode 5 and 6 Mode 7 (External ROM activation (Single-chip activation expanded mode, expanded mode, with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 On-chip RAM External address space H'060000 H'100000 On-chip RAM External address space/ reserved area H'160000 External address space H'FF8000...
Page 107: Section 4 Exception Handling
Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 108 Table 4.2 Exception Handling Vector Table Vector Address* Exception Source Vector Number Normal Mode* Advanced Mode Power-on reset H'0000 to H'0001 H'0000 to H'0003 Manual reset * H'0002 to H'0003 H'0004 to H'0007 Reserved for system use H'0004 to H'0005 H'0008 to H'000B H'0006 to H'0007 H'000C to H'000F...
Page 109: Reset
Vector Address* Exception Source Vector Number Normal Mode* Advanced Mode Internal interrupt* H'0040 to H'0041 H'0080 to H'0083    H'00EC to H'00ED H'01D8 to H'01DB Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3.
Page 110 Prefetch of first Internal Vector fetch program instruction processing φ Internal address bus Internal read signal Internal write High signal Internal data (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
Page 111: Interrupts After Reset
Internal Prefetch of first processing program instruction Vector fetch Address bus High D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted.
Page 112: Traces
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
Page 113: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack.
Page 114: Stack Status After Exception Handling
Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes Reserved* CCR* CCR* PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes Reserved* PC (24 bits)
Page 115: Usage Notes
Usage Notes When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
Page 116 Rev. 1.0, 09/01, page 72 of 904...
Page 117: Section 5 Interrupt Controller
Section 5 Interrupt Controller Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
Page 118 A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 INTCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority SSIER ITSR ISCR determination Internal interrupt sources I2 to I0 SWDTEND to IICI1 Interrupt controller...
Page 119: Input/Output Pins
Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name Function Input Nonmaskable external interrupt Rising or falling edge can be selected. ,5448 to ,543 Input Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected.
Page 120: Interrupt Control Register (Intcr)
5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Name Initial Value Description − − Reserved − − These bits are always read as 0 and cannot be modified. INTM1 Interrupt Control Select Mode 1 and 0 INTM0 These bits select either of two interrupt control modes for the interrupt controller.
Page 121 Bit Name Initial Value Description − − Reserved This bit is always read as 0 and cannot be modified. IPR14 Sets the priority of the corresponding interrupt IPR13 source. IPR12 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5...
Page 122: Irq Enable Register (Ier)
Bit Name Initial Value Description − − Reserved This bit is always read as 0 and cannot be modified. IPR2 Sets the priority of the corresponding interrupt IPR1 source. IPR0 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5...
Page 123 Bit Name Initial Value Description IRQ9E IRQ9 Enable The IRQ9 interrupt request is enabled when this bit is 1. IRQ8E IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. IRQ7E IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1.
Page 124: Irq Sense Control Registers H And L (Iscrh, Iscrl)
5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins ,5448 to ,543. • ISCRH Bit Name Initial Value Description IRQ15SCB IRQ15 Sense Control B IRQ15SCA IRQ15 Sense Control A 00: Interrupt request generated at ,5448 input low level 01: Interrupt request generated at falling edge...
Page 125 Bit Name Initial Value Description IRQ12SCB IRQ12 Sense Control B IRQ12SCA IRQ12 Sense Control A 00: Interrupt request generated at ,5445 input low level 01: Interrupt request generated at falling edge of ,5445 input 10: Interrupt request generated at rising edge of ,5445 input 11: Interrupt request generated at both falling and rising edges of ,5445 input...
Page 126 Bit Name Initial Value Description IRQ8SCB IRQ8 Sense Control B IRQ8SCA IRQ8 Sense Control A 00: Interrupt request generated at ,54; input low level 01: Interrupt request generated at falling edge of ,54; input 10: Interrupt request generated at rising edge of ,54;...
Page 127 Bit Name Initial Value Description IRQ5SCB IRQ5 Sense Control B IRQ5SCA IRQ5 Sense Control A 00: Interrupt request generated at ,548 input low level 01: Interrupt request generated at falling edge of ,548 input 10: Interrupt request generated at rising edge of ,548 input 11: Interrupt request generated at both falling and rising edges of ,548 input...
Page 128 Bit Name Initial Value Description IRQ2SCB IRQ2 Sense Control B IRQ2SCA IRQ2 Sense Control A 00: Interrupt request generated at ,545 input low level 01: Interrupt request generated at falling edge of ,545 input 10: Interrupt request generated at rising edge of ,545 input 11: Interrupt request generated at both falling and rising edges of ,545 input...
Page 129: Irq Status Register (Isr)
5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit Name Initial Value Description IRQ15F R/(W)* [Setting conditions] IRQ14F R/(W)* When the interrupt source selected by ISCR IRQ13F R/(W)* occurs IRQ12F R/(W)* [Clearing conditions] IRQ11F R/(W)* •...
Page 130: Irq Pin Select Register (Itsr)
5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins ,5448 to ,543. Bit Name Initial Value Description Selects ,5448 input pin. ITS15 0: PF2 1: P27 Selects ,5447 input pin. ITS14 0: PF1 1: P26 Selects ,5446 input pin. ITS13 0: P65 1: P25...
Page 131 Bit Name Initial Value Description Selects ,548 input pin. ITS5 0: PA5 1: P85 Selects ,547 input pin. ITS4 0: PA4 1: P84 Selects ,546 input pin. ITS3 0: P53 1: P83 Selects ,545 input pin. ITS2 0: P52 1: P82 Selects ,544 input pin.
Page 132: Software Standby Release Irq Enable Register (Ssier)
5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the ,54 pins used to recover from the software standby state. Bit Name Initial Value Description SSI15 Software Standby Release IRQ Setting SSI14 These bits select the ,54Q pins used to recover SSI13 from the software standby state.
Page 133: Internal Interrupts
When IRQ15 to IRQ0 interrupt requests occur at low level of ,54Q, the corresponding ,54 should be held low until an interrupt handling starts. Then the corresponding ,54 should be set to high in the interrupt handling routine and clear the IRQnF bit (n = 0 to 15) in ISR to 0. Interrupts may not be executed when the corresponding ,54#is set to high before the interrupt handling starts.
Page 134: Interrupt Exception Handling Vector Table
Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities.
Page 135 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC Source Mode Source Number Priority Activation Activation External H'001C — High — — IRQ0 H'0040 IPRA14 to IPRA12 — IRQ1 H'0044 IPRA10 to IPRA8 —...
Page 136 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC Source Source Number Mode Priority Activation Activation TPU_0 TGI0D H'00AC High — TCI0V H'00B0 — — — Reserved for H’00B4 IPRF6 to IPRF4 — — system use H’00B8 — — H’00BC —...
Page 137 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC Source Source Number Mode Priority Activation Activation High — — — Reserved for H’012C system use TMR_1 CMIA1 H'0130 IPRH10 to IPRH8 — — CMIB1 H'0134 — — OVI1 H'0138 — —...
Page 138 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC Source Source Number Mode Priority Activation Activation SCI_4 ERI4 H’01A0 IPRJ2 to IPRJ0 High — — RXI4 — — H’01A4 TXI4 H’01A8 — — TEI4 — — H’01AC Reserved for H’01B0 IPRK14 to IPRK12 —...
Page 139: Interrupt Control Modes And Interrupt Operation
Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2.
Page 140 Program execution status Interrupt generated? I = 0 Hold pending IRQ0 IRQ1 IICI1 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.
Page 141: Interrupt Control Mode 2
5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
Page 142: Interrupt Exception Handling Sequence
Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 or below? Level 1 interrupt? Mask level 5 or below? Mask level 0? Hold Save PC, CCR, and EXR pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance...
Page 143 Figure 5.5 Interrupt Exception Handling Rev. 1.0, 09/01, page 99 of 904...
Page 144: Interrupt Response Times
5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Page 145: Dtc And Dmac Activation By Interrupt
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Internal 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Instruction fetch S 6+2m Branch address read S Stack manipulation S Legend: m: Number of wait states in an external device access.
Page 146: Usage Notes
Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 147: Instructions That Disable Interrupts
5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 148 Rev. 1.0, 09/01, page 104 of 904...
Page 149: Section 6 Bus Controller (Bsc)
Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus masters—the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC), and data transfer controller (DTC).
Page 150 A block diagram of the bus controller is shown in figure 6.1. EXDMAC address bus Address Area decoder selector Internal address bus External bus controller Internal bus master bus request signal External bus EXDMAC bus request signal arbiter External bus Internal bus master bus acknowledge signal control signals EXDMAC bus acknowledge signal...
Page 151: Input/Output Pins
Input/Output Pins Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol Function Address strobe Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Read Output Strobe signal indicating that normal space is being read.
Page 152 Name Symbol Function &67/ Chip select 4/row address Output Strobe signal indicating that area 4 is 5$67/ strobe 4/write enable selected, DRAM row address strobe signal when area 4 is DRAM space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected.
Page 153: Register Descriptions
Name Symbol Function %5(42 Bus request output Output External bus request signal used when internal bus master accesses external address space when external bus is released. '$&.4 Data transfer acknowledge Output Data transfer acknowledge signal for single 1 (DMAC) address transfer by DMAC channel 1. '$&.3 '$&.3 Data transfer acknowledge...
Page 154: Bus Width Control Register (Abwcr)
• Refresh time constant register (RTCOR) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Name Initial Value* Description ABW7 Area 7 to 0 Bus Width Control ABW6 These bits select whether the corresponding ABW5...
Page 155: Wait Control Registers Ah, Al, Bh, And Bl (Wtcrah, Wtcral, Wtcrbh, And Wtcrbl)
6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM is connected. •...
Page 156 Bit Name Initial Value Description Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted...
Page 157 Bit Name Initial Value Description − Reserved This bit is always read as 0 and cannot be modified. Area 4 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1.
Page 158 Bit Name Initial Value Description Area 2 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM is connected*.
Page 159 • WTCRBL Bit Name Initial Value Description − Reserved This bit is always read as 0 and cannot be modified. Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1.
Page 160: Read Strobe Timing Control Register (Rdncr)
6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (5') negation timing in a basic bus interface read access. Bit Name Initial Value Description RDN7 Read Strobe Timing Control 7 to 0 RDN6 These bits set the negation timing of the read RDN5 strobe in a corresponding area read access.
Page 161: Cs Assertion Period Control Registers H, L (Csacrh, Csacrl)
&6 Assertion Period Control Registers H, L (CSACRH, CSACRL) &6 &6 &6 6.3.5 CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (&6Q) and address signals is to be extended. Extending the assertion period of the &6Q and address signals allows flexible interfacing to external I/O devices.
Page 162 Bus cycle Address Read Data Write Data Figure 6.3 &6 &6 and Address Assertion Period Extension (Example of 3-State Access Space &6 &6 and RDNn = 0) Rev. 1.0, 09/01, page 118 of 904...
Page 163: Area 0 Burst Rom Interface Control Register (Bromcrh) Area 1 Burst Rom Interface Control Register (Bromcrl)
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively.
Page 164: Bus Control Register (Bcr)
6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of :$,7 pin input. Bit Name Initial Value Description BRLE Bus Release Enable...
Page 165 Bit Name Initial Value Description ICIS0 Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted WDBE Write Data Buffer Enable The write data buffer function can be used for...
Page 166: Dram Control Register (Dramcr)
6.3.8 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM* interface settings. Note: * The synchronous DRAM interface is not supported in the H8S/2378 Serise. Bit Name Initial Value Description 2( Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin.
Page 167 Bit Name Initial Value Description CAST Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: 2 states 1: 3 states −...
Page 168 Bit Name Initial Value Description Burst Access Enable Selects enabling or disabling of burst access to areas designated as DRAM/continuous synchronous DRAM space. DRAM/continuous synchronous DRAM space burst access is performed in fast page mode. When using EDO page mode DRAM, the 2( signal must be connected.
Page 169 Bit Name Initial Value Description DMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when DMAC single address transfer is performed on the DRAM/synchronous DRAM . When the BE bit is cleared to 0 in DRAMCR, disabling DRAM/synchronous DRAM burst access, DMAC single address transfer is performed in full access mode regardless of the...
Page 170 Bit Name Initial Value Description MXC2 Address Multiplex Select MXC1 These bits select the size of the shift toward the MXC0 lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison.
Page 171 Bit Name Initial Value Description 011: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift •...
Page 172 Bit Name Initial Value Description 111: 11-bit shift • When 8-bit access space is designated: Row address bits A23 to A11 used for comparison • When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address.
Page 173: Dram Access Control Register (Draccr)
6.3.9 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: *The synchronous DRAM interface is not supported in the H8S/2378 series. Bit Name Initial Value Description DRMI Idle Cycle Insertion An idle cycle can be inserted after a DRAM/synchronous DRAM access cycle when a continuous normal space access cycle follows a DRAM/synchronous DRAM access cycle.
Page 174 Bit Name Initial Value Description RCD1 RAS-CAS Wait Control RCD0 These bits select a wait cycle to be inserted between the 5$6 assert cycle and &$6 assert cycle. A 1- to 4-state wait cycle can be inserted. 00: Wait cycle not inserted 01: 1-state wait cycle inserted 10: 2-state wait cycle inserted 11: 3-state wait cycle inserted...
Page 175 ø Address bus Column address Column address Row address Precharge-sel Row address SDWCD 0 High Data bus PALL ACTV WRIT Address bus Column address Column address Row address Precharge-sel Row address SDWCD 1 High Data bus PALL ACTV WRIT Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous DRAM Space Write Access (for CAS Latency 2) Rev.
Page 176: Refresh Control Register (Refcr)
6.3.10 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: *The synchronous DRAM interface is not supported in the H8S/2378 series. Bit Name Initial Value Description R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR.
Page 177 Bit Name Initial Value Description − Reserved This bit is always read as 0. The initial value should not be changed. RTCK2 Refresh Counter Clock Select RTCK1 These bits select the clock to be used to RTCK0 increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up.
Page 178 Bit Name Initial Value Description RLW1 Refresh Cycle Wait Control RLW0 These bits select the number of wait states to be inserted in a DRAM interface CAS-before- RAS refresh cycle/synchronous DRAM interface auto-refresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space.
Page 179: Refresh Timer Counter (Rtcnt)
6.3.11 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00.
Page 180 H'000000 H'0000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'FFFF H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000...
Page 181: Bus Specifications
6.4.2 Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (&6) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 182: Memory Interfaces
Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WTCRA, WTCRB Bus Specifications (Basic Bus Interface) Access Program Wait ABWn ASTn Bus Width States States — — — — — — (n = 0 to 7) Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of the read cycle or one half-state before the end of the read cycle) for the read strobe (5') used in the basic bus interface space.
Page 183 ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, an area for which the synchronous DRAM interface is designated functions as continuous synchronous DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space.
Page 184: Chip Select Signals
Only the basic bus interface can be used for area 6. Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external address space. The on- chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR);...
Page 185: Basic Bus Interface
Bus cycle ø Address bus Area n external address Figure 6.7 &6Q &6Q &6Q Signal Output Timing (n = 0 to 7) &6Q Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Page 186 Upper data bus Lower data bus D8 D7 Byte size 1st bus cycle Word size 2nd bus cycle 1st bus cycle 2nd bus cycle Longword size 3rd bus cycle 4th bus cycle Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.9 illustrates data alignment control for the 16-bit access space.
Page 187: Valid Strobes
6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the 5' signal is valid for both the upper and the lower half of the data bus. In a write, the +:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half.
Page 188 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Invalid High Write D15 to D8 Valid High impedance D7 to D0 Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space Rev.
Page 189 8-Bit, 3-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The /:5 pin is always fixed high. Wait states can be inserted. Bus cycle ø...
Page 190 16-Bit, 2-State Access Space: Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted.
Page 191 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev.
Page 192 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev.
Page 193 16-Bit, 3-State Access Space: Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Page 194 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev.
Page 195: Wait Control
Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) 6.5.4 Wait Control...
Page 196 Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T state and T state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB. Pin Wait Insertion: Setting the WAITE bit to 1 in BCR enables wait input by means of the :$,7 pin.
Page 197: Read Strobe ( Rd ) Timing
By program wait ø Address bus Read Data bus Read data Write Data bus Write data Notes: 1. Downward arrows indicate the timing of pin sampling. 2. When RDN = 0 Figure 6.18 Example of Wait State Insertion Timing 5') Timing 6.5.5 Read Strobe (5' The read strobe (5') timing can be changed for individual areas by setting bits RDN7 to RDN0 to...
Page 198: Extension Of Chip Select ( Cs ) Assertion Period
Bus cycle ø Address bus RDNn = 0 Data bus RDNn = 1 Data bus Figure 6.19 Example of Read Strobe Timing &6) Assertion Period &6 &6 6.5.6 Extension of Chip Select (&6 Some external I/O devices require a setup time and hold time between address and &6 signals and strobe signals such as 5', +:5, and /:5.
Page 199: Dram Interface
Bus cycle ø Address bus Read (when RDNn = 0) Data bus Read data Write Data bus Write data Figure 6.20 Example of Timing when Chip Select Assertion Period is Extended Both extension state T inserted before the basic bus cycle and extension state T inserted after the basic bus cycle, or only one of these, can be specified for individual areas.
Page 200: Address Multiplexing
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2 to 5), and continuous area (areas 2 to 5). Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space RMTS2 RMTS1 RMTS0...
Page 201: Data Bus
Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR Address Pins MXC2 MXC1 MXC0 Shift Size A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8 bits A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 address 9 bits...
Page 202: Pins Used For Dram Interface
6.6.4 Pins Used for DRAM Interface Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the &65 to &68 pins are in the input state after a reset, set the corresponding DDR to 1 when 5$65 to 5$68 signals are output.
Page 203: Basic Timing
6.6.5 Basic Timing Figure 6.21 shows the basic access timing for DRAM space. The four states of the basic timing consist of one T (precharge cycle) state, one T (row address output cycle) state, and the T and two T (column address output cycle) states.
Page 204: Column Address Output Cycle Control
from both the 5' pin and the (2() pin, but in external read cycles for other than DRAM space, the signal is output only from the 5' pin. 6.6.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR.
Page 205: Row Address Output State Control
6.6.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the 5$6 signal goes low from the beginning of the T state, and the row address hold time and DRAM read access time are changed relative to the fall of the 5$6 signal.
Page 206 If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three T states, in which row address output is maintained, cycle, in which the 5$6 signal goes low, and the T to be inserted between the T cycle, in which the column address is output.
Page 207: Precharge State Control
6.6.8 Precharge State Control When DRAM is accessed, a 5$6 precharge time must be secured. With this LSI, one T state is always inserted when DRAM space is accessed. From one to four T states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T cycles according to the DRAM connected and the operating frequency of this LSI.
Page 208: Wait Control
6.6.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the :$,7 pin. Wait states are inserted to extend the &$6 assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of &$6 in a write access.
Page 209 By program wait ø Row address Column address Address bus High Read Data bus Write High Data bus Note: Downward arrows indicate the timing of pin sampling. n = 2 to 5 Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output) Rev.
Page 210 By program wait ø Row address Column address Address bus High Read Data bus Write High Data bus Note: Downward arrows indicate the timing of pin sampling. n = 2 to 5 Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output) Rev.
Page 211: Byte Access Control
6.6.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.28 shows the control timing for 2-CAS access, and figure 6.29 shows an example of 2-CAS DRAM connection. ø...
Page 212: Burst Operation
This LSI 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration (Address shift size set to 10 bits) 10-bit column address Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 D15 to D0 Figure 6.29 Example of 2-CAS DRAM Connection 6.6.11 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a...
Page 213 ø Row address Column address 1 Column address 2 Address bus High Read Data bus Write High Data bus Note: n = 2 to 5 Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev. 1.0, 09/01, page 169 of 904...
Page 214 ø Row address Column address 1 Column address 2 Address bus High Read Data bus Write High Data bus Note: n = 2 to 5 Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access.
Page 215  the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the 5$6 down state, the clock will stop with 5$6 low. To enter the all-module-clocks-stopped mode with 5$6 high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction.
Page 216: Refresh Control
• RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the 5$6 signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.33 shows an example of the timing in RAS up mode.
Page 217 CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in REFCR. With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed.
Page 218 ø Figure 6.36 CBR Refresh Timing A setting can be made in bits RCW1 and RCW0 in REFCR to delay 5$6 signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the 5$6 signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Page 219 Normal space access request ø A23 to A0 Refresh period Figure 6.38 Example of CBR Refresh Timing (CBRM = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR.
Page 220 Software standby ø High Note: n = 2 to 5 Figure 6.39 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the 5$6 signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time.
Page 221: Dmac And Exdmac Single Address Transfer Mode And Dram Interface
Software DRAM space write standby ø Address bus Data bus Note: n = 2 to 5 Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the...
Page 222 When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the '$&. or ('$&. output goes low from the T state. Figure 6.41 shows the '$&. or ('$&. output timing for the DRAM interface when DDS = 1 or EDDS = 1.
Page 223 In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.42 shows the '$&. or ('$&. output timing for the DRAM interface when DDS = 0 or EDDS = 0. ø...
Page 224: Synchronous Dram Interface
Synchronous DRAM Interface In the H8S/2378R Series, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Page 225: Address Multiplexing
6.7.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. The address-precharge-setting command (Prechrge-sel) can be output on the upper column address.
Page 226: Data Bus
6.7.3 Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be connected directly.
Page 227 Table 6.9 Synchronous DRAM Interface Pins With Synchronous DRAM Setting Name Function &65 Row address strobe Output Row address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space &66 &$6 Column address strobe Output Column address strobe when areas 2 to 5 are designated as continuous synchronous DRAM space...
Page 228: Synchronous Dram Clock
6.7.5 Synchronous DRAM Clock When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the &68 pin. When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2, SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks.
Page 229 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1) Rev.
Page 230: Cas Latency Control
6.7.7 CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (T ) is inserted.
Page 231 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) Rev.
Page 232: Row Address Output State Control
6.7.8 Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR.
Page 233 ø ø SDRAM Column Address bus Row address Column address address Row address Precharge-sel Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.46 Example of Access Timing when Row Address Output Hold State is 1 State (RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) Rev.
Page 234: Precharge State Count
6.7.9 Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four T states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T cycles according to the synchronous DRAM connected and the operating frequency of this LSI.
Page 235 The setting of bits TPC1 and TPC0 is also valid for T states in refresh cycles. ø ø SDRAM Address bus Column address Row address Column address Row address Precharge-sel Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus...
Page 236: Bus Cycle Control In Write Cycle
6.7.10 Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access.
Page 237: Byte Access Control
6.7.11 Byte Access Control When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.49 and 6.50 show the control timing for DQM, and figure 6.51 shows an example of connection of byte control by DQMU and DQML.
Page 238 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address High DQMU High DQML Upper data bus High-Z Lower data bus PALL ACTV READ Figure 6.50 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) Rev.
Page 239: Burst Operation
16-Mbit synchronous DRAM This LSI 1 Mword × 16 bits × 4-bank configuration (Address shift size set to 8 bits) 8-bit column address (DQMU) DQMU (DQML) DQML (SDRAMø) A13 (BS1) A12 (BS0) Row address input: A11 to A0 Column address input: A7 to A0 Bank select address: A13/A12...
Page 240 DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal cannot be specified to the Tc2 cycle data output if Tc1 cycle is performed for second or following column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE bit to 1 when synchronous DRAM of CAS latency 1 is connected.
Page 241 ø ø SDRAM Column Address bus Row address Column address Column address 2 address 1 Row address Precharge-sel Read High DQMU, DQML Data bus PALL ACTV READ READ Write High DQMU, DQML Data bus PALL ACTV WRIT WRIT Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2) RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space.
Page 242 Note, however, the next continuous synchronous DRAM space access is a full access if: • a refresh operation is initiated in the RAS down state • self-refreshing is performed • the chip enters software standby mode • the external bus is released •...
Page 243: Refresh Control
6.7.13 Refresh Control This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as continuous synchronous DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
Page 244 T Rp T Rr T Rc1 T Rc2 SDRAM Address bus Precharge-sel High PALL Figure 6.54 Auto Refresh Timing When the interval specification from the PALL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the T cycle that is set by the TPC1 and TPC0 bits of DRACCR.
Page 245 ø SDRAMø Address bus Precharge-sel High PALL Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle.
Page 246 ø SDRAMø Address bus Precharge-sel High PALL Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM.
Page 247 Software standby SDRAMø Address bus Precharge-sel PALL SELF Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified.
Page 248: Mode Register Setting Of Synchronous Dram
Continuous synchronous DRAM space write Software standby ø ø SDRAM Address bus Column address Row address Column address Precharge-sel Row address DQMU, DQML Data bus PALL ACTV Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2) Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit...
Page 249 by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of address H'400000 + 2X for 16-bit bus configuration synchronous DRAM. The value of the address signal is fetched at the issuance time of the MRS command as the setting value of the mode register in the synchronous DRAM.
Page 250: Dmac And Exdmac Single Address Transfer Mode And Synchronous Dram Interface
6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the '$&. and ('$&. output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed.
Page 251 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.60 Example of '$&. '$&./('$&. ('$&. Output Timing when DDS = 1 or EDDS = 1 '$&.
Page 252 When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the '$&. or ('$&. output goes low from the T state.
Page 253 ø SDRAMø Address bus Column address Row address Column address Precharge-sel Row address Read High DQMU, DQML Data bus PALL ACTV READ Write High DQMU, DQML Data bus PALL ACTV WRIT Figure 6.61 Example of '$&. '$&./('$&. ('$&. Output Timing when DDS = 0 or EDDS = 0 '$&.
Page 254 (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is read- accessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR.
Page 255: Burst Rom Interface
Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR.
Page 256 Full access Burst access ø Upper address bus Lower address bus Data bus Note: n = 1 and 0 Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev. 1.0, 09/01, page 212 of 904...
Page 257: Wait Control
Full access Burst access ø Upper address bus Lower address bus Data bus Note: n = 1 and 0 Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.8.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the :$,7 pin can be used in the initial cycle (full access) on the burst ROM interface.
Page 258: Idle Cycle
Idle Cycle 6.9.1 Operation When this LSI accesses external address space, it can insert an idle cycle (T ) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle.
Page 259 Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.66 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Page 260 Bus cycle A Bus cycle B Bus cycle A Bus cycle B ø ø Address bus Address bus (area A) (area A) (area B) (area B) Data bus Data bus Data collision Idle cycle Long output floating time (a) No idle cycle insertion (b) Idle cycle insertion (ICIS2 = 0) (ICIS2 = 1, initial value)
Page 261 Bus cycle A Bus cycle B Bus cycle A Bus cycle B ø ø Address bus Address bus (area A) (area A) (area B) (area B) Idle cycle Overlap period between (area B) may occur (b) Idle cycle insertion (a) No idle cycle insertion (ICIS1 = 1, initial value) (ICIS1 = 0) &6) and Read (5'...
Page 262 In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 6.70 and 6.71. DRAM space read External read DRAM space read ø...
Page 263 Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access: In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not.
Page 264 Continuous synchronous Continuous synchronous DRAM space read External space read DRAM space read ø Column Address bus Column address 1 External address Column address 2 address address Precharge-sel External address address High DQMU, DQML High Data bus PALL ACTV READ READ Idle cycle Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode...
Page 265 Continuous synchronous Continuous synchronous DRAM space read External space read DRAM space read ø Column Address bus Column address 1 External address Column address 2 address address External address Precharge-sel address High DQMU, DQML High Data bus PALL ACTV READ READ Idle cycle Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode...
Page 266 Continuous synchronous Continuous synchronous DRAM space read External space read DRAM space write ø Column Column address 1 External address Column address 2 Address bus address address External address Precharge-sel address High DQMU, DQML High Data bus PALL ACTV READ WRIT Idle cycle Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode...
Page 267 DRAM space read External address space read DRAM space read ø Address bus Data bus Idle cycle Figure 6.76 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) DRAM space read External address space write DRAM space read...
Page 268 • Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit.
Page 269 Continuous synchronous Continuous synchronous DRAM space read External space read DRAM space read ø Column Column address 1 External address Column address 2 Address bus address address External address Precharge-sel address High DQMU, DQML Data bus PALL ACTV READ READ Idle cycle Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
Page 270 Continuous synchronous Synchronous DRAM space write External address space read DRAM space read ø Column Column Address bus External address Column address 2 address address address Precharge-sel External address address High DQMU, DQML Data bus PALL ACTV NOP WRIT READ Idle cycle Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
Page 271 Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous Synchronous DRAM Space Previous Access Next Access ICIS2* ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space read Normal space read — — — — Disabled (different area) —...
Page 272 Previous Access Next Access ICIS2* ICIS1 ICIS0 DRMI IDLC Idle cycle DRAM/continuous Normal space read — — — — Disabled synchronous — — — 1 state inserted DRAM* 2 states inserted space write DRAM/continuous — — — — Disabled synchronous DRAM* —...
Page 273 Continuous synchronous Continuous synchronous DRAM space read DRAM space write ø Column Column External address Address bus address address address Precharge-sel High DQMU, DQML Data bus PALL ACTV READ WRIT Idle cycle Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to Continuous Synchronous DRAM Space in RAS Down Mode (SDWCD = 1, CAS Latency 2) Rev.
Page 274: Pin States In Idle Cycle
6.9.2 Pin States in Idle Cycle Table 6.12 shows the pin states in an idle cycle. Table 6.12 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance &6Q (n = 7 to 0) High* 8&$6, /&$6 High*...
Page 275: Bus Release
On-chip memory read Internal I/O register read External write cycle Internal address bus Internal memory Internal I/O register address Internal read signal External address A23 to A0 External space write D15 to D0 Figure 6.83 Example of Timing when Write Data Buffer Function is Used 6.11 Bus Release This LSI can release the external bus in response to a bus request from an external device.
Page 276 In the external bus released state, internal bus masters except the EXDMAC can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled.
Page 277: Pin States In External Bus Released State
6.11.2 Pin States in External Bus Released State Table 6.13 shows pin states in the external bus released state. Table 6.13 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance &6Q (n = 7 to 0) High impedance 8&$6, /&$6...
Page 278: Transition Timing
6.11.3 Transition Timing Figure 6.84 shows the timing for transition to the bus released state. External space access cycle cycle External bus released state ø High-Z Address bus High-Z Data bus High-Z High-Z High-Z [1] Low level of signal is sampled at rise of ø. [2] Bus control signal returns to be high at end of external space access cycle.
Page 279 Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM interface. External space read cycle External bus released state ø SDRAMø High-Z Address bus High-Z Data bus High-Z Precharge-sel address High-Z High-Z High-Z High-Z High-Z DQMU, DQML PALL...
Page 280: Bus Arbitration
6.12 Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations (bus arbitration). There are four bus masters—the CPU, DTC, DMAC, and EXDMAC—that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
Page 281 CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, DMAC, or EXDMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: •...
Page 282: Bus Controller Operation In Reset
External Bus Release: When the %5(4 pin goes low and an external bus release request is issued while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle. 6.13 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any...
Page 283: Breqo Output Timing
%5(42 Output Timing %5(42 %5(42 %5(42 6.14.4 When the BREQOE bit is set to 1 and the %5(42 signal is output, %5(42 may go low before the %$&. signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of %5(4.
Page 284 Rev. 1.0, 09/01, page 240 of 904...
Page 285: Section 7 Dma Controller (Dmac)
Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. Features • Choice of short address mode or full address mode Short address mode Maximum of 4 channels can be used Dual address mode or single address mode can be selected In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as 16 bits...
Page 286 A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal interrupts TGI0A Address buffer TGI1A TGI2A Processor TGI3A TGI4A TGI5A MAR_0AH MAR_0AL TXI0 IOAR_0A RXI0 Control logic TXI1 ETCR_0A RXI1 MAR_0BH MAR_0BL External pins IOAR_0B ETCR_0B DMAWER MAR_1AH...
Page 287: Input/Output Pins
Input/Output Pins Table 7.1 summarizes the pins of the interrupt controller. Table 7.1 Pin Configuration Channel Pin Name Symbol Function '5(43 DMA request 0 Input Channel 0 external request DMA transfer acknowledge 0 '$&.3 Output Channel 0 single address transfer acknowledge 7(1'3 DMA transfer end 0 Output...
Page 288: Memory Address Registers (Mara And Marb)
• DMA band control register H (DMABCRH) • DMA band control register L (DMABCRL) • DMA write enable register (DMAWER) • DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode).
Page 289: I/O Address Registers (Ioara And Ioarb)
MAR is not initialized by a reset or in standby mode. Short Address Mode: In short address mode, MARA and MARB operate independently. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated.
Page 290 Short Address Mode: The function of ETCR in sequential mode and idle mode differs from that in repeat mode. In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit in DMABCRL is cleared, and transfer ends.
Page 291: Dma Control Registers (Dmacra And Dmacrb)
7.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B).
Page 292 Bit Name Initial Value Description Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. • When DTIE = 0 (no transfer end interrupt) 0: Transfer in sequential mode 1: Transfer in repeat mode •...
Page 293 Bit Name Initial Value Description • Channel A 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Setting prohibited 0011: Setting prohibited 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 reception complete interrupt 0110: Activated by SCI channel 1 transmission complete interrupt...
Page 294 Bit Name Initial Value Description • Channel B 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Activated by '5(4 pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by '5(4 pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt...
Page 295 Full Address Mode: • DMACR_0A and DMACR_1A Bit Name Initial Value Description DTSZ Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer SAID Source Address Increment/Decrement SAIDE Source Address Increment/Decrement Enable These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data...
Page 296 Bit Name Initial Value Description  Reserved These bits can be read from or written to. Legend x: Don't care • DMACR_0B and DMACR_1B Bit Name Initial Value Description  Reserved These bits can be read from or written to. DAID Destination Address Increment/Decrement DAIDE...
Page 297 Bit Name Initial Value Description • Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by '5(4 pin falling edge input 0011: Activated by '5(4 pin low-level input 010x: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1xxx: Setting prohibited •...
Page 298: Dma Band Control Registers H And L (Dmabcrh And Dmabcrl)
Bit Name Initial Value Description The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Legend x: Don't care 7.3.5...
Page 299 Bit Name Initial Value Description SAE0 Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode DTA1B Data Transfer Acknowledge 1B...
Page 300 • DMABCRL Bit Name Initial Value Description DTE1B Data Transfer Enable 1B DTE1A Data Transfer Enable 1A DTE0B Data Transfer Enable 0B DTE0A Data Transfer Enable 0A If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Page 301 Bit Name Initial Value Description DTIE1B Data Transfer End Interrupt Enable 1B DTIE1A Data Transfer End Interrupt Enable 1A DTIE0B Data Transfer End Interrupt Enable 0B DTIE0A Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
Page 302 Full Address Mode: • DMABCRH Bit Name Initial Value Description FAE1 Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1.
Page 303 Bit Name Initial Value Description DTA1 Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer.
Page 304 Bit Name Initial Value Description DTA0 Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer.
Page 305 • DMABCRL Bit Name Initial Value Description DTME1 Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted,...
Page 306 Bit Name Initial Value Description DTE1 Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored.
Page 307 Bit Name Initial Value Description DTME0 Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted,...
Page 308 Bit Name Initial Value Description DTE0 Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored.
Page 309 Bit Name Initial Value Description DTIE1A Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTIE1A bit is set to 1 when DTE1 = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Page 310: Dma Write Enable Register (Dmawer)
7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
Page 311 MAR_0A First transfer area IOAR_0A ETCR_0A MAR_0B IOAR_0B ETCR_0B MAR_1A IOAR_1A ETCR_1A MAR_1B IOAR_1B ETCR_1B DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B Second transfer area DMABCR using chain transfer Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A) Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings.
Page 312: Dma Terminal Control Register (Dmatcr)
7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. Bit Name Initial Value Description ...
Page 313: Activation Sources
Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and auto- requests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.3 DMAC Activation Sources Short Address Mode Full Address Mode Block...
Page 314: Activation By External Request
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA transfer. With TXI and RXI interrupts, however, the interrupt source flag is not cleared unless the relevant register is accessed in a DMA transfer.
Page 315: Operation
Operation 7.5.1 Transfer Modes Table 7.4 lists the DMAC transfer modes. Table 7.4 DMAC Transfer Modes Transfer Mode Transfer Source Remarks • • Short Dual address mode TPU channel 0 to 5 Up to 4 channels can address compare match/input operate independently (1) Sequential mode mode...
Page 316 Transfer Mode Transfer Source Remarks • Single address mode External request • 1-byte or 1-word transfer for a single transfer request • 1-bus cycle transfer by means of '$&. pin instead of using address for specifying I/O • Sequential mode, idle mode, or repeat mode can be specified •...
Page 317: Sequential Mode
7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR.
Page 318 Transfer Address T IOAR 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N – 1)) Where : L = Value set in MAR Address B N = Value set in ETCR Figure 7.3 Operation in Sequential Mode...
Page 319: Idle Mode
[1] Set each bit in DMABCRH. Sequential mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
Page 320 by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.6 Register Functions in Idle Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation Source Destination Start address of...
Page 321: Repeat Mode
[1] Set each bit in DMABCRH. Idle mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
Page 322 their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in repeat mode. Table 7.7 Register Functions in Repeat Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting...
Page 323 not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR...
Page 324: Single Address Mode
[1] Set each bit in DMABCRH. Repeat mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
Page 325 One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin ('$&.). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.8 Register Functions in Single Address Mode Function...
Page 326 Transfer Address T 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N – 1)) Where : L = Value set in MAR Address B N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified)
Page 327: Normal Mode
[1] Set each bit in DMABCRH. Single address • Clear the FAE bit to 0 to select short address mode setting mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal Set DMABCRH interrupt clearing with the DTA bit.
Page 328 to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9 summarizes register functions in normal mode. Table 7.9 Register Functions in Normal Mode Register Function Initial Setting...
Page 329 Transfer Address T Address T Address B Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) · (2 · (N – 1)) DAID DTSZ Address + DAIDE · (–1) · (2 · (N – 1)) Where : = Value set in MARA = Value set in MARB = Value set in ETCRA...
Page 330: Block Transfer Mode
[1] Set each bit in DMABCRH. Normal mode setting • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address in MARA, and the transfer destination address in MARB.
Page 331 ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register Function...
Page 332 Address T Address T 1st block Block area Transfer Address B Consecutive transfer of M bytes or words is performed in response to one request 2nd block Nth block Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) ·...
Page 333 Address T Address T Block area 1st block Transfer Consecutive transfer Address B of M bytes or words is performed in response to one request 2nd block Nth block Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) ·...
Page 334 Figure 7.15 shows the operation flow in block transfer mode. Start (DTE = DTME = 1) Transfer request? Acquire bus Read address specified by MARA SAID DTSZ MARA = MARA + SAIDE·(–1) ·2 Write to address specified by MARB DAID DTSZ MARB = MARB + DAIDE·(–1) ·2...
Page 335 Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH.
Page 336: Basic Bus Cycles
7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word- size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed.
Page 337 read read read write write write dead ø Address bus Bus release Bus release Bus release Last transfer cycle release Figure 7.18 Example of Short Address Mode Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
Page 338 read write read write read write dead ø Address bus Bus release Bus release Bus release Last transfer cycle release Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
Page 339 read write read write read write dead ø Address bus Last transfer cycle Bus release Bus release Burst transfer Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.
Page 340 read write read write dead read write read write dead ø Address bus Bus release Block transfer Bus release Last block transfer release Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) A one-block transfer is performed for a single transfer request, and after the transfer the bus is released.
Page 341 Bus release read write release read write release ø Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle control Channel Request clear period Request Request clear period Request Minimum Minimum of 2 cycles of 2 cycles Acceptance resumes Acceptance resumes...
Page 342 1 block transfer 1 block transfer Bus release read write dead release read write dead release ø Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle control Request clear period Request clear period Channel Request Request...
Page 343 release read write release read write release ø Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle control Channel Request clear period Request clear period Request Request Minimum Minimum of 2 cycles of 2 cycles Acceptance resumes Acceptance resumes Acceptance after transfer enabling;...
Page 344: Dma Transfer (Single Address Mode) Bus Cycles
1 block transfer 1 block transfer Bus release read write dead release read write dead release ø Address Transfer source Transfer source Transfer destination Transfer destination Idle Read Write Dead Idle Read Write Dead Idle control Request clear period Request clear period Channel Request Request...
Page 345 DMA read DMA read DMA read DMA read dead ø Address bus Last transfer release release release release cycle release Figure 7.26 Example of Single Address Mode Transfer (Byte Read) Figure 7.27 shows a transfer example in which 7(1' output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
Page 346 In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Single Address Mode (Write): Figure 7.28 shows a transfer example in which 7(1' output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
Page 347 DMA write DMA write DMA write dead ø Address bus Last transfer release release release cycle release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
Page 348 Bus release DMA single Bus release DMA single Bus release ø Transfer source/ Transfer source/ Address bus destination destination DMA control Idle Single Idle Single Idle Request clear Request clear Channel Request Request period period Minimum of Minimum of 2 cycles 2 cycles Acceptance resumes Acceptance resumes...
Page 349 Figure 7.31 shows an example of single address mode transfer activated by the '5(4 pin low level. Bus release DMA single Bus release DMA single release ø Transfer source/ Transfer source/ Address bus destination destination Single DMA control Idle Idle Single Idle Request clear...
Page 350: Write Data Buffer Function
7.5.11 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
Page 351: Multi-Channel Operation
read single read single read ø Internal address Internal read signal External address Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation.
Page 352: Relation Between Dmac And External Bus Requests, Refresh Cycles, And Exdmac
read DMA read DMA write DMA read DMA write DMA read DMA write ø Address bus DMA control Idle Read Write Idle Read Write Idle Read Write Read Channel 0A Request clear Request clear Request Selection Channel 0B hold Request clear Request Request Non-...
Page 353: Dmac And Nmi Interrupts
7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are set to 1.
Page 354: Clearing Full Address Mode
[1] Clear the DTE bit in DMABCRL to 0. Forced termination To prevent interrupt generation after forced of DMAC termination of DMAC operation, clear the DTIE bit to 0 at the same time. Clear DTE bit to 0 Forced termination Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation 7.5.16 Clearing Full Address Mode...
Page 355: Interrupt Sources
[1] Clear both the DTE bit and DTME bit in Clearing full DMABCRL to 0, or wait until the transfer ends address mode and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time.
Page 356: Usage Notes
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt controller independently. The priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.12.
Page 357 DMA last transfer cycle DMA transfer cycle dead DMA read DMA read DMA write DMA write ø DMA Internal Transfer Transfer Transfer Transfer destination source source destination address Read Idle Idle Write Idle Read DMA control Write Dead DMA register [2'] operation [1] Transfer source address register MAR operation (incremented/decremented/fixed)
Page 358: Module Stop
7.7.2 Module Stop When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is enabled.
Page 359: Activation By Falling Edge On Dreq Pin
4. Bus release cycle 5. CBR refresh cycle Figure 7.41 shows an example in which a low level is not output from the 7(1' pin in case 2 above. If the last transfer cycle is an external address cycle, a low level is output at the 7(1' pin in synchronization with the bus cycle.
Page 360: Activation Source Acceptance
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level. 7.7.6 Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both '5(4 pin falling edge sensing and low level sensing.
Page 361: Section 8 Exdma Controller
Section 8 EXDMA Controller This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. Features •...
Page 362 Bus controller Data buffer External pins Control logic Address buffer Processor EDSAR Interrupt request EDDAR signals to CPU EDMDR for individual EDTCR EDACR channels Internal data bus Legend EDSAR: EXDMA source address register EDDAR: EXDMA destination address register EDTCR: EXDMA transfer count register EDMDR: EXDMA mode control register EDACR:...
Page 363: Input/Output Pins
Input/Output Pins Table 8.1 summarizes the pins of the EXDMAC. Table 8.1 Pin Configuration Abbre- Channel Name viation Function ('5(45 EXDMA transfer request 2 Input Channel 2 external request ('$&.5 EXDMA transfer Output Channel 2 single address transfer acknowledge 2 acknowledge (7(1'5 EXDMA transfer end 2...
Page 364: Exdma Source Address Register (Edsar)
8.3.1 EXDMA Source Address Register (EDSAR) EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when a device with '$&.
Page 365: Exdma Transfer Count Register (Edtcr)
8.3.3 EXDMA Transfer Count Register (EDTCR) EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do not write to EDTCR for a channel on which EXDMA transfer is in progress. Normal Transfer Mode: Bit Name Initial Value Description —...
Page 366 Block Transfer Mode: Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be modified. Undefined Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256.
Page 367: Exdma Mode Control Register (Edmdr)
8.3.4 EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit Name Initial Value Description R/(W) EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress.
Page 368 Bit Name Initial Value Description R/(W)* Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1. The address registers indicate the next transfer addresses, but the data for which transfer has been performed within the block size is lost.
Page 369 Bit Name Initial Value Description MDS1 Mode Select 1 and 0 MDS0 These bits specify the activation source, bus mode, and transfer mode. 00: Auto request, cycle steal mode, normal transfer mode 01: Auto request, burst mode, normal transfer mode 10: External request, cycle steal mode, normal transfer mode 11: External request, cycle steal mode, block...
Page 370 Bit Name Initial Value Description TCEIE Transfer Counter End Interrupt Enable Enables or disables transfer end interrupt requests by the transfer counter. When transfer ends according to the transfer counter while this bit is set to 1, the IRF bit is set to 1, indicating that an interrupt request has occurred.
Page 371: Exdma Address Control Register (Edacr)
8.3.5 EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit Name Initial Value Description SAT1 Source Address Update Mode SAT0 These bits specify incrementing/decrementing of the transfer source address (EDSAR). When an external device with DACK is designated as the transfer source in single address mode, the specification by these bits is ignored.
Page 372 Bit Name Initial Value Description Source Address Repeat Area SARA4 SARA3 These bits specify the source address (EDSAR) SARA2 repeat area. The repeat area function updates SARA1 the specified lower address bits, leaving the SARA0 remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified.
Page 373 Bit Name Initial Value Description DAT1 Destination Address Update Mode DAT0 These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored.
Page 374 Bit Name Initial Value Description DARA4 Destination Address Repeat Area DARA3 These bits specify the destination address DARA2 (EDDAR) repeat area. The repeat area function DARA1 updates the specified lower address bits, DARA0 leaving the remaining upper address bits always the same.
Page 375: Operation
Operation 8.4.1 Transfer Modes The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.2 EXDMAC Transfer Modes Address Registers Transfer Number of Transfer Mode Origin Transfers Source Destination Dual Normal Auto request mode Auto 1 to EDSAR EDDAR address transfer...
Page 376: Address Modes
In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode. When the “no specification”...
Page 377 EXDMA EXDMA read cycle write cycle ø Address bus EDSAR EDDAR Figure 8.2 Example of Timing in Dual Address Mode Single Address Mode: In single address mode, the ('$&. signal is used instead of the source or destination address register to transfer data directly between an external device and external memory.
Page 378 External External address bus data bus Microcomputer External memory EXDMAC External device with DACK Data flow Figure 8.3 Data Flow in Single Address Mode Rev. 1.0, 09/01, page 334 of 904...
Page 379 Transfer from external memory to external device with DACK EXDMA cycle ø Address to external memory space Address bus EDSAR signal to external memory space Data output from external memory Data bus Transfer from external device with DACK to external memory EXDMA cycle ø...
Page 380: Dma Transfer Requests
8.4.3 DMA Transfer Requests Auto Request Mode: In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory.
Page 381 If a transfer request occurs in another channel during DMA transfer, the bus is temporarily released, then transfer is performed on the channel for which the transfer request was issued. If there is no external space bus request from another bus master, a one-cycle bus release interval is inserted.
Page 382: Transfer Modes
Bus cycle EXDMAC EXDMAC EXDMAC CPU cycle not generated Transfer conditions: Auto request mode, BGUP = 0 Bus cycle EXDMAC EXDMAC EXDMAC EXDMAC operates alternately with CPU Transfer conditions: Auto request mode, BGUP = 1 Figure 8.6 Examples of Timing in Burst Mode 8.4.5 Transfer Modes There are two transfer modes: normal transfer mode and block transfer mode.
Page 383 EXDMA Last EXDMA transfer cycle transfer cycle Bus cycle Read Write Read Write Transfer conditions: Dual address mode, auto request mode Bus cycle EXDMA EXDMA Transfer conditions: Single address mode, external request mode Figure 8.7 Examples of Timing in Normal Transfer Mode Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request.
Page 384: Repeat Area Function
Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA Transfer, for details. Figure 8.8 shows an example of DMA transfer timing in block transfer mode. One-block transfer cycle Bus cycle EXDMAC EXDMAC EXDMAC CPU cycle not generated Transfer conditions: ·...
Page 385 IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1 in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to the destination address register.
Page 386: Registers During Dma Transfer Operation
When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3), and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode External memory Range of First block Second block EDSAR values transfer transfer...
Page 387 When EDSAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output.
Page 388 In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word access. Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is contention between an address update associated with DMA transfer and a write by the CPU, the CPU write has priority.
Page 389 • When an NMI interrupt is generated, and transfer halts • A reset • Hardware standby mode • When 0 is written to the EDA bit, and transfer halts When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA transfer period.
Page 390: Channel Priority Order
of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an NMI interrupt. If an NMI interrupt is generated during block transfer, operation is halted midway through a block-size transfer and the EDA bit is cleared to 0, terminating the transfer operation.
Page 391 Channel 0 transfer Channel 1 transfer Channel 2 transfer ø Channel 0 Channel 1 Channel 2 Address bus release release Idle Channel 0 Channel 1 Channel 2 EXDMA control Request cleared Channel 0 Request Selected Request cleared Channel 1 held Request Request Channel 2...
Page 392 Conditions (1) Channel 0: Auto request, cycle steal mode Channel 1: External request, cycle steal mode, low level activation Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 0 EDA bit Channel 1/ Conditions (2) Channel 1: External request, cycle steal mode, low level activation Channel 2: Auto request, cycle steal mode Channel 2 Channel 2...
Page 393: Exdmac Bus Cycles (Dual Address Mode)
8.4.9 EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode): Figure 8.15 shows an example of transfer when (7(1' output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released.
Page 394 DMA read DMA write DMA read DMA write DMA read DMA write ø Address bus Last transfer cycle release release Burst transfer Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer If an NMI interrupt is generated while a channel designated for burst transfer is enabled for transfer, the EDA bit is cleared and transfer is disabled.
Page 395 ('5(4 ('5(4 Pin Falling Edge Activation Timing: Figure 8.18 shows an example of normal mode ('5(4 ('5(4 transfer activated by the ('5(4 pin falling edge. DMA write Bus release Bus release DMA read DMA write Bus release DMA read ø Transfer Transfer Address bus...
Page 396 One block transfer One block transfer Bus release DMA read DMA write Bus release DMA read DMA write Bus release ø Transfer Transfer Address bus Transfer source Transfer source destination destination DMA control Idle Read Write Idle Read Write Idle Request clearance period Request clearance period Channel...
Page 397 Bus release DMA read DMA write Bus release DMA read DMA write Bus release ø Transfer Transfer Address bus Transfer source Transfer source destination destination DMA control Idle Read Write Idle Read Write Idle Channel Request clearance period Request clearance period Request Request Minimum 3 cycles...
Page 398: Exdmac Bus Cycles (Single Address Mode)
One block transfer One block transfer Bus release DMA read DMA write Bus release DMA read DMA write Bus release ø Transfer Transfer Address bus Transfer source Transfer source destination destination DMA control Idle Read Write Idle Read Write Idle Request clearance period Request clearance period Channel...
Page 399 DMA read DMA read DMA read DMA read ø Address bus Bus release Bus release Bus release Bus release Last Bus release transfer cycle Figure 8.22 Example of Single Address Mode (Byte Read) Transfer Figure 8.23 shows an example of transfer when (7(1' output is enabled, and word-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
Page 400 DMA write DMA write DMA write DMA write ø Address bus Bus release Bus release Bus release Bus release Last Bus release transfer cycle Figure 8.24 Example of Single Address Mode (Byte Write) Transfer Figure 8.25 shows an example of transfer when (7(1' output is enabled, and word-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
Page 401 Bus release DMA single Bus release DMA single Bus release ø Transfer source/ Transfer source/ Address bus destination destination DMA control Idle Single Idle Single Idle Request Request clearance period clearance period Channel Request Request Minimum 3 cycles Minimum 3 cycles Acceptance Acceptance resumed...
Page 402 Bus release DMA single Bus release DMA single Bus release ø Transfer source/ Transfer source/ Address bus destination destination DMA control Idle Single Idle Single Idle Request Request clearance period clearance period Channel Request Request Minimum 3 cycles Minimum 3 cycles Acceptance Acceptance resumed...
Page 403: Examples Of Operation Timing In Each Mode
8.4.11 Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one- cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer.
Page 404 ø pin 1 bus cycle Last transfer cycle EXDMA single EXDMA single EXDMA single CPU cycle CPU cycle CPU cycle CPU cycle Bus cycle transfer cycle transfer cycle transfer cycle External External space External space External space space operation Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode (CPU Cycles/Single Address Mode) ø...
Page 405 Figures 8.31 to 8.34 show operation timing examples for various conditions. ø pin Last transfer cycle EXDMA EXDMA EXDMA EXDMA EXDMA EXDMA Bus cycle Repeated CPU cycle CPU cycle CPU cycle read write read write read write External External External space space space...
Page 406 ø pin Last transfer cycle 1 bus cycle EXDMA EXDMA EXDMA EXDMA EXDMA Bus cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle single cycle single cycle single cycle single cycle single cycle External External External External External space space space...
Page 407 If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next EXDMA cycle. The ('5(4 pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 8.35 to 8.38 show operation timing examples for various conditions.
Page 408 ø pin 2 bus cycles Last transfer cycle EXDMA single EXDMA single CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle Bus cycle transfer cycle transfer cycle External External External External External External space space space space space space operation...
Page 409 ø pin Original channel Original channel 1 cycle 1 cycle 3 cycles Other channel EXDMA transfer EXDMA EXDMA EXDMA EXDMA Bus release Bus cycle transfer cycle cycle read write read write release release Other channel Other channel Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention with Another Channel/Dual Address Mode/Low Level Sensing External Request/Cycle Steal Mode/Block Transfer Mode: In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode.
Page 410 Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0) Rev. 1.0, 09/01, page 366 of 904...
Page 411 Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode (No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) Rev. 1.0, 09/01, page 367 of 904...
Page 412 Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0) Rev. 1.0, 09/01, page 368 of 904...
Page 413 Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1) Rev. 1.0, 09/01, page 369 of 904...
Page 414 Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode (CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1) Rev. 1.0, 09/01, page 370 of 904...
Page 415 Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode (Contention with Another Channel/Dual Address Mode/Low Level Sensing) Rev. 1.0, 09/01, page 371 of 904...
Page 416: Ending Dma Transfer
8.4.12 Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. Transfer End by 1 → → → → 0 Transition of EDTCR: When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0.
Page 417: Relationship Between Exdmac And Other Bus Masters
When transfer is aborted, register values are retained, and as the address registers indicate the next transfer addresses, transfer can be resumed by setting the EDA bit to 1 in EDMDR. If the BEF bit is 1 in EDMDR, transfer can be resumed from midway through a block. Hardware Standby Mode and Reset Input: The EXDMAC is initialized in hardware standby mode and by a reset.
Page 418 Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant channel, and can be sent to the interrupt controller independently. The relative priority order of the channels is determined by the interrupt controller (see table 8.4). Figure 8.45 shows the transfer end interrupt logic.
Page 419 Transfer end interrupt exception handling routine Transfer continuation Transfer restart after end of interrupt handling routine processing Clear IRF bit to 0 Change register settings End of interrupt handling Write 1 to EDA bit routine End of interrupt handling Change register settings routine (RTE instruction execution) Write 1 to EDA bit...
Page 420: Usage Notes
Usage Notes 8.6.1 EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel.
Page 421: Enabling Interrupt Requests When Irf = 1 In Edmdr
When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the ('5(4 pin from the previous end of transfer, etc. 8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be requested since EDIE = 1 and IRF = 1.
Page 422 Rev. 1.0, 09/01, page 378 of 904...
Page 423: Section 9 Data Transfer Controller (Dtc)
Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on- chip RAM.
Page 424: Register Configuration
Internal address bus On-chip Interrupt controller Interrupt request CPU interrupt Internal data bus request Legend MRA, MRB : DTC mode registers A and B CRA, CRB : DTC transfer count registers A and B : DTC source address register : DTC destination address register DTCERA to DTCERG : DTC enable registers A to G DTVECR...
Page 425: Dtc Mode Register A (Mra)
9.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Name Initial Value Description − Undefined Source Address Mode 1 and 0 − Undefined These bits specify an SAR operation after a data transfer. 0x: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0;...
Page 426: Dtc Mode Register B (Mrb)
9.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Name Initial Value Description − CHNE Undefined DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to 9.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER...
Page 427: Dtc Transfer Count Register B (Crb)
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00.
Page 428: Activation Sources
Bit Name Initial Value Description SWDTE DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended •...
Page 429: Location Of Register Information And Dtc Vector Table
Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Interrupt controller DTVECR Interrupt mask Figure 9.2 Block Diagram of DTC Activation Source Control Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range.
Page 430 Lower addresses Start address of register information Register information Chain transfer Register information for second transfer in case of chain transfer Four bytes Figure 9.3 Correspondence between DTC Vector Address and Register Information Note: * Not available in this LSI. Rev.
Page 431 Table 9.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Activation Activation Source Source Vector Number Vector Address DTCE* Priority Software Write to DTVECR DTVECR H'0400 + (DTVECR — High [6:0] × 2) External pin IRQ0 H'0420 DTCEA7 IRQ1 H'0422 DTCEA6...
Page 432: Operation
Origin of Activation Activation Source Source Vector Number Vector Address DTCE* Priority TMR_0 CMIA0 H'0490 DTCEE3 High CMIB0 H'0492 DTCEE2 TMR_1 CMIA1 H'0498 DTCEE1 CMIB1 H'049A DTCEE0 DMAC DMTEND0A H'04A0 DTCEF7 DMTEND0B H'04A2 DTCEF6 DMTEND1A H'04A4 DTCEF5 DMTEND1B H'04A6 DTCEF4 SCI_0 RXI0 H'04B2...
Page 433 Figure 9.4 shows a flowchart of DTC operation, and table 9.2 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? CHNS = 0? Transfer counter = 0...
Page 434: Normal Mode
Table 9.2 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL CHNE CHNS DISEL DTC Transfer — Not 0 — — — — Ends at 1st transfer — — — — — Ends at 1st transfer — — — —...
Page 435: Repeat Mode
Transfer Figure 9.5 Memory Mapping in Normal Mode 9.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Page 436: Block Transfer Mode
Repeat area Transfer Figure 9.6 Memory Mapping in Repeat Mode 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.5 lists the register function in block transfer mode.
Page 437: Chain Transfer
First block Block area Transfer Nth block Figure 9.7 Memory Mapping in Block Transfer Mode 9.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Page 438: Interrupts
Source Destination Register information CHNE=1 Register information DTC vector start address address Register information CHNE=0 Source Destination Figure 9.8 Operation of Chain Transfer 9.5.5 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1.
Page 439: Operation Timing
9.5.6 Operation Timing φ DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) φ DTC activation request request Data transfer Vector read Read Write Read Write Address...
Page 440: Number Of Dtc Execution States
9.5.7 Number of DTC Execution States Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of states required for each execution status. Table 9.6 DTC Execution Status Register Information Internal Vector Read Read/Write Data Read Data Write...
Page 441: Procedures For Using Dtc
Procedures for Using DTC 9.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3.
Page 442: Chain Transfer
3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts.
Page 443: Chain Transfer When Counter = 0
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU.
Page 444: Software Activation
Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data Upper 8 bits transfer register of DAR information Figure 9.12 Chain Transfer when Counter = 0 9.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation.
Page 445: Usage Notes
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6.
Page 446 Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. Rev. 1.0, 09/01, page 402 of 904...
Page 447: Section 10 I/O Ports
Section 10 I/O Ports Table 10.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip supporting modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
Page 448 Table 10.1 Port Functions Mode 7 Input/ Modes 1 Modes 2 Port Description Mode 4 Output and 5 and 6 EXPE = 1 EXPE = 0 Type Port General I/O port P17/PO15/TIOCB2/TCLKD/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ Schmitt- ('5$.6 also functioning TCLKD/('5$.6 TCLKD triggered as PPG outputs, input...
Page 449 Mode 7 Input/ Modes 1 Modes 2 Port Description Mode 4 Output and 5 and 6 EXPE = 1 EXPE = 0 Type Port General I/O port P53/$'75*/,546 Schmitt- also functioning triggered P52/SCK2/,545 as interrupt input P51/RxD2/,544 inputs, A/D when converter inputs, used as P50/TxD2/,543...
Page 450 Mode 7 Input/ Modes 1 Modes 2 Port Description Mode 4 Output and 5 and 6 EXPE = 1 EXPE = 0 Type Port General I/O port PA7/A23/,54: PA7/A23/,54: PA7/,54: Only PA4 also functioning to PA7 PA6/A22/,549 PA6/A22/,549 PA6/,549 as address PA5/A21/,548 PA5/A21/,548 PA5/,548...
Page 451 Mode 7 Input/ Modes 1 Modes 2 Port Description Mode 4 Output and 5 and 6 EXPE = 1 EXPE = 0 Type Port General I/O port PE7/D7 PE7/D7 PE7/D7 Built-in also functioning PE6/D6 PE6/D6 PE6/D6 as data I/Os input PE5/D5 PE5/D5 PE5/D5...
Page 452: Port 1
10.1 Port 1 Port 1 is an 8-bit I/O port that also has other functions. The port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 register (PORT1) 10.1.1 Port 1 Data Direction Register (P1DDR) The individual bits of P1DDR specify input or output for the pins of port 1.
Page 453: Port 1 Register (Port1)
10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. PORT1 cannot be modified. Bit Name Initial Value Description If a port 1 read is performed while P1DDR bits are —* set to 1, the P1DR values are read. If a port 1 read is —* performed while P1DDR bits are cleared to 0, the pin —*...
Page 454 Mode 7 (EXPE = 0) EDRAKE — TPU channel 2 (1) in table (2) in table below settings below P17DDR — NDER15 — — Pin function TIOCB2 output P17 input P17 output PO15 output TIOCB2 input* TCLKD input* Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000, B000, and B'01xx and IOB3 = 1. 2.
Page 455 • P16/PO14/TIOCA2/('5$.5 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH, bit EDRAKE in EDMDR_2 and bit P16DDR.
Page 456 TPU channel 2 settings MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011 IOA3 to IOA0 B'0000 B'0001 to B'0011 B'xx00 Other than B'xx00 B'0100 B'0101 to B'0111 B'1xxx CCLR1, CCLR0 — — — — Other B'10 than B'10 Output function —...
Page 457 • P15/PO13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH, and bit P15DDR.
Page 458 • P14/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH, and bit P14DDR. TPU channel 1 (1) in table (2) in table below...
Page 459 • P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH, and bit P13DDR.
Page 460 • P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH, and bit P12DDR.
Page 461 • P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0 and bits IOB3 to IOB0 in TIORH_0), bit NDER9 in NDERH, and bit P11DDR. TPU channel 0 (1) in table (2) in table below...
Page 462 • P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH, and bit P10DDR. TPU channel 0 (1) in table (2) in table below...
Page 463: Port 2
10.2 Port 2 Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 register (PORT2) 10.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2.
Page 464: Port 2 Register (Port2)
10.2.3 Port 2 Register (PORT2) PORT2 shows the pin states. PORT2 cannot be modified. Bit Name Initial Value Description If a port 2 read is performed while P2DDR bits are —* set to 1, the P2DR values are read. If a port 2 read is —* performed while P2DDR bits are cleared to 0, the pin —*...
Page 465: Pin Functions
10.2.4 Pin Functions Port 2 pins also function as PPG outputs, TPU I/Os, and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. • P27/PO7/TIOCB5/(,548) The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL, bit P27DDR, and bit ITS15 in ITSR.
Page 466 • P26/PO6/TIOCA5/(,5447) The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL, bit P26DDR, and bit ITS14 in ITSR. TPU channel 5 (1) in table (2) in table below...
Page 467 • P25/PO5/TIOCB4/(,5446, The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER5 in NDERL, bit P25DDR, and bit ITS13 in ITSR. TPU channel 4 (1) in table (2) in table below...
Page 468 • P24/PO4/TIOCA4/RXD4/,5445 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4 and bits IOA3 to IOA0 in TIOR_4), bit NDER4 in NDERL, bit RE in SCI_4, bit P24DDR, and bit ITS12 in ITSR. TPU channel 4 (1) in table (2) in table below...
Page 469 • P23/PO3/TIOCD3/TXD4/(,5444, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL, bit TE in SCR of SCI_4, bit P23DDR, and bit ITS11 in ITSR.
Page 470 • P22/PO2/TIOCC3/(,5443, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL, bit P22DDR, and bit ITS10 in ITSR. TPU channel 3 (1) in table (2) in table below...
Page 471 • P21/PO1/TIOCB3/(,54<, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL, bit P21DDR, and bit ITS9 in ITSR. TPU channel 3 (1) in table (2) in table below...
Page 472 • P20/PO0/TIOCA3/(,54;, The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL, bit P20DDR, and bit ITS8 in ITSR. TPU channel 3 (1) in table (2) in table below...
Page 473: Port 3
10.3 Port 3 Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 register (PORT3) •...
Page 474: Port 3 Data Register (P3Dr)
10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P35DR Output data for a pin is stored when the pin function is specified to a general purpose I/O.
Page 475: Port 3 Open Drain Control Register (P3Odr)
10.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls the output status for each port 3 pin. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P35ODR Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while P34ODR...
Page 476: Port Function Control Register 2 (Pfcr2)
10.3.5 Port Function Control Register 2 (PFCR2) P3ODR controls the I/O port. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be modified. $6 Output Enable ASOE Selects to enable or disable the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as $6 output pin /:5 Output Enable...
Page 477: Pin Functions
10.3.6 Pin Functions Port 3 pins also function as the pins for SCI I/Os, I C output, and a bus control signal output. The correspondence between the register specification and the pin functions is shown below. 2(, , , , /(CKE P35/SCK1/SCL0/(2( The pin function is switched as shown below according to the combination of the ICE bit in ICCRA of I...
Page 478 P34/SCK0/SCK4/SDA0 The pin function is switched as shown below according to the combination of bit ICE in ICCRA of I C_0, bit C/$ in SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 — — — CKE0 — —...
Page 479 P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_1 and bit P31DDR. P31DDR — Pin function P31 input P31 output* TxD1 output* Note: * NMOS open-drain output when P31ODR = 1. P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_0 and bit P30DDR.
Page 480: Port 4
10.4 Port 4 Port 4 is an 8-bit input-only port. Port 4 has the following register. • Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows port 4 pin states. PORT4 cannot be modified. Bit Name Initial Value Description...
Page 481 P45/AN5 Pin function AN5 input P44/AN4 Pin function AN4 input P43/AN3 Pin function AN3 input P42/AN2 Pin function AN2 input P41/AN1 Pin function AN1 input P40/AN0 Pin function AN0 input Rev. 1.0, 09/01, page 437 of 904...
Page 482: Port 5
10.5 Port 5 Port 5 is a 4-bit I/O port. The port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) • Port 5 register (PORT5) 10.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5.
Page 483: Port 5 Register (Port5)
10.5.3 Port 5 Register (PORT5) PORT5 shows the pin states. PORT5 cannot be modified. Bit Name Initial Value Description — Undefined Reserved Undefined values are read from these bits. —* If bits P53 to P50 are read while P5DDR bits are set to 1, the P5DR values are read.
Page 484 ,545 ,545 ,545 P52/SCK2/,545 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR. CKE1 — CKE0 — —...
Page 485: Port 6
10.6 Port 6 Port 6 is a 6-bit I/O port that also has other functions. The port 6 has the following registers. • Port 6 data direction register (P6DDR) • Port 6 data register (P6DR) • Port 6 register (PORT6) 10.6.1 Port 6 Data Direction Register (P6DDR) The individual bits of P6DDR specify input or output for the pins of port 6.
Page 486: Port 6 Register (Port6)
10.6.3 Port 6 Register (PORT6) PORT6 shows the pin states. PORT6 cannot be modified. Bit Name Initial Value Description — Undefined — Reserved These bits are reserved, if read they will return an — Undefined — undefined value. —* If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read.
Page 487 '$&.3/,5445 ,5445 '$&.3 '$&.3 ,5445 ,5445 P64/TMO0/'$&.3 The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit P64DDR, and bit ITS12 in ITSR. SAE1 OS3 to OS0 All 0...
Page 488 '5(44/,54< ,54< '5(44 '5(44 ,54< ,54< P61/TMRI1/'5(44 The pin function is switched as shown below according to the combination of bit P61DDR and bit ITS9 in ITSR. P61DDR Pin function P61 input P61 output TMRI1 input '5(44 input ,54< interrupt input* Notes: 1.
Page 489: Port 8
10.7 Port 8 Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) • Port 8 register (PORT8) 10.7.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8.
Page 490: Port 8 Data Register (P8Dr)
10.7.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P85DR Output data for a pin is stored when the pin function is specified to a general purpose I/O.
Page 491: Pin Functions
10.7.4 Pin Functions Port 8 pins also function as interrupt inputs and EXDMAC I/Os. The correspondence between the register specification and the pin functions is shown below. ,548, , , , /('$&.6 ('$&.62 2 2 2 SC K 3 ,548 ,548 ('$&.6 ('$&.6...
Page 492 ('$&.5 ('$&.5 ('$&.5/(,547 ,547 ,547 ,547, , , , P84/('$&.5 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR. Modes 1, 2, 4, 5, 6, 7 (EXPE = 1) P84DDR —...
Page 493 Mode 7 (EXPE = 0) ETENDE — P83DDR — Pin function P83 input P83 output RXD3input ,546 interrupt input* ,546 input when ITS3 = 1. Note: ,545 ,545 ,545, , , , /(7(1'5 (7(1'5 (7(1'5 (7(1'5 P82/(,545 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR.
Page 494 ,544 ,544 ,544, , , , /('5(46 ('5(46 ('5(46 ('5(462 2 2 2 TX D 3 P81/(,544 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_3, bit P81DDR and bit ITS1 in ITSR. P81DDR —...
Page 495: Port 9
10.8 Port 9 Port 9 is an 8-bit input-only port. Port 4 has the following register. • Port 9 register (PORT4) 10.8.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows port 4 pin states. PORT9 cannot be modified. Bit Name Initial Value Description...
Page 496 P95/AN13/DA3 Pin function AN13 input DA3 output P94/AN12/DA2 Pin function AN12 input DA2 output P93/AN11 Pin function AN11 input P92/AN10 Pin function AN10 input P91/AN9 Pin function AN9 input P90/AN8 Pin function AN8 input Rev. 1.0, 09/01, page 452 of 904...
Page 497: Port A
10.9 Port A Port A is an 8-bit I/O port that also has other functions. The port A has the following registers. • Port A data direction register (PADDR) • Port A data register (PADR) • Port A register (PORTA) •...
Page 498: Port A Data Direction Register (Paddr)
10.9.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Name Initial Value Description •...
Page 499: Port A Data Register (Padr)
10.9.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Name Initial Value Description PA7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PA6DR PA5DR PA4DR PA3DR...
Page 500: Port A Mos Pull-Up Control Register (Papcr)
10.9.4 Port A MOS Pull-Up Control Register (PAPCR) PAPCR controls the MOS input pull-up function. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and all the bits are valid in modes 4 and 7. Bit Name Initial Value Description PA7PCR...
Page 501 Bit Name Initial Value Description A23E Address 23 Enable Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1 A22E Address 22 Enable Enables or disables output for address output 22 (A22). 0: DR output when PA6DDR = 1 1: A22 output when PA6DDR = 1 A21E...
Page 502: Pin Functions
10.9.7 Pin Functions Port A pins also function as the pins for address outputs and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. ,54: ,54:, PA6/A22/,549 ,54: ,549 ,549, PA5/A21/,548 ,549 ,548 ,548 ,548 PA7/A23/,54: The pin function is switched as shown below according to the operating mode, bit EXPE, bits...
Page 503: Port A Mos Input Pull-Up States
PA3/A19, PA2/A18, PA1/A17, PA20/A16 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A19E to A16E, and bit PADDR. Operating 1, 2, 5, mode EXPE — — AxxE — — PADDR — Address Address Address function...
Page 504: Port B
10.10 Port B Port B is an 8-bit I/O port that also has other functions. The port B has the following registers. • Port B data direction register (PBDDR) • Port B data register (PBDR) • Port B register (PORTB) •...
Page 505: Port B Data Register (Pbdr)
10.10.2 Port B Data Register (PBDR) PBDR is stores output data for the port B pins. Bit Name Initial Value Description PB7DR An output data for a pin is stored when the pin function is specified to a general purpose I/O. PB6DR PB5DR PB4DR...
Page 506: Port B Mos Pull-Up Control Register (Pbpcr)
10.10.4 Port B MOS Pull-Up Control Register (PBPCR) PBPCR controls the on/off state of MOS input pull-up of port B. PBPCR is valid in modes 4 and Bit Name Initial Value Description PB7PCR When PBDDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pull-up PB6PCR for that pin.
Page 507: 10.10.6 Port B Mos Input Pull-Up States
10.10.6 Port B MOS Input Pull-Up States Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 508: Port C
10.11 Port C Port C is an 8-bit I/O port that also has other functions. The port C has the following registers. • Port C data direction register (PCDDR) • Port C data register (PCDR) • Port C register (PORTC) •...
Page 509: Port C Data Register (Pcdr)
10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Name Initial Value Description PC7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PC6DR PC5DR PC4DR PC3DR...
Page 510: Port C Mos Pull-Up Control Register (Pcpcr)
10.11.4 Port C MOS Pull-Up Control Register (PCPCR) PCPCR controls the on/off state of MOS input pull-up of port C. PCPCR is valid in modes 4 and Bit Name Initial Value Description PC7PCR When PCDDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pull-up PC6PCR for that pin.
Page 511: 10.11.6 Port C Mos Input Pull-Up States
10.11.6 Port C MOS Input Pull-Up States Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 512: Port D
10.12 Port D Port D is an 8-bit I/O port that also has other functions. The port D has the following registers. • Port D data direction register (PDDDR) • Port D data register (PDDR) • Port D register (PORTD) •...
Page 513: Port D Register (Portd)
10.12.3 Port D Register (PORTD) PORTD shows port D pin states. PORTD cannot be modified. Bit Name Initial Value Description If a port D read is performed while PDDDR bits are —* set to 1, the PDDR values are read. If a port D read —* is performed while PDDDR bits are cleared to 0, the —*...
Page 514: 10.12.6 Port D Mos Input Pull-Up States
PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PDDDR. Operating 1, 2, 4, 5, 6 mode EXPE — PDDDR — — Pin function Data I/O PD input PD output...
Page 515: Port E
10.13 Port E Port E is an 8-bit I/O port that also has other functions. The port E has the following registers. • Port E data direction register (PEDDR) • Port E data register (PEDR) • Port E register (PORTE) •...
Page 516: Port E Data Register (Pedr)
10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Name Initial Value Description PE7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PE6DR PE5DR PE4DR PE3DR...
Page 517: Port E Pull-Up Control Register (Pepcr)
10.13.4 Port E Pull-up Control Register (PEPCR) PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus mode. Bit Name Initial Value Description PE7PCR When PEDDR = 0 (input port), the input pull-up MOS of the input pin is on when the corresponding bit is PE6PCR set to 1.
Page 518: 10.13.6 Port E Mos Input Pull-Up States
10.13.6 Port E MOS Input Pull-Up States Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in 8-bit bus mode. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 519: Port F
10.14 Port F Port F is an 8-bit I/O port that also has other functions. The port F has the following registers. For details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2). •...
Page 520 Bit Name Initial Value Description • PF7DDR 1/0* Modes 1, 2, 4, 5, and 6 Pin PF7 functions as the ø output pin when the PF6DDR corresponding PFDDR bit is set to 1, and as an input PF5DDR port when the bit is cleared to 0. PF4DDR Pin PF6 functions as the $6 output pin when ASOE is set to 1.
Page 521: Port F Data Register (Pfdr)
10.14.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Name Initial Value Description PF7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PF6DR PF5DR PF4DR PF3DR...
Page 522: 10.14.4 Pin Functions
10.14.4 Pin Functions Port F pins also function as the pins for external interrupt inputs, bus control signal I/Os, and system clock outputs (ø). The correspondence between the register specification and the pin functions is shown below. PF7/ø The pin function is switched as shown below according to bit PF7DDR. Operating 1, 2, 4 to 7 mode...
Page 523 PF4/+:5 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PF4DDR. Operating 1, 2, 4, 5, 6 mode EXPE — PF4DDR — — +:5 output +:5 output Pin function PF4 input PF4 output PF3//:5 The pin function is switched as shown below according to the operating mode, bit EXPE, bit LWROE, and bit PF3DDR.
Page 524 /&$6 /&$6 /&$6/'40/ '40/ '40/ '40/* ,5448 ,5448 ,5448 PF2//&$6 /,5448 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR.
Page 525 8&$6 8&$6 8&$6/,5447 ,5447 ,5447/'408 ,5447 '408 '408 '408* PF1/8&$6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR. Operating 1, 2, 4, 5, 6 mode EXPE —...
Page 526: Port G
10.15 Port G Port G is a 7-bit I/O port that also has other functions. The port G has the following registers. • Port G data direction register (PGDDR) • Port G data register (PGDR) • Port G register (PORTG) •...
Page 527 Bit Name Initial Value Description — — Reserved • PG6DDR Modes 1, 2, 4, 5, and 6 Pins PG6 to PG4 function as bus control input/output PG5DDR pins (%5(42, %$&., and %5(4) when the PG4DDR appropriate bus controller settings are made. PG3DDR Otherwise, these pins are I/O ports, and their functions can be switched with PGDDR.
Page 528: Port G Data Register
10.15.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Name Initial Value Description — — Reserved This bit is always read as 0, and cannot be modified. PG6DR An output data for a pin is stored when the pin function is specified to a general purpose I/O.
Page 529: Port Function Control Register 0 (Pfcr0)
10.15.4 Port Function Control Register 0 (PFCR0) PFCR0 performs I/O port control. Bit Name Initial Value Description CS7E CS7 to CS0 Enable These bits enable or disable the corresponding &6Q CS6E output. CS5E 0: Pin is designated as I/O port CS4E 1: Pin is designated as &6Q output pin CS3E...
Page 530 %$&. %$&. %$&. PG5/%$&. The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, and bit PG5DDR. Operating 1, 2, 4, 5, 6 mode EXPE — BRLE — PG5DDR — — %$&. %$&. function input output...
Page 531 &66 &66 &66/5$66 5$66 5$66/&$6 5$66 &$6 &$6 &$6*, PG2/&65 &65 &65 &65/5$65 5$65 5$65/5$6 5$65 PG3/&66 The pin function is switched as shown below according to the operating mode, bit EXPE, bit CSnE, bits RMTS2 to RMTS0, and bit PGnDDR. Operating 1, 2, 4, 5, 6 mode...
Page 532: Port H
10.16 Port H Port H is a 4-bit I/O port that also has other functions. The port H has the following registers. For details on the port function control register 0, refer to section 10.15.4, Port Function Control Register 0 (PFCR0), and for details on the port function control register 2, refer to section 10.3.5, Port Function Control Register 2 (PFCR2).
Page 533 Bit Name Initial Value Description — — Reserved • PH3DDR Modes 1, 2, 4, 5, 6, and 7 (when EXPE = 1) When the 2( output enable bit (OEE) and 2( output select bit PH2DDR (OES) are set to 1, pin PH3 functions as the 2( output pin. PH1DDR Otherwise, when bit CS7E is set to 1, pin PH3 functions as a &6 PH0DDR...
Page 534: Port H Data Register (Phdr)
10.16.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit Name Initial Value Description — — Reserved These bits are reserved; they are always read as 0 and cannot be modified. PH3DR Output data for a pin is stored when the pin function is specified to a general purpose I/O.
Page 535: 10.16.4 Pin Functions
10.16.4 Pin Functions Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. &6:/2( 2(/CKE* ,54:) &6: &6: ,54: ,54: PH3/&6: /(,54: The pin function is switched as shown below according to the operating mode, bit EXPE, bit OEE, bit OES, bit CS7E, and bit PH3DDR.
Page 536 5$68/SDRAMφ φ φ φ * &68/5$68 &68 &68 5$68 5$68 PH1/&68 The pin function is switched as shown below according to the operating mode, DCTL pin, bit EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR. DCTL* Operating 1, 2, 4, 5, 6 —...
Page 537: Section 11 16-Bit Timer Pulse Unit (Tpu)
Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 11.1 and figure 11.1, respectively.
Page 538 Table 11.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock ø/1 ø/1 ø/1 ø/1 ø/1 ø/1 ø/4 ø/4 ø/4 ø/4 ø/4 ø/4 ø/16 ø/16 ø/16 ø/16 ø/16 ø/16 ø/64 ø/64 ø/64 ø/64 ø/64 ø/64...
Page 539 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 activation compare compare compare compare compare compare match or match or match or match or match or match or input capture input capture input capture input capture input capture input capture DMAC...
Page 540 Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5 Channel 5: TGI5A TGI5B TCI5V TCI5U Clock input Internal clock: ø/1 ø/4...
Page 541: Input/Output Pins
11.2 Input/Output Pins Table 11.2 Pin Configuration Channel Symbol Function TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin...
Page 542: Register Descriptions
11.3 Register Descriptions The TPU has the following registers in each channel. • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) • Timer I/O control register H_0 (TIORH_0) • Timer I/O control register L_0 (TIORL_0) • Timer interrupt enable register_0 (TIER_0) •...
Page 543: Timer Control Register (Tcr)
• Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) • Timer general register C_3 (TGRC_3) • Timer general register D_3 (TGRD_3) • Timer control register_4 (TCR_4) • Timer mode register_4 (TMDR_4) • Timer I/O control register _4 (TIOR_4) •...
Page 544 Bit Name Initial Value Description CCLR2 Counter Clear 2 to 0 CCLR1 These bits select the TCNT counter clearing source. CCLR0 See tables 11.3 and 11.4 for details. CKEG1 Clock Edge 1 and 0 CKEG0 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g.
Page 545 Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* TCNT clearing disabled...
Page 546 Table 11.5 TPSC2 to TPSC0 (Channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 547 Table 11.7 TPSC2 to TPSC0 (Channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/1024...
Page 548 Table 11.9 TPSC2 to TPSC0 (Channel 4) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/1024 Counts on TCNT5 overflow/underflow...
Page 549: Timer Mode Register (Tmdr)
11.3.2 Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Name Initial Value Description –...
Page 550: Timer I/O Control Register (Tior)
Table 11.11 MD3 to MD0 Bit 3 Bit 2 Bit 1 Bit 0 MD3* MD2* Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 551 TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Initial Bit Name Value Description IOB3 I/O Control B3 to B0 IOB2 Specify the function of TGRB. IOB1 For details, see tables 11.12, 11.14, 11.15, 11.16, IOB0 11.18, and 11.19. IOA3 I/O Control A3 to A0 IOA2 Specify the function of TGRA.
Page 552 Table 11.12 TIORH_0 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 553 Table 11.13 TIORL_0 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 554 Table 11.14 TIOR_1 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 555 Table 11.15 TIOR_2 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 556 Table 11.16 TIORH_3 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_3 IOB3 IOB2 IOB1 IOB0 Function TIOCB3 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 557 Table 11.17 TIORL_3 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_3 IOD3 IOD2 IOD1 IOD0 Function TIOCD3 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 558 Table 11.18 TIOR_4 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_4 IOB3 IOB2 IOB1 IOB0 Function TIOCB4 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 559 Table 11.19 TIOR_5 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_5 IOB3 IOB2 IOB1 IOB0 Function TIOCB5 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 560 Table 11.20 TIORH_0 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 561 Table 11.21 TIORL_0 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCC0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 562 Table 11.22 TIOR_1 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 563 Table 11.23 TIOR_2 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 564 Table 11.24 TIORH_3 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_3 IOA3 IOA2 IOA1 IOA0 Function TIOCA3 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 565 Table 11.25 TIORL_3 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_3 IOC3 IOC2 IOC1 IOC0 Function TIOCC3 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 566 Table 11.26 TIOR_4 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_4 IOA3 IOA2 IOA1 IOA0 Function TIOCA4 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 567 Table 11.27 TIOR_5 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_5 IOA3 IOA2 IOA1 IOA0 Function TIOCA5 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 568: Timer Interrupt Enable Register (Tier)
11.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Name Initial value Description TTGE A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Page 569 Bit Name Initial value Description TGIEC TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Page 570: Timer Status Register (Tsr)
11.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Name Initial value Description TCFD Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5.
Page 571 Bit Name Initial value Description TGFD R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Page 572: Timer Counter (Tcnt)
Bit Name Initial value Description TGFB R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register •...
Page 573: Timer General Register (Tgr)
11.3.7 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers.
Page 574: Timer Synchronous Register (Tsyr)
11.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Name Initial value Description –...
Page 575: Operation
11.4 Operation 11.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Page 576 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 577 Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC activation Figure 11.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match.
Page 578 2. Examples of waveform output operation Figure 11.6 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
Page 579 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Page 580: Synchronous Operation
Counter cleared by TIOCB TCNT value input (falling edge) H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 11.9 Example of Input Capture Operation 11.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting).
Page 581 Synchronous operation selection Set synchronous operation Synchronous presetting Synchronous clearing Set TCNT Clearing source generation channel? Select counter Set synchronous clearing source counter clearing Start count Start count <Synchronous presetting> <Counter clearing> <Synchronous clearing> [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters.
Page 582: Buffer Operation
Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 11.11 Example of Synchronous Operation 11.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers.
Page 583 Compare match signal Timer general Buffer register Comparator TCNT register Figure 11.12 Compare Match Buffer Operation • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register.
Page 584 Examples of Buffer Operation: 1. When TGR is an output compare register Figure 11.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 585: Cascaded Operation
TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA H'0532 H'0F07 H'09FB TGRA H'0532 H'0F07 TGRC Figure 11.16 Example of Buffer Operation (2) 11.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter.
Page 586 Example of Cascaded Operation Setting Procedure: Figure 11.17 shows an example of the setting procedure for cascaded operation. Set bits TPSC2 to TPSC0 in the channel 1 Cascaded operation (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.
Page 587: Pwm Modes
TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 11.19 Example of Cascaded Operation (2) 11.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR.
Page 588 Table 11.30 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TIOCB0 TGRC_0 TIOCC0 TIOCC0 TGRD_0 TIOCD0 TGRA_1 TIOCA1 TIOCA1 TGRB_1 TIOCB1 TGRA_2 TIOCA2 TIOCA2 TGRB_2 TIOCB2 TGRA_3 TIOCA3 TIOCA3 TGRB_3 TIOCB3...
Page 589 Example of PWM Mode Setting Procedure: Figure 11.20 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 590 TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 11.21 Example of PWM Mode Operation (1) Figure 11.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
Page 591 Figure 11.23 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 592: Phase Counting Mode
11.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 593 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 11.25 shows an example of phase counting mode 1 operation, and table 11.32 summarizes the TCNT up/down-count conditions.
Page 594 2. Phase counting mode 2 Figure 11.26 shows an example of phase counting mode 2 operation, and table 11.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count...
Page 595 3. Phase counting mode 3 Figure 11.27 shows an example of phase counting mode 3 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 596 4. Phase counting mode 4 Figure 11.28 shows an example of phase counting mode 4 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 597 Phase Counting Mode Application Example: Figure 11.29 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Page 598: Interrupts
11.5 Interrupts There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 599 Table 11.36 TPU Interrupts Interrupt DMAC Channel Name Interrupt Source Flag Activation Activation TGI0A TGRA_0 input capture/compare match TGFA_0 Possible Possible TGI0B TGRB_0 input capture/compare match TGFB_0 Possible Not possible TGI0C TGRC_0 input capture/compare match TGFC_0 Possible Not possible TGI0D TGRD_0 input capture/compare match TGFD_0 Possible Not possible...
Page 600: Dtc Activation
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Page 601: Operation Timing
11.9 Operation Timing 11.9.1 Input/Output Timing TCNT Count Timing: Figure 11.30 shows TCNT count timing in internal clock operation, and figure 11.31 shows TCNT count timing in external clock operation. φ Falling edge Rising edge Internal clock TCNT input clock TCNT N –...
Page 602 φ TCNT input clock N + 1 TCNT Compare match signal TIOC pin Figure 11.32 Output Compare Output Timing Input Capture Signal Timing: Figure 11.33 shows input capture signal timing. φ Input capture input Input capture signal N + 1 N + 2 TCNT N + 2...
Page 603 φ Compare match signal Counter clear signal H'0000 TCNT Figure 11.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal H'0000 TCNT Figure 11.35 Counter Clear Timing (Input Capture) Buffer Operation Timing: Figures 11.36 and 11.37 show the timings in buffer operation. φ...
Page 604: Interrupt Signal Timing
φ Input capture signal N + 1 TCNT TGRA, N + 1 TGRB TGRC, TGRD Figure 11.37 Buffer Operation Timing (Input Capture) 11.9.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 11.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing.
Page 605 φ Input capture signal TCNT TGF flag TGI interrupt Figure 11.39 TGI Interrupt Timing (Input Capture) TCFV Flag/TCFU Flag Setting Timing: Figure 11.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 11.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing.
Page 606 φ TCNT input clock TCNT H'0000 H'FFFF (underflow) Underflow signal TCFU flag TCIU interrupt Figure 11.41 TCIU Interrupt Setting Timing Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it.
Page 607: Usage Notes
DTC/DMAC DTC/DMAC read cycle write cycle φ Destination Source address Address address Status flag Interrupt request signal Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation 11.10 Usage Notes 11.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted.
Page 608: 11.10.3 Caution On Cycle Setting
Phase Phase diffe- diffe- Pulse width Pulse width Overlap Overlap rence rence TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 11.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated).
Page 609: 11.10.5 Contention Between Tcnt Write And Increment Operations
TCNT write cycle ø TCNT address Address Write signal Counter clearing signal H'0000 TCNT Figure 11.45 Contention between TCNT Write and Clear Operations 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Page 610: 11.10.6 Contention Between Tgr Write And Compare Match
11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written.
Page 611: 11.10.8 Contention Between Tgr Read And Input Capture
TGR write cycle ø Buffer register Address address Write signal Compare match signal Buffer register write data Buffer register Figure 11.48 Contention between Buffer Register Write and Compare Match 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Page 612: 11.10.9 Contention Between Tgr Write And Input Capture
11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.50 shows the timing in this case. TGR write cycle ø...
Page 613: 11.10.11 Contention Between Overflow/Underflow And Counter Clearing
Buffer register write cycle ø Buffer register Address address Write signal Input capture signal TCNT Buffer register Figure 11.51 Contention between Buffer Register Write and Input Capture 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence.
Page 614: 11.10.12 Contention Between Tcnt Write And Overflow/Underflow
11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.53 shows the operation timing when there is contention between TCNT write and overflow.
Page 615: Section 12 Programmable Pulse Generator (Ppg)
Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently.
Page 616 Compare match signals NDERH NDERL Control logic PO15 Pulse output PO14 PO13 pins, group 3 Internal PO12 PODRH NDRH PO11 data bus PO10 Pulse output pins, group 2 Pulse output pins, group 1 PODRL NDRL Pulse output pins, group 0 Legend : PPG output mode register : PPG output control register...
Page 617: Input/Output Pins
12.2 Input/Output Pins Table 12.1 summarizes the I/O pins of the PPG. Table 12.1 PPG I/O Pins Pin Name Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output Group 2 pulse output PO10 Output Output Output Output...
Page 618: Next Data Enable Registers H, L (Nderh, Nderl)
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1. NDERH Bit Name Initial Value Description NDER15 Next Data Enable 15 to 8 NDER14 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the...
Page 619: Output Data Registers H, L (Podrh, Podrl)
12.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. PODRH Bit Name Initial Value Description POD15 Output Data Register 15 to 8...
Page 620: Next Data Registers H, L (Ndrh, Ndrl)
12.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Page 621 Bit Name Initial Value Description — — Reserved 1 is always read and write is disabled. NDR11 Next Data Register 11 to 8 NDR10 The register contents are transferred to the corresponding PODRH bits by the output trigger NDR9 specified with PCR. NDR8 NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same...
Page 622: Ppg Output Control Register (Pcr)
Bit Name Initial Value Description — — Reserved 1 is always read and write is disabled. NDR3 Next Data Register 3 to 0 NDR2 The register contents are transferred to the corresponding PODRL bits by the output trigger NDR1 specified with PCR. NDR0 12.3.4 PPG Output Control Register (PCR)
Page 623: Ppg Output Mode Register (Pmr)
Bit Name Initial Value Description G0CMS1 Group 0 Compare Match Select 1 and 0 G0CMS0 Select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 12.3.5 PPG Output Mode Register (PMR)
Page 624 Bit Name Initial Value Description G3NOV Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) G2NOV Group 2 Non-Overlap...
Page 625: Operation
12.4 Operation Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Page 626: Output Timing
12.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø...
Page 627: Sample Setup Procedure For Normal Pulse Output
12.4.2 Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled) Select TGR functions [2] Set the PPG output trigger period Set TGRA value [3] Select the counter clock source with TPU setup...
Page 628: Example Of Normal Pulse Output (Example Of Five-Phase Pulse Output)
12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH PO15 PO14 PO13 PO12 PO11 Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)
Page 629: Non-Overlapping Pulse Output
12.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • NDR bits are always transferred to PODR bits at compare match A. • At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1.
Page 630: Sample Setup Procedure For Non-Overlapping Pulse Output
Compare match A Compare match B Write to NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR Write to NDR here here Do not write Do not write to NDR here to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing 12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output...
Page 631: Example Of Non-Overlapping Pulse Output (Example Of Four-Phase Complementary Non-Overlapping Output)
12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary non- overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 Time NDRH PODRH Non-overlap margin PO15 PO14 PO13...
Page 632: Inverted Pulse Output
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. 4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95...
Page 633: Pulse Output Triggered By Input Capture
12.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.
Page 634 Rev. 1.0, 09/01, page 590 of 904...
Page 635: Section 13 8-Bit Timers (Tmr)
Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Page 636 Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1). External clock source Internal clock sources TMR_0 TMR_1 TMCI0 Ø/8 Ø/8 Ø/64 Ø/64 TMCI1 Ø/8192 Ø/8192 Clock 1 Clock select Clock 0 TCORA_0 TCORA_1 Compare match A1 Compare match A0 Comparator A_0 Comparator A_1...
Page 637: Input/Output Pins
13.2 Input/Output Pins Table 13.1 summarizes the pins of the 8-bit timer module. Table 13.1 Pin Configuration Channel Name Symbol Function Timer output pin TMO0 Output Outputs at compare match Timer clock input pin TMCI0 Input Inputs external clock for counter Timer reset input pin TMRI0 Input...
Page 638: Time Constant Register A (Tcora)
13.3.2 Time Constant Register A (TCORA) TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1.
Page 639 Bit Name Initial Value Description CMIEB Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled CMIEA Compare Match Interrupt Enable A Selects whether CMFA interrupt requests...
Page 640: Timer Control/Status Register (Tcsr)
Table 13.2 Clock Input to TCNT and Count Condition Channel Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description TMR_0 Clock input disabled Internal clock, counted at falling edge of ø/8 Internal clock, counted at falling edge of ø/64 Internal clock, counted at falling edge of ø/8192 Count at TCNT_1 overflow signal* TMR_1...
Page 641 Bit Name Initial Value Description CMFA R/(W)* Compare Match Flag A [Setting condition] • Set when TCNT matches TCORA [Clearing conditions] • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA • When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 R/(W)* Timer Overflow Flag...
Page 642 Bit Name Initial Value Description Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output)
Page 643: Operation
Bit Name Initial Value Description — Reserved This bit is always read as 1 and cannot be modified. Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
Page 644: Operation Timing
TCNT H'FF Counter clear TCORA TCORB H'00 Figure 13.2 Example of Pulse Output 13.5 Operation Timing 13.5.1 TCNT Incrementation Timing Figure 13.3 shows the count timing for internal clock input. Figure 13.4 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges.
Page 645: Timing Of Cmfa And Cmfb Setting When Compare-Match Occurs
ø External clock input pin Clock input to TCNT TCNT N–1 Figure 13.4 Count Timing for External Clock Input 13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match.
Page 646: Timing Of Compare Match Clear
ø Compare match A signal Timer output pin Figure 13.6 Timing of Timer Output 13.5.4 Timing of Compare Match Clear TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 13.7 shows the timing of this operation. ø...
Page 647: Timing Of Overflow Flag (Ovf) Setting
ø External reset input pin Clear signal TCNT N–1 H'00 Figure 13.8 Timing of Clearance by External Reset 13.5.6 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.9 shows the timing of this operation.
Page 648: Compare Match Count Mode
[1] Setting of compare match flags • The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs. • The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. [2] Counter clear specification •...
Page 649: A/D Converter Activation
Table 13.3 8-Bit Timer Interrupt Sources Name Interrupt Source Interrupt Flag DTC Activation Priority CMIA0 TCORA_0 compare match CMFA Possible High CMIB0 TCORB_0 compare match CMFB Possible OVI0 TCNT_0 overflow Not possible CMIA1 TCORA_1 compare match CMFA Possible High CMIB1 TCORB_1 compare match CMFB Possible...
Page 650: Usage Notes
13.8 Usage Notes 13.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.10 shows this operation.
Page 651: Contention Between Tcor Write And Compare Match
TCNT write cycle by CPU ø Address TCNT address Internal write signal TCNT input clock TCNT Counter write data Figure 13.11 Contention between TCNT Write and Increment 13.8.3 Contention between TCOR Write and Compare Match During the T state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13.12.
Page 652: Contention Between Compare Matches A And B
TCOR write cycle by CPU ø Address TCOR address Internal write signal TCNT TCOR TCOR write data Compare match signal Inhibited Figure 13.12 Contention between TCOR Write and Compare Match 13.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.4.
Page 653: Switching Of Internal Clocks And Tcnt Operation
13.8.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 13.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected.
Page 654 Table 13.5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from Clock before low to low* switchover Clock after switchover TCNT clock TCNT CKS bit write Switching from Clock before low to high* switchover...
Page 655: Mode Setting With Cascaded Connection
Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high Clock before to high switchover Clock after switchover TCNT clock TCNT CKS bit write Notes: 1. Includes switching from low to stop, and from stop to low. 2.
Page 656 Rev. 1.0, 09/01, page 612 of 904...
Page 657: Section 14 Watchdog Timer
Section 14 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (:'729)) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer.
Page 658: Input/Output Pin
Overflow ø/2 Interrupt ø/64 WOVI control ø/128 (interrupt request ø/512 Clock signal) Clock ø/2048 select ø/8192 ø/32768 Reset ø/131072 Internal reset signal* control Internal clock sources RSTCSR TCNT TSCR Module bus interface Legend : Timer control/status register TCSR : Timer counter TCNT : Reset control/status register RSTCSR...
Page 659: Timer Counter (Tcnt)
14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. 14.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Rev.
Page 660 Bit Name Initial Value Description R/(W)* Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows in interval timer mode (changes from H’FF to H’00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Page 661: Reset Control/Status Register (Rstcsr)
Bit Name Initial Value Description 111: Clock ø/131072 (frequency: 1.68 s) Note: * Only a write of 0 is permitted, to clear the flag. 14.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal.
Page 662: Operation
14.4 Operation 14.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer mode, set the WT/,7 and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the :'729) signal is output.
Page 663: Interval Timer Mode
TCNT count Overflow H'FF Time H'00 WOVF=1 H'00 written H'00 written TME=1 to TCNT WDTOVF TME=1 to TCNT internal reset are generated WDTOVF signal 132 states * Internal reset signal * 518 states Legend : Timer mode select bit : Timer enable bit Notes: 1.
Page 664: Interrupts
TCNT count Overflow Overflow Overflow Overflow H'FF Time H'00 WOVI WOVI WOVI WOVI WT/ =0 TME=1 Legend WOVI: Interval timer interrupt request generation Figure 14.3 Operation in Interval Timer Mode 14.5 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
Page 665: Contention Between Timer Counter (Tcnt) Write And Increment
To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer instruction cannot perform writing to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0 to the WOVF bit, satisfy the lower condition shown in figure 14.4.
Page 666: Changing Value Of Cks2 To Cks0
TCNT write cycle Next cycle ø Address Internal write signal TCNT input clock TCNT Counter write data Figure 14.5 Contention between TCNT Write and Increment 14.6.3 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation.
Page 667: System Reset By Wdtovf Signal
System Reset by :'729) :'729) Signal :'729) :'729) 14.6.6 If the :'729) output signal is input to the 5(6 pin, the chip will not be initialized correctly. Make sure that the :'729) signal is not input logically to the 5(6 pin. To reset the entire system by means of the :'729) signal, use the circuit shown in figure 14.6.
Page 668 Rev. 1.0, 09/01, page 624 of 904...
Page 669: Section 15 Serial Communication Interface (Sci, Irda)
Section 15 Serial Communication Interface (SCI, IrDA) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 670 • Average transfer rate generator (only for H8S/2378R series): The following transfer rate can be selected (SCI_2 only) 115.152 or 460.606 kbps at 10.667 MHz operation 115.196, 460.784 or 720 kbps at 16 MHz operation 720 kbps at 32 MHz operation Clocked Synchronous mode •...
Page 671 Internal Module data bus data bus SCMR φ Baud rate φ/4 generator SEMR φ/16 Transmission/ φ/64 reception control Clock Parity generation Average transfer Parity check rate generator External clock (SCI_2) 10.667 MHz operation • 115.152 kbps • 460.606 kbps 16 MHz operation Legend •...
Page 672: Input/Output Pins
15.2 Input/Output Pins Table 15.1 shows the serial pins for each SCI channel. Table 15.1 Pin Configuration Channel Pin Name* Function SCK0 Channel 0 clock input/output RxD0/IrRxD Input Channel 0 receive data input (normal/IrDA) TxD0/IrTxD Output Channel 0 transmit data output (normal/IrDA) SCK1 Channel 1 clock input/output RxD1...
Page 673 • Bit rate register_0 (BRR_0) • IrDA control register_0 (IrCR_0) • Receive shift register_1 (RSR_1) • Transmit shift register_1 (TSR_1) • Receive data register_1 (RDR_1) • Transmit data register_1 (TDR_1) • Serial mode register_1 (SMR_1) • Serial control register_1 (SCR_1) •...
Page 674: Receive Shift Register (Rsr)
• Smart card mode register_4 (SCMR_4) • Bit rate register_4 (BRR_4) 15.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 675 Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Name Initial Value Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length.
Page 676 Bit Name Initial Value Description CKS1 Clock Select 1 and 0: CKS0 These bits select the clock source for the on-chip baud rate generator. 00: ø clock (n = 0) 01: ø/4 clock (n = 1) 10: ø/16 clock (n = 2) 11: ø/64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 15.3.9, Bit...
Page 677: Serial Control Register (Scr)
Bit Name Initial Value Description BCP1 Basic Clock Pulse 1 and 0 BCP0 These bits select the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, refer to section 15.7.4, Receive Data...
Page 678 Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Name Initial Value Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0.
Page 679 Bit Name Initial Value Description MPIE Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited.
Page 680 Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Name Initial Value Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0.
Page 681 Bit Name Initial Value Description TEIE Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. CKE1 Clock Enable 1 and 0 CKE0 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode.
Page 682: Serial Status Register (Ssr)
15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode.
Page 683 Bit Name Initial Value Description ORER R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
Page 684 Bit Name Initial Value Description R/(W)* Framing Error Indicates that a framing error occurred while receiving in asynchr onous m ode and the reception has ended abnormally. [Setting condition] • When the stop bit is 0 I n 2- st op- bi t m ode, onl y t he f i r st st op bi t i s checked f or a val ue of 0;...
Page 685 Bit Name Initial Value Description R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchr onous m ode and the reception has ended abnormally. [Setting condition] • When a parity error is detected during reception I f a par i t y er r or occur s, t he r ecei ve dat a i s t r ansf er r ed t o R D R but t he R D R F f l ag i s not set .
Page 686 Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Name Initial Value Description TDRE R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and data writing to TDR is enabled.
Page 687 Bit Name Initial Value Description ORER R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
Page 688 Bit Name Initial Value Description R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchr onous m ode and the reception has ended abnormally. [Setting condition] • When a parity error is detected during reception I f a par i t y er r or occur s, t he r ecei ve dat a i s t r ansf er r ed t o R D R but t he R D R F f l ag i s not set .
Page 689: Smart Card Mode Register (Scmr)
Bit Name Initial Value Description [Clearing conditions] • When 0 is written to TEND after reading TEND • When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR Multiprocessor Bit This bit is not used in Smart Card interface mode. MPBT Multiprocessor Bit Transfer Write 0 to this bit in Smart Card interface mode.
Page 690: Bit Rate Register (Brr)
Bit Name Initial Value Description SMIF Smart Card Interface Mode Select This bit is set to 1 to make the SCI operate in Smart Card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart card interface mode 15.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate.
Page 691 Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in Smart Card interface mode.
Page 692 Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency ø (MHz) 3.6864 4.9152 Bit Rate Error Error Error Error (bit/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16...
Page 693 Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency ø (MHz) 9.8304 12.288 Bit Rate Error Error Error Error (bit/s) –0.26 –0.25 0.03 0.08 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 1200 0.00 0.16...
Page 694 Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4) Operating Frequency ø (MHz) 19.6608 Bit Rate Error Error Error Error (bit/s) –0.12 3 0.31 –0.25 3 –0.02 0.16 0.00 0.16 –0.47 0.16 0.00 0.16 0.15 0.16 0.00 0.16 –0.47 1200 0.16...
Page 695 Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Maximum Bit ø (MHz) Rate (bit/s) ø (MHz) Rate (bit/s) 62500 312500 2.097152 65536 375000 2.4576 76800 12.288 384000 93750 437500 3.6864 115200 14.7456 460800 125000 500000 4.9152 153600 17.2032 537600...
Page 696 Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency ø (MHz) Bit Rate (bit/s) — — — — — — — — — — — — 2.5 k 10 k 25 k 50 k 100 k 250 k 500 k —...
Page 697 Operating Frequency ø (MHz) Bit Rate (bit/s) 2.5 k 10 k 25 k 50 k 100 k 250 k 500 k — — — — — — 2.5 M — — — — — — Legend Blank: Cannot be set. —: Can be set, but there will be a degree of error.
Page 698 Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency ø (MHz) 7.1424 10.00 10.7136 13.00 Bit Rate Error Error Error Error (bit/s) 9600 0.00 8.99 Operating Frequency ø...
Page 699: Irda Control Register (Ircr)
15.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit Name Initial Value Description IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output. 0: Pins TxD0/IrTxD and RxD0/IrRxD function as TxD0 and RxD0 1: Pins TxD0/IrTxD and RxD0/IrRxD function as IrTxD and IrRxD IrCKS2 IrDA Clock Select 2 to 0...
Page 700: Serial Extension Mode Register (Semr)
15.3.11 Serial Extension Mode Register (SEMR) SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by selecting the average transfer rate. Bit Name Initial Value Description — Undefined — Reserved If these bits are read, an undefined value will be returned and cannot be modified.
Page 701 Bit Name Initial Value Description ACS2 Asynchronous clock source selection (valid when ACS1 CKS1 = 1 in asynchronous mode) ACS0 Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS.
Page 702: Operation In Asynchronous Mode
15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Page 703 Table 15.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data P STOP 8-bit data P STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP...
Page 704: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 705: Clock
15.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/$ bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
Page 706: Sci Initialization (Asynchronous Mode)
15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change.
Page 707: Data Transmission (Asynchronous Mode)
15.4.5 Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 708 [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start of transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 709: Serial Data Reception (Asynchronous Mode)
15.4.6 Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 710 ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception. Table 15.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* ORER Receive Data Receive Error Type Lost Overrun error Transferred to RDR...
Page 711 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 712 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 PER = 1? Parity error handling Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 15.9 Sample Serial Reception Data Flowchart (2) Rev.
Page 713: Multiprocessor Communication Function
15.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 714 Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB= 1) (MPB= 0) ID transmission cycle = Data transmission cycle = receiving station data transmission to...
Page 715: Multiprocessor Serial Data Transmission
15.5.1 Multiprocessor Serial Data Transmission Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Page 716 SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start of transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and Read TDRE flag in SSR transmission is enabled. SCI status check and transmit TDRE = 1? data write:...
Page 717: Multiprocessor Serial Data Reception
15.5.2 Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 718 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. ID reception cycle: Set MPIE bit in SCR to 1 Set the MPIE bit in SCR to 1. Read ORER and FER flags in SSR SCI status check, ID reception and comparison: FER ∨...
Page 719 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 720: Operation In Clocked Synchronous Mode
15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Page 721: Sci Initialization (Clocked Synchronous Mode)
15.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change.
Page 722: Serial Data Transmission (Clocked Synchronous Mode)
15.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 723 Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request generated and TDRE flag request generated request generated cleared to 0 in TXI interrupt handling routine 1 frame...
Page 724 [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start of transmission pin. [2] SCI status check and transmit data Read TDRE flag in SSR write: Read SSR and check that the TDRE flag is set to 1, then write transmit data TDRE = 1? to TDR and clear the TDRE flag to 0.
Page 725: Serial Data Reception (Clocked Synchronous Mode)
15.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR.
Page 726 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. [2] [3] Receive error handling: Read ORER flag in SSR If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to ORER = 1?
Page 727: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Page 728 SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the Start of transmission/reception receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR SCI status check and transmit data write: Read SSR and check that the...
Page 729: Operation In Smart Card Interface Mode
15.7 Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting.
Page 730 When there is no parity error Transmitting station output When a parity error occurs Transmitting station output Receiving station Legend output : Start bit : Data bits D0 to D7 : Parity bit : Error signal Figure 15.22 Normal Smart Card Interface Data Format Data transfer with the types of IC cards (direct convention and inverse convention) are performed as described in the following.
Page 731: Block Transfer Mode
15.7.3 Block Transfer Mode Operation in block transfer mode is the same as that in normal Smart Card interface, except for the following points. • In reception, though the parity check is performed, no error signal is output even if an error is detected.
Page 732: Initialization
372 clocks 186 clocks 371 0 Internal basic clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 15.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Bit Rate) 15.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below.
Page 733: Data Transmission (Except For Block Transfer Mode)
15.7.6 Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation when the SCI is in transmit mode.
Page 734 Transfer nth transfer frame Retransferred frame frame n+1 (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR Transfer to TSR from TDR Transfer to TSR from TDR from TDR TEND...
Page 735 Start Initialization Start transmission ERS = 0? Error processing TEND = 1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted ? ERS = 0? Error processing TEND = 1? Clear TE bit to 0 Figure 15.28 Example of Transmission Processing Flow Rev.
Page 736: Serial Data Reception (Except For Block Transfer Mode)
15.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 15.29 illustrates the retransfer operation when the SCI is in receive mode. 1.
Page 737: Clock Output Control
Start Initialization Start reception ORER = 0 and PER = 0 Error processing RDRF = 1? Read RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit to 0 Figure 15.30 Example of Reception Processing Flow 15.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and...
Page 738 When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. Powering On: To secure the clock duty from power-on, the following switching procedure should be followed.
Page 739: Irda Operation
15.8 IrDA Operation When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system.
Page 740 When the serial data is 1, no pulse is output. UART frame Data Stop Start Transmit Receive IR frame Data Stop Start Pulse width 1.6 µs to 3/16 bit cycle cycle Figure 15.34 IrDA Transmit/Receive Operations Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI.
Page 741 Table 15.12 Settings of Bits IrCKS2 to IrCKS0 Bit Rate (bps) (Above) /Bit Period × × × × 3/16 (µs) (Below) Operating Frequency 2400 9600 19200 38400 57600 115200 ø (MHz) 78.13 19.53 9.77 4.88 3.26 1.63 — 2.097152 — 2.4576 —...
Page 742: Sci Interrupts
15.9 SCI Interrupts 15.9.1 Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Page 743: Interrupts In Smart Card Interface Mode
Table 15.13 SCI Interrupt Sources DMAC Channel Name Interrupt Source Interrupt Flag Activation Activation Priority ERI0 Receive Error ORER, FER, PER Not possible Not possible High RXI0 Receive Data Full RDRF Possible Possible TXI0 Transmit Data Empty TDRE Possible Possible TEI0 Transmission End TEND...
Page 744 Table 15.14 Interrupt Sources DMAC Channel Name Interrupt Source Interrupt Flag Activation Activation Priority ERI0 Receive Error, detection ORER, PER, ERS Not possible Not possible High RXI0 Receive Data Full RDRF Possible Possible TXI0 Transmit Data Empty TEND Possible Possible ERI1 Receive Error, detection ORER, PER, ERS...
Page 745: Usage Notes
DMAC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC or DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. 15.10 Usage Notes 15.10.1 Module Stop Mode Setting...
Page 746: 15.10.6 Restrictions On Use Of Dmac Or Dtc
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR.
Page 747 Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode or software standby mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission.
Page 748 Figure 15.39 shows a sample flowchart for mode transition during reception. <Transmission> [1] Data being transmitted is interrupted. All data transmitted? After exiting software standby mode, normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, Read TEND flag in SSR but note that if the DTC has been activated, the remaining data in...
Page 749 Transition Exit from End of to software software Start of transmission transmission standby standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 15.37 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission)
Page 750 <Reception> Read RDRF flag in SSR [1] Receive data being received RDRF = 1 becomes invalid. Read receive data in RDR RE = 0 Transition to software [2] Includes module stop mode. standby mode Exit from software standby mode Change operating mode? Initialization RE = 1...
Page 751: Section 16 I C Bus Interface2 (Iic2) (Option)
For the mask ROM version, ‘W’ is added to the model name of the product that uses optional functions. For example: HD6432268WTE For the F-ZTAT version, product model names do not depend on optional functions. When using optional functions, contact the Hitachi sales office. This LSI has a two-channel I C bus interface, The I...
Page 752 Transfer clock generation circuit Transmission/ ICCRA reception control circuit Output ICCRB control ICMR Noise canceler ICDRT Output ICDRS control Address Noise canceler comparator ICDRR Bus state decision circuit Arbitration ICSR decision circuit ICEIR Interrupt Interrupt request Legend: generator ICCRA C bus control register A ICCRB C bus control register B ICMR...
Page 753: Input/Output Pins
SCL in SDA in (Master) SCL in SCL in SDA in SDA in (Slave 1) (Slave 2) Figure 16.2 External Circuit Connections of I/O Pins 16.2 Input/Output Pins Table 16.1 summarizes the input/output pins used by the I C bus interface. Table 16.1 I C Bus Interface Pins Name...
Page 754: C Bus Control Register A (Iccra)
• I C bus status register_0 (ICSR_0) • I C bus slave address register_0 (SAR_0) • I C bus transmit data register_0 (ICDRT_0) • I C bus receive data register_0 (ICDRR_0) • I C bus shift register_0 (ICDRS_0) • I C bus control register A_1 (ICCRA_1) •...
Page 755 Bit Bit Name Initial Value R/W Description C Bus Interface Enable 0: This module is halted. 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) RCVD Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read.
Page 756: C Bus Control Register B (Iccrb)
Table 16.2 Transfer Rate Bit3 Bit2 Bit1 Bit0 Clock Transfer Rate φ φ φ φ =8MHz φ φ φ φ =10MHz φ φ φ φ =20MHz φ φ φ φ =25MHz φ φ φ φ =33MHz CKS3 CKS2 CKS1 CKS0 φ/28 286kHz 357kHz...
Page 757: C Bus Mode Register (Icmr)
Bit Bit Name Initial Value R/W Description Start Condition/Stop Condition Prohibit The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
Page 758 Bit Bit Name Initial Value R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first WAIT Wait Insertion Bit This bit selects whether to insert a wait after data transfer except for the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks.
Page 759: C Bus Interrupt Enable Register (Icier)
Bit Bit Name Initial Value R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. The data is transferred with one addition acknowledge bit.
Page 760 Bit Bit Name Initial Value R/W Description Receive interrupt enable This bit enables or disables the receive data full interrupt request (RXI) when a received data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0.
Page 761: C Bus Status Register (Icsr)
16.3.5 C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags and status. Bit Bit Name Initial Value R/W Description TDRE Transmit Data Register Empty [Setting condition] • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty [Clearing conditions] •...
Page 762 Bit Bit Name Initial Value R/W Description differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] • If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode •...
Page 763: Slave Address Register (Sar)
16.3.6 Slave address register (SAR) SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Page 764: Operation
16.4 Operation 16.4.1 C Bus Format Figure 16.3 shows the I C bus formats. Figure 16.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits. (a) I C bus format (FS = 0) DATA n: transfer bit count (n = 1 to 8)
Page 765: Master Transmit Operation
Stop condition. The master device drives SDA from low to high while SCL is high. 16.4.2 Master Transmit Operation In I C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 21.5 and 21.6.
Page 766 (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (master output) Slave address (slave output) TDRE TEND ICDRT Address + R/ Data 1 Data 2 ICDRS Address + R/ Data 1 User [4] Write data to ICDRT (second byte).
Page 767: Master Receive Operation
16.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 21.7 and 21.8. The reception procedure and operations in master receive mode are shown below.
Page 768 Master transmit mode Master receive mode (master output) (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (slave output) TDRE TEND RDRF ICDRS Data 1 ICDRR Data 1 User [3] Read ICDRR [2] Read ICDRR (dummy read) processing...
Page 769: Slave Transmit Operation
16.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 21.9 and 21.10. The transmission procedure and operations in slave transmit mode are described below.
Page 770 Slave receive mode Slave transmit mode (master output) (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (slave output) TDRE TEND Data 1 Data 2 Data 3 ICDRT ICDRS Data 1...
Page 771: Slave Receive Operation
Slave receive mode Slave transmit mode (master output) (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (slave output) TDRE TEND ICDRT ICDRS Data n ICDRR User [5] Clear TDRE [4] Read ICDRR (dummy read) processing [3] Clear TEND...
Page 772 before clearing RDRF, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR. (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7...
Page 773: Noise Canceler
16.4.6 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 774 Start Initialize Read BBSY in ICCRB Test the status of the SCL and SDA lines. BBSY=0 ? Select master transmit mode. Set MST = 1 and TRS Start condition issuance. = 1 in ICCRA. Write BBSY = 1 Select transmit data for the first byte (slave address + R/W), and SCP = 0.
Page 775 Mater receive mode Clear TEND, select master receive mode, and then clear TDRE. Clear TEND in ICSR Set acknowledge to the transmitting device. Set TRS = 0 (ICCRA) Dummy read ICDDR Clear TDRE of ICSR Wait for 1 byte to be received. Set ACKBT = 0 (ICIER) Check if (last receive - 1) Dummy read ICDRR...
Page 776 [1] Clear the flag AAS. Slave transmit mode Clear AAS in ICSR [2] Set transmit data for ICDRT (except for the last data), and clear TDRE to 0. Write transmit data [3] Wait the empty of ICDRT. in ICDRT [4] Set the last byte of the transmit data, and clear TDRE to 0. Read TDRE in ICSR [5] Wait the transmission end of the last byte.
Page 777 Slave receive mode [1] Clear the flag AAS. Clear AAS in ICSR [2] Set the acknowledge for the transmit device. Set ACKBT=0 in ICIER [3] Dummy read ICDRR. Dummy read ICDRR [4] Wait the reception end of 1 byte. [5] Judge the (last receive - 1). Read RDRF in ICSR [6] Read the received data, and clear RDRF to 0.
Page 778: Interrupt Request
16.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost. Table 16.3 shows the contents of each interrupt request. Table 16.3 Interrupt Requests Interrupt Request Abbreviation Interrupt Condition Transmit Data Empty...
Page 779: Bit Synchronous Circuit
16.6 Bit Synchronous Circuit In master mode, • When SCL is driven to low by the slave device • When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up resistance) This module has a possibility that high level period may be short in the two states described above.
Page 780 Rev. 1.0, 09/01, page 736 of 904...
Page 781: Section 17 A/D Converter
Section 17 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. The block diagram of A/D converter is shown in figure 17.1. 17.1 Features • 10-bit resolution •...
Page 782: Input/Output Pins
Module data bus Internal data bus AVCC Vref 10-bit D/A AVSS – Comparator Control circuit Sample-and- hold circuit AN10 AN11 AN12 ADI interrupt signal AN13 AN14 Conversion start AN15 trigger from 8-bit timer or TPU Legend ADDRD: A/D data register D ADCR: A/D control register ADDRE: A/D data register E...
Page 783: Register Description
The sixteen analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and channel set 1 (AN8 to AN15). Table 17.1 A/D Converter Pins Pin Name Symbol Function Analog power supply pin Input Analog block power supply Analog ground pin Input Analog block ground...
Page 784: A/D Data Registers A To H (Addra To Addrh)
• A/D data register G (ADDRG) • A/D data register H (ADDRH) • A/D control/status register (ADCSR) • A/D control register (ADCR) 17.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion.
Page 785: A/D Control/Status Register (Adcsr)
17.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Name Initial Value Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends in single mode • When A/D conversion ends on all specified channels in scan mode [Clearing conditions]...
Page 786 Bit Name Initial Value Description Channel select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. Set the input channel when conversion is stopped (ADST = 0). When SCANE = 0 and SCANS = X 0000: AN0 1000: AN8 0001: AN1...
Page 787: A/D Control Register (Adcr)
17.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion start by an external trigger input. Bit Name Initial Value Description TRGS1 Timer Trigger Select 1 and 0 TRGS0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger (TPU)
Page 788: Operation
17.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D conversion.
Page 789: Input Sampling And A/D Conversion Time
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. 17.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit.
Page 790: External Trigger Input Timing
CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion — — — — start delay time Input sampling —...
Page 791: Interrupts
17.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables an ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. The DTC or DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software.
Page 792 Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 17.4 A/D Conversion Precision Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 17.5 A/D Conversion Precision Definitions Rev.
Page 793: Usage Notes
17.7 Usage Notes 17.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode.
Page 794: Setting Range Of Analog Power Supply And Other Pins
Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 17.7.4 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of the device may be adversely affected. •...
Page 795 Vref AN0 to AN15 0.1 µF Notes: Values are reference values. 10 µF 0.01 µF 2. R : Input impedance Figure 17.7 Example of Analog Input Protection Circuit Table 17.6 Analog Pin Specifications Item Unit Analog input capacitance — Permissible signal source impedance —...
Page 796 Rev. 1.0, 09/01, page 752 of 904...
Page 797: Section 18 D/A Converter
Section 18 D/A Converter 18.1 Features D/A converter features are listed below. • 8-bit resolution • Six output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode •...
Page 798: Input/Output Pins
18.2 Input/Output Pins Table 18.1 summarizes the input and output pins of the D/A converter. Table 18.1 Pin Configuration Pin Name Symbol Function Analog power pin Input Analog power Analog ground pin Input Analog ground Reference voltage pin Vref Input Reference voltage of D/A converter Analog output pin 0 Output...
Page 799: D/A Control Registers 01, 23, And 45 (Dacr01, Dacr23, Dacr45)
18.3.2 D/A Control Registers 01, 23, and 45 (DACR01, DACR23, DACR45) DACR01, DACR23, and DACR45 control the operation of the D/A converter. DACR01, DACR23, and DACR45 control the operation of channels 0 and 1, channels 2 and 3, and channels 4 and 5, respectively.
Page 800 Table 18.2 Control of D/A Conversion Bit 5 Bit 7 Bit 6 DAOE1 DAOE0 Description D/A conversion disabled Channel 0 D/A conversion enabled, channel1 D/A conversion disabled Channel 1 D/A conversion enabled, channel0 D/A conversion disabled Channel 0 and 1 D/A conversions enabled D/A conversion disabled Channel 0 and 1 D/A conversions enabled Rev.
Page 801 DACR23 Bit Name Initial Value Description DAOE1 D/A Output Enable 3 Controls D/A conversion and analog output. 0: Analog output (DA3) is disabled 1: Channel 3 D/A conversion is enabled; analog output (DA3) is enabled DAOE0 D/A Output Enable 2 Controls D/A conversion and analog output.
Page 802 Table 18.3 Control of D/A Conversion Bit 5 Bit 7 Bit 6 DAOE3 DAOE2 Description D/A conversion disabled Channel 2 D/A conversion enabled, channel3 D/A conversion disabled Channel 3 D/A conversion enabled, channel2 D/A conversion disabled Channel 2 and 3 D/A conversions enabled D/A conversion disabled Channel 2 and 3 D/A conversions enabled Rev.
Page 803 DACR45 Bit Name Initial Value Description DAOE1 D/A Output Enable 5 Controls D/A conversion and analog output. 0: Analog output (DA5) is disabled 1: Channel 5 D/A conversion is enabled; analog output (DA5) is enabled DAOE0 D/A Output Enable 4 Controls D/A conversion and analog output.
Page 804: Operation
Table 18.3 Control of D/A Conversion Bit 5 Bit 7 Bit 6 DAOE3 DAOE2 Description D/A conversion disabled Channel 4 D/A conversion enabled, channel5 D/A conversion disabled Channel 5 D/A conversion enabled, channel4 D/A conversion disabled Channel 4 and 5 D/A conversions enabled D/A conversion disabled Channel 4 and 5 D/A conversions enabled 18.4...
Page 805: Usage Notes
DADR0 DACR01 DADR0 DACR01 write cycle write cycle write cycle write cycle ø Address DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion Conversion result 2 High-impedance state result 1 DCONV DCONV Legend : D/A conversion time DCONV Figure 18.2 Example of D/A Converter Operation 18.5 Usage Notes 18.5.1...
Page 806 Rev. 1.0, 09/01, page 762 of 903...
Page 807: Section 19 Ram
Section 19 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR).
Page 808 Rev. 1.0, 09/01, page 764 of 904...
Page 809: Section 20 Flash Memory (F-Ztat Version)
Section 20 Flash Memory (F-ZTAT Version) The features of the flash memory included in the flash memory version are summarized below. The block diagram of the flash memory is shown in figure 20.1. 20.1 Features • Size Product Classification ROM Size ROM Address H8S/2378 Series HD64F2377...
Page 810: Mode Transitions
Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating Bus interface/controller Mode pins mode EBR1 EBR2 RAMER SYSCR Flash memory Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2: Erase block register 2 RAMER:...
Page 811 The differences between boot mode and user program mode are shown in table 20.1. Figure 20.3 shows boot mode. Figure 20.4 shows user program mode. Reset state User mode (on-chip ROM enabled) SWE = 0 MD0 = 0, MD1 = 0, SWE = 1 MD2 = 0, P50 = 0, Programmer...
Page 812 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the chip (originally incorporated in the chip) is programming control program and new started and the programming control program in application program beforehand in the host.
Page 813 1. Initial state 2. Programming/erase control program transfer (1) the program that will transfer the When user program mode is entered, user programming/ erase control program to on-chip software confirms this fact, executes the transfer RAM should be written into the flash memory by program in the flash memory, and transfers the the user beforehand.
Page 814: Block Configuration
20.3 Block Configuration Figure 20.5 shows the block configuration of 384-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 384- kbyte flash memory is divided into 64 kbytes (5 blocks), 32 kbytes (1 block), and 4 kbyte (8 blocks).
Page 815 Programming unit: 128 bytes H'000000 H'000001 H'000002 H'00007F Erase unit 4 kbytes H'000FFF H'001000 H'001001 H'001002 Programming unit: 128 bytes H'00107F Erase unit 4 kbytes H'001FFF H'00207F Programming unit: 128 bytes H'002000 H'002001 H'002002 Erase unit 4 kbytes H'002FFF H'003000 H'003001 H'003002 H'00307F...
Page 816: Input/Output Pins
20.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 20.2. Table 20.2 Pin Configuration Pin Name Function Input Reset Input Sets this LSI’s operating mode Input Sets this LSI’s operating mode Input Sets this LSI’s operating mode Input Sets operating mode in programmer mode Input...
Page 817: Flash Memory Control Register 2 (Flmcr2)
Bit Name Initial Value Description This bit is reserved. This bit is always read as 0 in — modes 1 and 2. This bit is always read as 1 in modes 3 to 7. The initial value should not be changed.
Page 818: Erase Block Register 1 (Ebr1)
Bit Name Initial Value Description FLER Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See 20.9.3 Error Protection, for details. —...
Page 819 Bit Name Initial Value Description 7, 6 — Reserved The initial value should not be changed. EB13 When this bit is set to 1, 64 kbytes of EB13 are to be erased. EB12 When this bit is set to 1, 64 kbytes of EB12 are to be erased.
Page 820: Ram Emulation Register (Ramer)
20.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified.
Page 821 Bit Name Initial Value Description — Reserved These bits always read 0. — Reserved The initial value should not be changed. RAMS RAM Select Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory block are in the program/erase- protect state.
Page 822: On-Board Programming Modes
20.6 On-Board Programming Modes There are two modes for programming/erasing the flash memory: boot mode and programmer mode. Boot mode is used to program/erase the flash memory on the board. Programmer mode is used to program/erase the flash memory with the PROM programmer. There is also user program mode which is used to program/erase the flash memory on the board.
Page 823 of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system clock frequency of this LSI within the ranges listed in table 20.6. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses H’FFA800 to H’FFBFFF is the area to which the programming control program is transferred from the host.
Page 824 Table 20.5 Boot Mode Operation Host Operation Communication Contents LSI Operation Processing Contents Processing Contents Branches to boot program at reset-start. Boot program initiation H'00, H'00 . . . H'00 Continuously transmits data H'00 • Measures low-level period of receive data H'00. at specified bit rate.
Page 825: User Program Mode
20.6.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the program/erase program or a program which provides the program/erase program from external memory.
Page 826: Flash Memory Emulation In Ram
20.7 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables RAM to be overlapped onto the part of flash memory area so that data to be programmed to flash memory can be emulated in the on-chip RAM in real time.
Page 827 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode.
Page 828: Flash Memory Programming/Erasing
20.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Page 829 Write pulse application subroutine Start of programming Write pulse application Start Perform programming in the erased state. Do not perform additional programming Enable WDT Set SWE bit in FLMCR1 on previously programmed addresses. Wait (x) µs Set PSU bit in FLMCR1 Wait (y) µs Store 128-byte program data in program data area and reprogram data area...
Page 830: Erase/Erase-Verify
20.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 20.10 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2).
Page 831 Start Set SWE bit in FLMCR1 Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) µs Start of erase Set E bit in FLMCR1 Wait (z) ms n ← n + 1 Clear E bit in FLMCR1 Halt erase Wait (α) µs...
Page 832: Program/Erase Protection
20.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 20.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or standby mode.
Page 833: Programmer Mode
In programmer mode, a PROM programmer can perform programming/erasing via a socket adapter, just like for a discrete flash memory. Use a PROM programmer which supports the Hitachi 512-kbyte flash memory on-chip MCU device type (FZTAT512V3A). A 12-MHz input clock is needed.
Page 834 Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. 2. Reset the flash memory before turning on/off the power. When applying or disconnecting Vcc power, fix the 5(6 pin low and place the flash memory in the hardware protection state.
Page 835 Programming/ erasing possible Wait time: 100 µs Wait time: x φ Min 0 µs OSC1 MD2 to MD0 SWE set SWE cleared SWE bit (1) Boot Mode Programming/ erasing Wait time: 100 µs possible Wait time: x φ Min 0 µs OSC1 MD2 to MD0 SWE set...
Page 836 Wait time: x Wait time: x Wait time: x Wait time: x Programming/erasing Programming/erasing Programming/erasing Programming/erasing possible possible possible possible φ OSC1 MD2 to MD0 RESW cleared SWE bit User User User User User mode User Mode Boot Mode mode program mode program...
Page 837: Section 21 Clock Pulse Generator
Section 21 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (ø) and internal clocks. The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider. Figure 21.1 shows a block diagram of the clock pulse generator. PLLCR SCKCR STC0, STC1...
Page 838 Bit Name Initial Value Description PSTOP ø Clock Output Disable Controls ø output. Normal Operation 0: ø output 1: Fixed high Sleep Mode 0: ø output 1: Fixed high Software Standby Mode 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance All module clock stop mode...
Page 839: Pll Control Register (Pllcr)
Bit Name Initial Value Description SCK2 System Clock Select 2 to 0 SCK1 Select the division ratio. SCK0 000: 1/1 001: 1/2 010: 1/4 011: 1/8 100: 1/16 101: 1/32 11X: Setting prohibited X: Don’t care 21.1.2 PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the PLL circuit.
Page 840: Connecting A Crystal Oscillator
21.2.1 Connecting a Crystal Oscillator A crystal oscillator can be connected as shown in the example in figure 21.2. Select the damping resistance R according to table 20.1. An AT-cut parallel-resonance type should be used. Figure 21.3 shows the equivalent circuit of the crystal oscillator. Use a crystal oscillator that has the characteristics shown in table 21.2.
Page 841: External Clock Input
21.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 21.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode.
Page 842: Pll Circuit
Table 21.3 External Clock Input Conditions = 3.0 V to 3.6 V Test Item Symbol Unit Conditions External clock input — Figure 21.5 low pulse width External clock input — high pulse width External clock rise time — External clock fall time —...
Page 843: Frequency Divider
3. The target value is set in bits STC1 and STC0, and a transition is made to software standby mode. 4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. 5. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS3 to STS0.
Page 844: Notes On Board Design
21.5.3 Notes on Board Design When using the crystal oscillator, place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 21.6. Avoid Signal A Signal B This LSI...
Page 845: Section 22 Power-Down Modes
Section 22 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
Page 846 Table 22.1 Operating Modes High Clock All Module Software Hardware Operating State Speed Division Sleep Module Clock Stop Standby Standby Mode Mode Mode Stop Mode Mode Mode Mode Clock pulse generator Functions Functions Functions Functions Functions Halted Halted Instruction Functions Functions Halted Functions...
Page 847 * The active or halted state can be selected by means of the MSTP0 bit in MSTPCR. pin = low Hardware Reset state standby mode pin = high pin = low pin = high SSBY = 0 SLEEP instruction Sleep mode High-speel mode (Internal clock is PLL MSTPCR =...
Page 848: Register Descriptions
22.1 Register Descriptions The registers relating to the power-down mode are shown below. For details on the system clock control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR). • System clock control register (SCKCR) • Standby control register (SBYCR) •...
Page 849 Bit Name Initial Value Description — — Reserved — — These bits are always read as 0. The initial value should not be changed. STS3 Standby Timer Select 3 to 0 STS2 These bits select the time the MCU waits for the STS1 clock to stabilize when software standby mode is STS0...
Page 850: Module Stop Control Registers H And L (Mstpcrh, Mstpcrl)
22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode. MSTPCRH Bit Name Initial Value Module...
Page 851: Extension Module Stop Control Registers H And L (Exmstpcrh, Exmstpcrl)
22.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) EXMSTPCR performs all-module-clocks-stop mode control with MSTPCR. When entering all-module-clocks-stop mode, set EXMSTPCR to H’FFFF. Otherwise, set EXMSTPCR to H’FFFD. EXMSTPCRH Bit Name Initial Value Module — Reserved Read/write is enabled. 1 should be written in writing.
Page 852: Operation
22.2 Operation 22.2.1 Clock Division Mode When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and on-chip peripheral functions all operate on the operating clock (1/2, 1/4, 1/8, 1/16, or 1/32) specified by bits SCK2 to SCK0.
Page 853: Software Standby Mode
22.2.3 Software Standby Mode Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O ports, are retained.
Page 854 Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS3 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time. Table 22.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0.
Page 855: Hardware Standby Mode
In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin.
Page 856: Module Stop Mode
Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the 67%< pin and the 5(6 pin. When the 67%< pin is driven high while the 5(6 pin is low, the reset state is set and clock oscillation is started. Ensure that the 5(6 pin is held low until the clock oscillator stabilizes (for details on the oscillation stabilization time, refer to table 22.2).
Page 857: All-Module-Clocks-Stop Mode
The module registers which are set in module stop mode cannot be read or written to. 22.2.6 All-Module-Clocks-Stop Mode When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip peripheral functions controlled by MSTPCR (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF), or for all the on-chip peripheral functions except the 8-bit timer (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), executing a SLEEP instruction while the SSBY bit in SBYCR is cleared to 0 will cause all the on-chip peripheral functions (except the 8-bit timer and watchdog timer), the bus controller,...
Page 858: Usage Notes
22.4 Usage Notes 22.4.1 I/O Port Status In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 22.4.2 Current Dissipation during Oscillation Stabilization Standby Period Current dissipation increases during the oscillation stabilization standby period.
Page 859: Section 23 List Of Registers
Section 23 List of Registers The address list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) •...
Page 860 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States C bus control register A_0 ICCRA_0 H'FD58 IIC2_0 C bus control register B_0 ICCRB_0 H'FD59 IIC2_0 C bus mode register_0 ICMR_0 H'FD5A IIC2_0 C bus interrupt enable register_0 ICIER_0 H'FD5B IIC2_0...
Page 861 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Interrupt priority register B IPRB H'FE02 Interrupt priority register C IPRC H'FE04 Interrupt priority register D IPRD H'FE06 Interrupt priority register E IPRE H'FE08 Interrupt priority register F IPRF H'FE0A Interrupt priority register G...
Page 862 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Port function control register 0 PFCR0 H'FE32 PORT Port function control register 1 PFCR1 H'FE33 PORT Port function control register 2 PFCR2 H'FE34 PORT Port A MOS pull-up control register PAPCR H'FE36 PORT...
Page 863 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Timer status register_3 TSR_3 H'FE85 TPU_3 Timer counter_3 TCNT_3 H'FE86 TPU_3 Timer general register A_3 TGRA_3 H'FE88 TPU_3 Timer general register B_3 TGRB_3 H'FE8A TPU_3 Timer general register C_3 TGRC_3 H'FE8C TPU_3...
Page 864 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Read strobe timing control register RDNCR H'FEC6 Chip select assertion period control CSACRH H'FEC8 registers H Chip select assertion period control CSACRL H'FEC9 register L Burst ROM interface control register H BROMCRH 8 H'FECA Burst ROM interface control register L...
Page 865 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States I/O address register 1B IOAR_1B H'FEFC DMAC Transfer count register 1B ETCR_1B H'FEFE DMAC DMA write enable register DMAWER H'FF20 DMAC DMA terminal control register DMATCR H'FF21 DMAC DMA control register 0A DMACR_0A 8 H'FF22...
Page 866 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Extension module stop control register EXMSTPCR H'FF42 SYSTEM Extension module stop control register EXMSTPCR H'FF43 SYSTEM PLL control register PLLCR H'FF45 SYSTEM PPG output control register H'FF46 PPG output mode register H'FF47 Next data enable register H NDERH...
Page 867 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Port G register PORTG H'FF5F PORT Port 1 data register P1DR H'FF60 PORT Port 2 data register P2DR H'FF61 PORT Port 3 data register P3DR H'FF62 PORT Port 5 data register P5DR H'FF64 PORT...
Page 868 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Receive data register_1 RDR_1 H'FF85 SCI_1 Smart card mode register_1 SCMR_1 H'FF86 SCI_1 Serial mode register_2 SMR_2 H'FF88 SCI_2 Bit rate register_2 BRR_2 H'FF89 SCI_2 Serial control register_2 SCR_2 H'FF8A SCI_2...
Page 869 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Timer control register 1 TCR_1 H'FFB1 TMR_1 Timer control/status register 0 TCSR_0 H'FFB2 TMR_0 Timer control/status register 1 TCSR_1 H'FFB3 TMR_1 Time constant register A0 TCORA_0 H'FFB4 TMR_0 Time constant register A1 TCORA_1 H'FFB5...
Page 870 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Timer I/O control register L_0 TIORL_0 H'FFD3 TPU_0 Timer interrupt enable register_0 TIER_0 H'FFD4 TPU_0 Timer status register_0 TSR_0 H'FFD5 TPU_0 Timer counter_0 TCNT_0 H'FFD6 TPU_0 Timer general register A_0 TGRA_0 H'FFD8 TPU_0...
Page 871: Register Bits
23.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16- or 32-bit registers are shown as 2 or 4 lines. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 872 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module EDTCR_2 — — — — — — — — EXDMAC_2 — — — — — — — — — — — —...
Page 873 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IPRC — IPRC14 IPRC13 IPRC12 — IPRC10 IPRC9 IPRC8 — IPRC6 IPRC5 IPRC4 — IPRC2 IPRC1 IPRC0 IPRD — IPRD14 IPRD13 IPRD12 —...
Page 874 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P3DDR — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR PORT P5DDR — — — — P53DDR P52DDR P51DDR P50DDR P6DDR — —...
Page 875 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SMR_4* STOP CKS1 CKS0 SCI_4 Smart card SMR_4* BCP1 BCP0 CKS1 CKS0 interface 4 BRR_4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_4...
Page 876 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCNT_4 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRA_4 Bit15 Bit14 Bit13 Bit12 Bit11...
Page 877 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BRLE BREQ0E — IDLC ICIS1 ICIS0 WDBE WAITE — — — — — ICIS2 — — RAMER — — — — RAMS RAM2 RAM1...
Page 878 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MAR_1AL Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 DMAC2` Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IOAR_1A Bit15 Bit14 Bit13 Bit12 Bit11...
Page 879 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTC* DTCERC — DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCERD DTCED7 DTCED6 DTCED5 DTCED4...
Page 880 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module NDRL NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 NDRH — — — — NDR11 NDR10 NDR9 NDR8 NDRL — — —...
Page 881 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PEDR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR PORT PFDR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR PGDR — PG6DR PG5DR PG4DR...
Page 882 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRB — — — — — — ADDRC — — — — — — ADDRD — — — — — — ADDRE —...
Page 883 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCNT_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR_0 TMR_1 TCNT_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCSR WT/,7 —...
Page 884 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCNT_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRA_1 Bit15 Bit14 Bit13 Bit12 Bit11...
Page 885: Register States In Each Operating Mode
23.3 Register States in Each Operating Mode Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed ICCRA_0 Initialized — — — — — — — IIC2_0 ICCRB_0 Initialized — — —...
Page 886 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed IPRE Initialized — — — — — — Initialized IPRF Initialized — — — — — — Initialized IPRG Initialized — —...
Page 887 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed PEPCR Initialized — — — — — — — PORT P3ODR Initialized — — — — — — — PAODR Initialized —...
Page 888 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed TCNT_4 Initialized — — — — — — Initialized TPU_4 TGRA_4 Initialized — — — — — — Initialized TGRB_4 Initialized —...
Page 889 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed ETCR_0A Initialized — — — — — — Initialized DMAC MAR_0BH Initialized — — — — — — Initialized MAR_0BL Initialized —...
Page 890 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed SBYCR Initialized — — — — — — Initialized SYSTEM SCKCR Initialized — — — — — — Initialized SYSCR Initialized —...
Page 891 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed PORTG Initialized — — — — — — — PORT P1DR Initialized — — — — — — — P2DR Initialized —...
Page 892 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed SCR_2 Initialized — — — Initialized Initialized Initialized Initialized SCI_2 TDR_2 Initialized — — — Initialized Initialized Initialized Initialized SSR_2 Initialized —...
Page 893 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed TCNT_1 Initialized — — — — — — — TMR_0 TMR_1 TCSR Initialized — — — — — — — TCNT Initialized —...
Page 894 Clock Module All Module Software Hardware Register Reset High- Division Sleep Stop Clock Stop Standby Standby Module Name Speed TIER_2 Initialized — — — — — — Initialized TPU_2 TSR_2 Initialized — — — — — — Initialized TCNT_2 Initialized —...
Page 895: Section 24 Electrical Characteristics
Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.0 PLLV Input voltage (except port 4) –0.3 to V +0.3 Input voltage (port 4) –0.3 to AV +0.3...
Page 896: Dc Characteristics
24.2 DC Characteristics Table 24.2 DC Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item Symbol...
Page 897 Table 24.3 DC Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item Symbol...
Page 898 Notes: 1. When the A/D and D/A converters are not used, do not leave the AV , and AV pins open. Connect the AV and V pins to V , and the AV pin to V 2. Current dissipation values are for V min = V –...
Page 899: Ac Characteristics
24.3 AC Characteristics C = 50 pF: ports A to H C = 30 pF: ports 1 to 3, LSI output pin P50 to P53, ports 6 and 8 RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement level: 1.5 V (V = 3.0 V to 3.6 V) Figure 24.1 Output Load Circuit...
Page 900: Clock Timing
24.3.1 Clock Timing Table 24.5 Clock Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, ø = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 901 cdif sdcf sdcr SDRAM SDCH SDCL Figure 24.3 SDRAMφ φ φ φ Timing* EXTAL DEXT DEXT OSC1 OSC1 ø Figure 24.4 (1) Oscillation Stabilization Timing Rev. 1.0, 09/01, page 857 of 904...
Page 902: Control Signal Timing
Oscillator ø NMIEG SSBY NMI exception handling Software standby mode NMI exception (power-down mode) handling Oscillation NMIEG = 1 stabilization time SSBY = 1 OSC2 SLEEP instruction Figure 24.4 (2) Oscillation Stabilization Timing 24.3.2 Control Signal Timing Table 24.6 Control Signal Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V...
Page 903 ø RESS RESS RESW Figure 24.5 Reset Input Timing ø NMIS NMIH NMIW IRQW (i = 0 to 15)* IRQS IRQH (edge input) IRQS (level input) Note: * Necessary for SSIER setting to clear software standby mode. Figure 24.6 Interrupt Input Timing Rev.
Page 904: Bus Timing
24.3.3 Bus Timing Table 24.7 Bus Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, ø = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 905 Table 24.8 Bus Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, ø = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 906 Item Symbol Unit Test Conditions :$,7 setup time — Figure 24.15 :$,7 hold time — %5(4 setup time — Figure 24.23 BREQS %$&. delay time — BACD Bus floating time — %5(42 delay time — Figure 24.24 BRQOD &6 delay time* —...
Page 907 ø A23 to A0 CSD1 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD2 Write WDH1 WSW1 D15 to D0 DACD1 DACD2 EDACD1 EDACD2 Figure 24.7 Basic Bus Timing: Two-State Access Rev.
Page 908 ø A23 to A0 CSD1 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD1 WDS1 Write WDH1 WSW2 D15 to D0 DACD1 DACD2 EDACD1 EDACD2 Figure 24.8 Basic Bus Timing: Three-State Access Rev.
Page 909 ø A23 to A0 Read (RDNn = 1) D15 to D0 Read (RDNn = 0) D15 to D0 Write D15 to D0 Figure 24.9 Basic Bus Timing: Three-State Access, One Wait Rev. 1.0, 09/01, page 865 of 904...
Page 910 ø A23 to A0 CSD1 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD2 Write WDS2 WSW1 WDH3 D15 to D0 DACD1 DACD2 EDACD1 EDACD2 &6 &6 &6 Assertion Period Extended)
Page 911 ø A23 to A0 CSD1 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD2 RSD1 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD1 WDS3 Write WSW2 WDH3 D15 to D0 DACD1 DACD2 EDACD1 EDACD2 &6 Assertion Period Extended) &6 &6...
Page 912 ø A23 to A6, A5 to A1 RSD2 Read RDS2 RDH2 D15 to D0 Figure 24.12 Burst ROM Access Timing: One-State Burst Access Rev. 1.0, 09/01, page 868 of 904...
Page 913 ø A23 to A6, A5 to A1 RSD2 RDS2 RDH2 Read D15 to D0 Figure 24.13 Burst ROM Access Timing: Two-State Burst Access Rev. 1.0, 09/01, page 869 of 904...
Page 914 ø A23 to A0 CSD3 CSD2 PCH2 CASD1 CASD1 CASW1 OED1 OED1 Read RDS2 RDH2 D15 to D0 WCS1 WCH1 WRD2 WRD2 Write WDS1 WDH2 D15 to D0 DACD1 DACD2 EDACD1 EDACD2 Note: timing: when DDS = 0 and EDDS = 0 timing: when RAST = 0 Figure 24.14 DRAM Access Timing: Two-State Access Rev.
Page 915 Tcwp ø A23 to A0 Read D15 to D0 Write D15 to D0 Note: timing: when DDS = 0 and EDDS = 0 timing: when RAST = 0 Tcw : Wait cycle inserted by programmable wait function Tcwp: Wait cycle inserted by pin wait function Figure 24.15 DRAM Access Timing: Two-State Access, One Wait Rev.
Page 916 ø A23 to A0 CPW1 Read D15 to D0 Write RCS1 D15 to D0 DACD1 DACD2 EDACD1 EDACD2 Note: timing: when DDS = 0 and EDDS = 0 timing: when RAST = 0 Figure 24.16 DRAM Access Timing: Two-State Burst Access Rev.
Page 917 ø A23 to A0 CSD3 CSD2 PCH1 CASD1 CASD2 CASW2 OED2 OED1 Read RDS2 RDH2 D15 to D0 WCS2 WCH2 WRD2 WRD2 Write WDS2 WDH3 D15 to D0 DACD1 DACD2 EDACD1 EDACD2 Note: timing: when DDS = 0 and EDDS = 0 timing: when RAST = 0 Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1) Rev.
Page 918 ø A23 to A0 CPW2 Read D15 to D0 Write RCS2 D15 to D0 Note: timing: when DDS = 1 and EDDS = 1 timing: when RAST = 1 Figure 24.18 DRAM Access Timing: Three-State Burst Access Rev. 1.0, 09/01, page 874 of 904...
Page 919 TRc1 TRc2 ø CSD1 CSD2 CSR1 CASD1 CASD1 Figure 24.19 CAS-Before-RAS Refresh Timing TRrw TRc1 TRcw TRc2 ø CSD1 CSD2 CSR2 CASD1 CASD1 Figure 24.20 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Self-refresh DRAM access Tpsr ø CSD2 CSD2 RPS2 CASD1 CASD1 Figure 24.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0)
Page 920 Self-refresh DRAM access Tpsr ø CSD2 CSD2 RPS1 CASD1 CASD1 Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ø BREQS BREQS BACD BACD A23 to A0 D15 to D0 Figure 24.23 External Bus Release Timing Rev. 1.0, 09/01, page 876 of 904...
Page 921 ø BRQOD BRQOD Figure 24.24 External Bus Request Output Timing Rev. 1.0, 09/01, page 877 of 904...
Page 922 SDRAM Address bus Precharge-sel CSD4 CSD4 CSD4 CSD4 CSD4 CSD4 Read High DQMD DQMD DQMU, DQML RDS3 RDH3 Data bus CSD4 CSD4 CSD4 CSD4 CSD4 CSD4 CSD4 CSD4 Write High DQMD DQMU, DQMD DQML Data bus WDH4 Figure 24.25 Synchronous DRAM Basic Access Timing (CAS Latency 2) Rev.
Page 923 Software standby SDRAM Address bus Precharge-sel CKED CKED Figure 24.26 Synchronous DRAM Self-Refresh Timing Rev. 1.0, 09/01, page 879 of 904...
Page 924 T tp φ SDRAMφ Address bus Precharge-sel CKED CKED DQMU, DQML Data bus Figure 24.27 Read Data: Two-State Expansion (CAS Latency 2) Rev. 1.0, 09/01, page 880 of 904...
Page 925: Dmac And Exdmac Timing
24.3.4 DMAC and EXDMAC Timing Table 24.9 DMAC and EXDMAC Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, ø = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 926 ø A23 to A0 (read) D15 to D0 (read) (write) D15 to D0 (write) DACD1 DACD2 EDACD1 EDACD2 Figure 24.28 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access Rev. 1.0, 09/01, page 882 of 904...
Page 927 ø A23 to A0 (read) D15 to D0 (read) (write) D15 to D0 (write) DACD1 DACD2 EDACD1 EDACD2 Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access Rev. 1.0, 09/01, page 883 of 904...
Page 928 T2 or T3 ø ETED ETED Figure 24.30 DMAC and EXDMAC 7(1' 7(1'/(7(1' (7(1' Output Timing 7(1' 7(1' (7(1' (7(1' ø DRQS DRQH EDRQS DERQH Figure 24.31 DMAC and EXDMAC '5(4 '5(4 '5(4/('5(4 '5(4 ('5(4 ('5(4 Input Timing ('5(4 ø EDRKD EDRKD Figure 24.32 EXDMAC ('5$.
Page 929: Timing Of On-Chip Peripheral Modules
24.3.5 Timing of On-Chip Peripheral Modules Table 24.10 Timing of On-Chip Peripheral Modules Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, ø = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 930 Item Symbol Min Unit Test Conditions IIC2 SCL input cycle time +600 — Figure 24.44 SCL input high pulse width +300 — SCLH SCL input low pulse width +300 — SCLL SCL, SDA Input fall time — SCL, SDA Input spike pulse —...
Page 931 ø TOCD Output compare output* TICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 24.35 TPU Input/Output Timing ø TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 24.36 TPU Clock Input Timing ø...
Page 932 ø TMRS TMRI0, TMRI1 Figure 24.39 8-Bit Timer Reset Input Timing ø WOVD WOVD Figure 24.40 WDT Output Timing SCKW SCKr SCKf SCK0 to SCK2 Scyc Figure 24.41 SCK Clock Input Timing SCK0 to SCK2 TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data) Figure 24.42 SCI Input/Output Timing: Synchronous Mode...
Page 933 ø TRGS Figure 24.43 A/D Converter External Trigger Input Timing SDA0 SDA1 SCLH STOS STAH STAS SCL0 SCL1 SCLL SDAS SDAH Note: S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 24.44 I C Bus Interface Input/Output Timing (Option) Rev.
Page 934: A/D Conversion Characteristics
24.4 A/D Conversion Characteristics Table 24.11 A/D Conversion Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, ø = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 935: Flash Memory Characteristics
24.6 Flash Memory Characteristics Table 24.13 Flash Memory Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, T = 0°C to 75°C (program/erase operating temperature range: regular specifications), T = 0°C to 85°C (program/erase operating temperature range: wide-range specifications)
Page 936 Test Item Symbol Min Unit Conditions µs Erasing Wait time after — — SWE bit setting* µs Wait time after — — ESU bit setting* µs Wait time after — — Erase time E bit setting* wait α µs Wait time after —...
Page 937: Usage Note
24.7 Usage Note The F-ZTAT and mask ROM versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on.
Page 938 Rev. 1.0, 09/01, page 894 of 904...
Page 939: Appendix
Appendix I/O Port States in Each Pin State Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode* Reset Mode Standby Mode State Mode Port 1 1 to 7 Keep Keep I/O port Port 2 1 to 7 Keep Keep I/O port...
Page 940 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode* Reset Mode Standby Mode State Mode P96/DA4 1 to 7 [DAOE4 = 1] Keep Input port Keep [DAOE4 = 0] P95/DA3 1 to 7 [DAOE3 = 1] Keep Input port Keep...
Page 941 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode* Reset Mode Standby Mode State Mode PA4/A20 3, 4, 7 [OPE = 0, [Address output] [Address address output] output] PA3/A19 A20 to A16 PA2/A18 [Other than the [OPE = 1, above] [Other than...
Page 942 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode* Reset Mode Standby Mode State Mode Port C [OPE = 0, [Address output] [Address address output] output] A7 to A0 [Other than the [OPE = 1, above] [Other than address output] the above]...
Page 943 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode* Reset Mode Standby Mode State Mode PF7/ø [Clock output] [Clock output] [Clock 1, 2, 4 to 6 Clock output] output Clock output Clock output 3, 7 [Other than the [Other than the above] above]...
Page 944 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode* Reset Mode Standby Mode State Mode PF2//&$6/ 1 to 7 [OPE = 0, [/&$6 ('40/) [/&$6 /&$6#('40/) DQML output] ('40/) output] output] /&$6 [Other than the ('40/) [OPE = 1, above] /&$6 ('40/)
Page 945 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode* Reset Mode Standby Mode State Mode %$&. PG5/%$&. 1 to 7 [%$&. output] [%$&. output] %$&. %$&. [Other than the above] [Other than the above] Keep I/O port PG4/ 1 to 7 [%5(42...
Page 946 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode* Reset Mode Standby Mode State Mode PH3/2(/ 1 to 7 [OPE = 0, [2( output] [2( output] &6: 2( output] [&6 output] [&6 output] [OPE = 1, &6 2( output] [Other than the...
Page 947: Product Lineup
Note: The above products include those under development or being planned. For the status of each product, contact a Hitachi sales office. When using the optional functions for the F- ZTAT version, which has the common type name, contact a Hitachi sales office.
Page 948: Package Dimensions
Package Dimensions For package dimensions, dimensions described in Hitachi Semiconductor Packages have priority. As of July, 2001 22.0 ± 0.3 Unit: mm *0.22 ± 0.05 0.08 0.20 ± 0.04 1.25 0˚ – 8˚ 0.5 ± 0.1 0.10 Hitachi Code FP-144H JEDEC —...
Page 949 H8S/2378, H8S/2378R Series Hardware Manual Publication Date: 1st Edition, September 2001 Published by: Customer Service Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.

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H8s/2377r f-ztat Hd64f2377r H8s/2377 f-ztat Hd64f2377 H8s/2376 f-ztat Hd64f2376 ... Show all

Hitachi H8S/2378, H8S/2378R Series Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 DMA Controller (DMAC)

Section 8 EXDMA Controller

Section 9 Data Transfer Controller (DTC)

Section 10 I/O Ports

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Summary of Contents for Hitachi H8S/2378, H8S/2378R Series