Page 1 MELSEC-Q/L Programming Manual (Common Instruction)
Page 3: Safety Precautions
SAFETY PRECAUTIONS (Read these precautions before using this product.) Before using this product, please read this manual and the related manuals introduced in this manual, and pay full attention to safety to handle the product correctly. Please store this manual in a safe place and make it accessible when required. Always forward a copy of the manual to the end user.
Page 4: Introduction
INTRODUCTION This manual "MELSEC-Q/L Programming Manual (Common Instruction)" describes the common instructions required for programming of the QCPU and LCPU. "Common instructions" are all instructions except for dedicated instructions for intelligent function modules; PID control instructions; process control instruction; SFC instructions; ST instructions; instructions for socket communication features;...
Page 5: Table Of Contents
CONTENTS SAFETY PRECAUTIONS ..............1 CONDITIONS OF USE FOR THE PRODUCT .
Page 6 Other instructions ............... . 75 Instructions for Data Link .
Page 7 Setting devices (excluding annunciators) ........... . . 158 Resetting devices (excluding annunciators) .
Page 8 16-bit BIN data increment, 16-bit BIN data decrement ......... . . 265 32-bit BIN data increment, 32-bit BIN data decrement .
Page 9 Ramp signal................345 Pulse density measurement .
Page 10 Calculation of averages for 16-bit data, calculation of averages for 32-bit data ......450 Check code ................452 CRC operation.
Page 11 Conversion from ASCII to hexadecimal BIN ........... 574 Extracting character string data from the right, extracting character string data from the left .
Page 12 File setting for file register ..............679 File setting for comments .
Page 13 High-speed block transfer of file register ............812 User message .
Page 14: Manuals
MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following lists. The numbers in the "CPU module"...
Page 15 Describes the general concept, specifications, and part names and settings for MELSECNET Reference Manual () and MELSECNET/B. <IB-66350> MELSEC-Q/L Ethernet Interface Module User's Manual E-mail function, programmable controller CPU status monitoring function, communication via (Application) CC-Link IE Field Network, CC-Link IE Controller Network, MELSECNET/H, or MELSECNET/ <SH-080010>...
Page 16: Terms
TERMS This manual uses the generic names and abbreviations shown below to refer to Q/L series CPU modules, unless otherwise specified.  indicates a part of the model or version. Term Description A5B A generic term for the power source-free type A52B, A55B, and A58B extension base unit on which the A Series I/O module and special function module can be mounted A6B A generic term for the A62B, A65B, and A68B extension base unit on which the A Series I/O module and special...
Page 17 Term Description QnPHCPU A generic term for Q02PHCPU, Q06PHCPU, Q12PHCPU and Q25PHCPU QnPRHCPU A generic term for Q12PRHCPU and Q25PRHCPU QnU(D)(H)CPU A generic term for Q02UCPU, Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU and Q26UDHCPU QnUCPU A generic term for Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q03UDVCPU, Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU, Q06UDHCPU, Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU and Q100UDEHCPU...
Page 18: Chapter 1 General Description
 MELSEC-L CPU Module User's Manual (Function Explanation, Program Fundamentals) Basic model QCPU Qn(H)/QnPH/ QnPRHCPU Describes the functions User's Manual and devices of the CPU (Function Explanation, module, and programming. Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L Programming QnA Programming QnA Programming Programming Programming Manual (Common Manual...
Page 19 High Performance model QCPU Qn(H)/QnPH/ QnPRHCPU User's Manual Describes the functions (Function Explanation, and devices of the CPU Program module, and programming. Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L Programming QnA Programming QnA Programming Programming Programming Manual (Common Manual...
Page 20 Redundant CPU Qn(H)/QnPH/ Describes the functions and QnPRHCPU devices of the CPU module, User's Manual and programming. (Function Explanation, Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L Programming Manual Programming Manual Programming Manual Programming Manual Programming/ (Common Instruction) (SFC)
Page 21 Universal model QCPU QnUCPU Describes the functions and User's Manual devices of the CPU module, and programming. (Function Explanation, Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L MELSEC-Q Programming Manual Programming/ Programming Manual Programming Manual Programming Manual (Common Instruction) (SFC)
Page 22 LCPU MELSEC-L Describes the functions and CPU Module devices of the CPU module, User's Manual and programming. (Function Explanation, Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/QnA MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L Programming Manual Programming Manual Programming Manual Programming Manual Programming Manual (Common Instruction)
Page 23: Chapter 2 Instruction Tables
INSTRUCTION TABLES Types of Instructions The major types of CPU module instructions consist of sequence instructions, basic instructions, application instructions, data link instructions, QCPU instructions and redundant system instructions. These types of instructions are listed in the following Table. Types of instructions Description Reference Sequence...
Page 24 Types of instructions Description Reference Application Logical operation instruction Logical operations such as logical sum, logical product, etc. Page 355 instruction APPLICATION Rotation instruction Rotation of designated data INSTRUCTIONS Shift instruction Shift of designated data Bit processing instruction Bit set and reset, bit test, batch reset of bit devices Data processing instruction 16-bit data searches, data processing such as decoding and encoding Structure creation instruction...
Page 25: How To Read Instruction Tables
How to Read Instruction Tables The instruction tables found from Page 25 Sequence Instructions to Page 79 Redundant System Instructions (For Redundant CPU) have been made according to the following format: Ò Ó Ô Õ Ö × Ø Ù  Classifies instructions according to their application. ...
Page 26  Indicates the type of processing that is performed by individual instructions. (D)+(S) (D+1, D) +(S+1, S) (D +1,D) 16 bits 16 bits Indicates 16 bits. Indicates 32 bits. Upper 16 bits Lower 16 bits  Indicates execution conditions for individual instructions. Execution condition Non-conditional Executed at ON...
Page 27 Sequence Instructions Contact instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Contact • Starts logic operation (Starts A contact logic operation) ● Page 131 • Starts logical NOT operation (Starts B contact logic operation) •...
Page 28: Association Instructions
*1 The number of steps may vary depending on the device being used. Device Number of steps Internal device, file register (R0 to R32767) Direct access input (DX) Devices other than above *2 The number of steps may differ, depending on the device or CPU module to be used. CPU module Device Number of steps...
Page 29: Output Instructions
Output instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Output • Device output  Page 148 Page 150 Page 154 Page 156  • Sets device Page 158 Page 162 Annunciator (F)  •...
Page 30: Termination Instructions
Termination instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Termination FEND • Termination of main Page 177 FEND program • Termination of sequence Page 179 program *1 For the High-speed Universal model QCPU, the number of basic steps is two. Other instructions Category Instruction...
Page 31 Basic Instructions Comparison operation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BIN 16-bit • Conductive status when (S1) ● Page 187 S1 S2 data = (S2) comparisons • Non-conductive status when AND= S1 S2 (S1) ...
Page 32 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BIN 32-bit LDD= • Conductive status when ● Page 189 S1 S2 data (S1+1, S1) = (S2+1, S2) comparisons • Non-Conductive status when ANDD= S1 S2 (S1+1, S1) ...
Page 33 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Floating LDE= • Conductive status when Page 191 S1 S2 decimal (S1+1, S1) = (S2+1, S2) point data • Non-Conductive status when ANDE= S1 S2 (S1+1, S1) ...
Page 34 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Floating LDED= • Conductive status when Page 193 S1 S2 decimal (S1+3, S1+2, S1+1, S1) = point data (S2+3, S2+2, S2+1, S2) ANDED= S1 S2 comparisons •...
Page 35 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Character LD$= • Compares character string Page 196 S1 S2 string data S1 and character string S2 comparisons one character at a time. AND$= S1 S2 •...
Page 36 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  BIN 16-bit BKCMP= • This instruction compares Page 199 BKCMP S1 S2 D Block data BIN 16-bit data stored in n- comparisons point devices starting from BKCMP<>...
Page 37 *1 The number of steps may differ, depending on the device or CPU module to be used. CPU module Device Number of Remark steps High Performance model QCPU • Word device: Internal device (except for file register When using a High Performance model Process CPU QCPU, Process CPU or Redundant CPU, Redundant CPU...
Page 38: Arithmetic Operation Instruction
Arithmetic operation instruction Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● BIN 16-bit • D+(S)(D) Page 220 addition and subtraction operations ● • (S1)+(S2)(D) Page 222 S1 S2 D S1 S2 D ● •...
Page 39 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BCD 4-digit • (D)+(S)(D) ● Page 232 addition and subtraction operations  • (S1)+(S2)(D) Page 234 S1 S2 D S1 S2 D • (D)-(S)(D) ● Page 232 ...
Page 40 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● Floating • (D+1, D)+(S+1, S)(D+1, D) Page 244 decimal point data addition and subtraction • (S1+1, S1)+(S2+1, S2)(D+1, ● Page 246 operations S1 S2 D (single precision) S1 S2 D...
Page 41 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  BIN 16-bit • This instruction adds BIN 16-bit Page 256 S1 S2 data block data stored in n-point devices addition and starting from the device BK+P BK+P S1 S2...
Page 42 *1 The number of steps may differ, depending on the device or CPU module to be used. CPU module Device Number of Remark steps High Performance model QCPU • Word device: Internal device (except for file register When using a High Performance model Process CPU QCPU, Process CPU or Redundant CPU, Redundant CPU...
Page 43: Data Conversion Instructions
Data conversion instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● Page 269 BCD conversions conversions BCDP BIN (0 to 9999) BCDP DBCD ● BCD conversions DBCD (S+1, S) (D+1, D) DBCDP BIN (0 to 99999999) DBCDP ●...
Page 44 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BIN 16-bit   Page 281 Conversion 32-bit (D+1, D) conversions BIN (-32768 to 32767) DBLP DBLP  WORD Page 282 Conversion WORD (S+1, S) BIN (-32768 to 32767) WORDP WORDP BIN ...
Page 45 *1 The number of basic steps is two for the Universal model QCPU and LCPU. *2 The subset is effective only with Universal model QCPU and LCPU. *3 For the High-speed Universal model QCPU, the number of basic steps is two. 2 INSTRUCTION TABLES 2.4 Basic Instructions...
Page 46 Data transfer instruction Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● 16-bit data • (S)(D) Page 297 transfer MOVP MOVP ● 32-bit data DMOV • (S+1, S)(D+1, D) DMOV transfer DMOVP DMOVP ● Floating EMOV Page 299...
Page 47 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Exchange SWAP Page 318 SWAP b8 b7 of upper 8 bits 8 bits and lower SWAPP SWAPP bytes b8 b7 8 bits 8 bits Shift SMOV ...
Page 48: Program Branch Instructions
Program branch instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● Jump • Jumps to Pn when input Page 321 conditions are met. ● • Jumps to Pn from the scan after the meeting of input condition.
Page 49: Other Convenient Instructions
Other convenient instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Up/Down UDCNT1  Page 334 UDCNT1 (S)+0 counter (S)+1 Down Present 1 2 3 4 6 7 6 5 3 2 1 0 -1 -2 -3 -2 -1 0 value contact ...
Page 50 Application Instructions Logical operation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Logical WAND • (D)(S)(D) ● Page 356 WAND product WANDP WANDP WAND • (S1)(S2)(D) ● Page 358 WAND S1 S2 D WANDP WANDP S1 S2 D...
Page 51 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Exclusive WXOR • (D)(S)(D) ● Page 369 WXOR WXORP WXORP ● WXOR • (S1)(S2)(D) Page 371 WXOR S1 S2 D WXORP WXORP S1 S2 D DXOR •...
Page 52 *1 The number of basic steps is three for the Universal model QCPU and LCPU. *2 The number of steps may differ, depending on the device or CPU module to be used. CPU module Device Number of Remark steps High Performance model QCPU •...
Page 53: Rotation Instructions
Rotation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Right ● Page 381 SM700 rotation of 16-bit data RORP RORP Right rotation by n bits Carry flag ● SM700 RCRP RCRP Right rotation by n bits Carry flag Left rotation ●...
Page 54 Shift instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● n-bit shift of Page 391 16-bit data Carry flag SFRP SFRP b0 SM700 0 to 0 ● Carry flag SFLP SM700 SFLP 0 to 0 1-bit shift of BSFR ...
Page 55 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Bit shift SFTR Page 404 SFTR S D n1 right/shift left SFTRP SFTRP S D n1 SFTL  Page 406 SFTL S D n1 SFTLP SFTLP S D n1 ...
Page 56: Bit Processing Instructions
Bit processing instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● Bit set/reset BSET Page 412 BSET BSETP BSETP BRST ● BRST BRSTP BRSTP  Bit tests TEST Page 414 (S1) TEST S1 S2 D TESTP TESTP S1 S2 D...
Page 57: Data Processing Instructions
Data processing instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Data  Page 418 (S2) S1 S2 D (S1) searches SERP SERP S1 S2 D (D): Match No. (D + 1): Number of matches DSER ...
Page 58 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Separating • Separates 16-bit data Page 429 and linking designated by (S) into 4-bit units, and stores at the lower DISP DISP 4 bits of n points from (D). (n4) ...
Page 59 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Sort SORT • Sorts data of n points from Page 444 S1 n SORT S2 D1 device designated by (S1) in 16-bit units. (n  (n-1)/2 scans •...
Page 60: Structure Creation Instructions
Structure creation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Number of • Executes n times between Page 457 repeats the [FOR] and [NEXT]. NEXT  NEXT  BREAK • Forcibly ends the Page 460 BREAK execution of the [FOR] to...
Page 61 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Select • Performs auto refresh of Page 487 refresh intelligent function modules, auto refresh of link refresh, and communications with peripherals. • Performs auto refresh of ...
Page 62: Data Table Operation Instructions
Data table operation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Data table FIFW Page 498 Pointer Pointer + 1 FIFW processing FIFWP FIFWP Device at pointer + 1  FIFR Page 500 (S) Pointer Pointer - 1 FIFR...
Page 63: Display Instructions
Display instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ASCII print • Outputs ASCII code from  Page 512 When SM701 is OFF device designated by (S) to 00H to output module. • Outputs ASCII code of 8 When SM701 is ON points (16 characters) from device designated by (S) to...
Page 64: Character String Processing Instructions
Character string processing instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BIN   BINDA • Converts 1-word BIN value Page 528 BINDA Decimal designated by (S) to a 5-digit, ASCII decimal ASCII value, and stores BINDAP it at the word device designated BINDAP...
Page 65 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Decimal DABCD • Converts a 4-digit, decimal Page 543 DABCD ASCII  ASCII value designated by (S) to a 1-word BCD value, and stores DABCDP it at a word device number DABCDP designated by (D).
Page 66 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Hexadecimal • Converts the 1-word BIN value Page 572 BIN  ASCII at the device numbers designated by (S) to ASCP hexadecimal ASCII, and stores ASCP n characters of them at the device numbers designated by...
Page 67: Special Function Instructions
Special function instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Trigonometric • Sin(S+1, S)(D+1, D)  Page 594 functions (Floating-point SINP single- SINP precision)  • Cos(S+1, S)(D+1, D) Page 598 COSP COSP ...
Page 68 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Angles   • (S+1, S)(D+1, D) Page 618 Radians Conversion from angles to radians conversion RADP RADP RADD • (S+3, S+2, S+1, S)(D+3, D+2,  Page 620 RADD D+1, D)
Page 69 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Random • Generates a random number (from 0 Page 646 number to less than 32767) and stores it at generation the device designated by (D). RNDP RNDP Random...
Page 70: Data Control Instructions
Data control instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Page 662 Upper and LIMIT • When (S3) < (S1), a value of (S1) LIMIT S1 S2 lower limit is stored at (D). •...
Page 71 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  X or Y SCL2 • Executes scaling for the scaling Page 674 SCL2 S1 S2 D coordinate conversion data (16-bit data units) data specified by (S2) with the input SCL2P SCL2P S1 S2 D...
Page 72: Clock Instructions
Clock instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Read/write DATERD Page 683 (Clock elements) (D) +0 Year DATERD D clock data Month Hour DATERDP Minute DATERDP D Sec. Day of the week ...
Page 73 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Date LDDT= Page 697 S1 S2 n Year Year Comparison comparison operation Month Month result ANDDT= S1 S2 ORDT= S1 S2  LDDT<> S1 S2 n Year Year Comparison...
Page 74 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Clock LDTM= Page 701 S1 S2 n Hour Hour comparison Comparison operation Minute Minute result ANDTM= Second Second S1 S2 ORTM= S1 S2 LDTM<>  S1 S2 n Hour Hour...
Page 75: Expansion Clock Instructions
Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Clock data TZCP Page 707 TZCP S1 S2 S3 Hour Hour band turns on. min. min. comparison Sec. Sec. TZCPP TZCPP S1 S2 S3 Hour Hour Hour min.
Page 76: Program Control Instructions
Program control instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Program PSTOP • Places designated program in Page 719 PSTOP File name control standby status. instructions PSTOPP PSTOPP File name POFF • Turns OUT instruction coil of ...
Page 77: Other Instructions
Other instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps WDT reset • Resets watchdog timer during  Page 752 sequence program. WDTP WDTP  Timing DUTY Page 754 DUTY n1 n2 D clock n1 scans n2 scans SM420 to SM424, SM430 to SM434...
Page 78 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Writing data SP.FWRITE • Writes data to the designated file. Page 779 SP.FWRITE S0 D0 S1 S2 to the designated file Reading SP.FREAD • Reads data from the designated ...
Page 79: Instructions For Data Link
Instructions for Data Link Instructions for network refresh Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Link S.ZCOM • Refreshes the designated Page 820 S.ZCOM instruction: network. Network SP.ZCOM refresh SP.ZCOM Jn S.ZCOM S.ZCOM SP.ZCOM SP.ZCOM Un...
Page 80: Multiple Cpu Dedicated Instruction
Multiple CPU Dedicated Instruction Instructions for writing to the CPU shared memory of host CPU Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Write to S.TO • Writes device data of the host Page 848 S.TO host CPU...
Page 81: Multiple Cpu High-Speed Transmission Dedicated Instruction
Multiple CPU High-speed Transmission Dedicated Instruction Instructions for multiple CPU high-speed transmission Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Writing D.DDWR • In multiple CPU system, data Page 872 D.DDWR devices to stored in a device specified by another host CPU ((S2)) or later is...
Page 82: Chapter 3 Configuration Of Instructions
CONFIGURATION OF INSTRUCTIONS Configuration of Instructions Most CPU module instructions consist of an instruction part and a device part. Each part is used for the following purpose: • Instruction part: indicates the function of the instruction. • Device part: indicates the data that is to be used with the instruction. The device part consists of source data, destination data, and number of devices.
Page 83: Designating Data
Designating Data The following six types of data can be used with CPU module instructions. Data that can be handled Bit data by CPU module Numeric data Integer data Word data Double-word data Real number Single-precision (floating point) data floating point data Double-precision floating point data Character string data...
Page 84: Using Bit Data
Using bit data Bit data is data used in one-bit units, such as for contacts or coils. "Bit devices" and "Bit designated word devices" can be used as bit data. When using bit devices Bit devices are designated in one-point units. Designation of 1 point of bit device M0 Designation of 1 point...
Page 85: Using Word (16 Bits) Data
Using word (16 bits) data Word data is 16-bit numeric data used by basic instructions and application instructions. The following two types of word data can be used with CPU module: • Decimal constants: K-32768 to K32767 • Hexadecimal constants: H0000 to HFFFF Word devices and bit devices designated by digit can be used as word data.
Page 86 In cases where digit designation is made at the destination (D), the number of points designated are used as the destination. Bit devices below the number of points designated as digits do not change. Ladder example Processing • When source (S) data is a numerical value X010 H1234 0 0 0 1 1 0 1 0 0...
Page 87: Using Double Word (32 Bits) Data
Using double word (32 bits) data Double word data is 32-bit numerical data used by basic instructions and application instructions. The two types of double word data that can be dealt with by CPU module are as follows: • Decimal constants: K-2147483648 to K2147483647 •...
Page 88 When destination (D) data is a word device, the word device for the destination becomes 0 following the bit designated by digit designation at the source. Ladder example Processing • With 32-bit instructions K1X0 X3 X2 X1 X0 DMOV K1X0 Filled with 0s 0 0 0 0 0 0 0 0 0 0 X2 X1 X0...
Page 89: Using Single/Double-Precision Real Number Data
Using single/double-precision real number data Real number data is floating decimal point data used with basic instructions and application instructions. Only word devices are capable of storing real number data. Single-precision real number data (single-precision floating-point data) Instructions which deal with single-precision floating-point data designate devices which are used for the lower 16 bits of data. Single-precision floating-point data are stored in the 32 bits which make up (designated device number) and (designated device number + 1).
Page 90 Double-precision real number data (double-precision floating-point data) Instructions which deal with double-precision floating-point data designate devices which are used for the lower 16 bits of data. Double-precision floating-point data are stored in the 64 bits which make up (designated device number) to (designated device number + 3).
Page 91 Precautions Precautions when an input value of a single/double-precision real number is set using a programming tool are shown below. ■Single-precision real number Because single-precision real number data are processed as the 32-bit single-precision in a programming tool, the number of significant digits becomes approximately 7.
Page 92 The CPU module floating decimal point data can be monitored using the monitoring function of a programming tool. When floating-point data is used to express 0, all data in the following range are turned to 0. • Single-precision floating-point data: b0 to b31 •...
Page 93: Using Character String Data
Using character string data Character string data is character data used by basic instructions and application instructions. The target ranges from the designated character to the NULL code (00H) that indicates the end of the character string. When designated character is the NULL code One word is used to store the NULL code.
Page 94: Indexing
Indexing Overview of indexing Indexing is an indirect setting made by using an index register. When an Indexing is used in a sequence program, the device to be used will become the device number specified directly plus the contents of the index register. For example, if D2Z2 has been specified, the specified device is calculated as follows: D(2+3) = D5 and the content of Z2 is 3 become the specified device.
Page 95 *1 SFC transfer devices and SFC block devices are devices for SFC use. Refer to the manual below for how to use these devices.  MELSEC-Q/L/QnA Programming Manual (SFC) *2 For the High-speed Universal model QCPU, the SFC block device (BL) and step relay (S) can be modified using indices within the following range.
Page 96 ■A case where indexing has been performed, and the actual process device (Z0 =20, Z1 = -5) Ladder example Actual process device MOV K2X64 K1M33 MOV K20 Description K2X(50 + 14) = K2X64 K2X50Z0 MOV K 5 Converts K20 into a hexadecimal number. K1M38Z1 K1M(38 - 5) = K1M33 MOV K2X50Z0 K1M38Z1...
Page 97 Indexing with 32-bit index registers A method of specifying index registers in indexing with 32-bit can be selected from the following two methods. • Specifying the index registers' range used for indexing with 32-bit. • Specifying the 32-bit indexing using "ZZ" specification. *1 The methods applies only to Universal model QCPU (excluding Q00UJCPU) and LCPU.
Page 98 • Device that indexing can be used Indexing can be used only for the device shown below. Device Description Serial number access format file register Extended data register (D) Extended link register (W) • Usable range of index registers The following table shows the usable range of index registers for indexing with 32-bit index registers. For indexing with 32-bit index registers, the specified index register (Zn) and the next index register of the specified register (Zn+1) are used.
Page 99 ■Example of specifying 32-bit indexing with "ZZ" specification One index register can specify 32-bit indexing by using "ZZ" specification such as "ZR0ZZ4". The 32-bit indexing with "ZZ" specification is as follows. Stores 100000 at Z4 and Z5. DMOVP K100000 Indexing ZR device with 32-bit MOVP K100 ZR0ZZ4...
Page 100 • A case where 32-bit indexing used "ZZ" specification has been performed, and the actual process device (Z0 (32-bit) =100000, Z2 (32-bit) = -20) Ladder example Actual process device ZR101000 D10 DMOV K100000 Z0 K-20 Description ZR1000ZZ0 D30Z2 ZR1000ZZ0 ZR(1000+100000)=ZR101000 D30Z2 D(30-20)=D10 •...
Page 101 Index modification using extended data register (D) and extended link register (W) Like index modification using data register (D) and link register (W) of internal user device, a device can be specified by index modification within the range of the extended data register (D) and extended link register (W). *1 This applies only to Universal model QCPU (excluding Q00UJCPU) and LCPU.
Page 102 ■Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) will not cause an error.
Page 103 Other index modifications For bit data, device numbers can be index modified when performing digit designation. However, Indexing is not possible by digit designation. BIN K4X0Z2 Setting is possible since this indicates Indexing for device number. If Z2=3, then (X0+3)=X3 BIN K4Z3X0 Setting is not possible since this indicates Indexing by digit designation.
Page 104 Cautions ■Performing indexing between the FOR and NEXT instructions Pulses can be output between the FOR and NEXT instructions by use of the edge relay (V). However, pulse output using the PLS/PLF/pulse (P) instruction is not allowed. When edge relay is used When edge relay is not used M0Z1 provides normal pulse output.
Page 105 ■Device range check during indexing • Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU Device range checks are not conducted during indexing. Therefore, when the data after index modification exceed the user specified device range, the data is read by another device or written to another device without causing an error.
Page 106 ■Changing indexing with 16-bit index register for indexing with 32-bit index register For changing indexing with 16-bit index register for indexing with 32-bit index register, check if the program has enough spaces for indexing. For indexing with 32-bit index registers, the specified index register (Zn) and the next index register of the specified register (Zn+1) are used.
Page 107: Indirect Specification
Indirect Specification Indirect Specification Indirect specification is a method that specifies address of the device to be used in a sequence program using two word devices (two points of word device). Use indirect specification as index modification when the index register is insufficient. ADRSET D100 Store the address of D100 in D0 and D1.
Page 108 Precautions ■Address for indirect specification The address for indirect specification uses two words. Therefore, to substitute indirect specification for index modification, the addition/subtraction of 32-bit data is required. The following is the ladder used for the address addition/subtraction of the device stored in D1 and D0 for indirect specification.
Page 109 ■Indirect specification and index modification When a device is specified by both indirect specification and index modification, index modification is executed first and then the device is specified by indirect specification. Store K5 in the index register Z2. ADRSET D0 D100Z2 Store the address of D0 in D105 and D106 (D(100) + 5) = D105).
Page 110: Reducing Instruction Processing Time
Reducing Instruction Processing Time Subset processing Subset processing is used to place limits on bit devices used by basic instructions and application instructions in order to increase processing speed. However, the instruction symbol does not change. To shorten scans, run instructions under the conditions indicated below. Conditions which each device must meet for subset processing ■When using word data Device...
Page 111: Operation Processing With Standard Device Registers (Z) (Universal Model Qcpu And Lcpu Only)
Instructions for which subset processing can be used Types of instructions Instruction symbol Contact instructions LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP, ANDF, ORP, ORF, LDPI, ANDPI, ANDFI, ORPI, ORFI Output instructions OUT, SET, RST Comparison operation instructions =, <>, <, <=, >, >=, D=, D<>, D<, D<=, D>, D>= Arithmetic operation +, -, *, /, INC, DEC, D+, D-, D*, D/, DINC, DDEC, B+, B-, B*, B/, E+, E-, E*, E/...
Page 112: Cautions On Programming (Operation Errors)
Cautions on Programming (Operation Errors) Operation errors are returned in the following cases when executing basic instructions and application instructions with CPU module: • An error listed on the explanatory page for the individual instruction occurred. • When an intelligent function module device is used, no intelligent function module is installed at the specified I/O number position.
Page 113 Device range check Device range checks for the devices used by basic instructions and application instructions in CPU module are as indicated below: ■Instructions for specified each device, including MOV and DMOV • For the Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU. The device range is not checked.
Page 114 ■Instructions for a block of devices, including BMOV and FMOV • For the Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU. The device range is checked. When the device number is outside the device range, an operation error occurs. For example, when 12K points are assigned to a data register, an error occurs if the device number of the data register exceeds D12287.
Page 115 ■Character string data • For the Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU. Because all character string data is of variable length, device range checks are performed. When the device number is outside the device range, an operation error occurs. For example, in a case where the data register has been allocated 12K points, there will be an error if it exceeds D12287.
Page 116 ■Precautions for using the extended data register (D) or extended link register (W) With the following specification methods, data cannot be specified crossing over the boundary of the internal user device and extended data register (D) or extended link register (W). Doing so causes "OPERATION ERROR" (error code: 4101). *1 Universal model QCPU (models other than Q00UJCPU) and LCPU are applicable.
Page 117 ■Precautions when using Universal model QCPU/LCPU For the Universal model QCPU and LCPU, an error occurs if any of the following accesses is performed using the following instructions and data. (Error code: 4101) Instructions and data • Instructions for specified each device, including MOV and DMOV •...
Page 118 Device data check Device data checks for the devices used by basic instructions and application instructions in CPU module are as indicated below: ■When using BIN data No error is returned even if the operation results in overflow or underflow. The carry flag (SM700) does not go on at such times, either.
Page 119: Conditions For Execution Of Instructions
Conditions for Execution of Instructions The following four types of execution conditions exist for the execution of CPU module sequence instructions, basic instructions, and application instructions: Execution condition Description Non-conditional execution  An instruction is always executed regardless of whether the precondition of the instruction is on or off. When the precondition is off, the instruction performs off processing.
Page 120: Counting Step Number
Counting Step Number The number of steps in CPU module sequence instructions, basic instructions, and application instructions differs depending on whether indirect setting of the device used is possible or not. Counting the number of basic steps The basic number of steps for basic instructions and application instructions is calculated by adding the device number and 1. For example, the "+ instruction"...
Page 121 Instruction symbol Devices with additional steps Added steps Number of basic (number of steps instruction steps) Serial number access format file register, Extended data 1(2) register (D), Extended link register (W) Multiple CPU shared device Timer/Counter 3(4) Serial number access format file register, Extended data 1(2) register (D), Extended link register (W) Multiple CPU shared device...
Page 122 Instruction symbol Devices with additional steps Added steps Number of basic (number of steps instruction steps) DMOV, DMOVP, EMOV, EMOVP Serial number access format file register, Extended data register (D), Extended link register (W) Multiple CPU shared device Decimal constant, hexadecimal constant, real constant BCD, BCDP, BIN, BINP, FLT, FLTP, CML, CMLP Serial number access format file register, Extended data (S): 1, (D): 2...
Page 123 The following table shows steps depending on the devices. Devices with additional steps Added steps Example Intelligent function module device MOV U4\G10 D0 Multiple CPU shared device MOV U3E1\G10000 D0 Link direct device MOV J3\B20 D0 Index register / standard device register MOV Z0 D0 Serial number access format file register MOV ZR123 D0...
Page 124: Operation When The Out, Set/Rst, Or Pls/Plf Instructions Use The Same Device
Operation When the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device The following describes the operation for executing multiple instructions of the OUT, SET/RST, or PLS/PLF that use the same device in one scan. OUT instructions using the same device Do not program more than one OUT instruction using the same device in one scan.
Page 125 SET/RST instructions using the same device • The SET instruction turns ON the specified device when the execution command is ON and performs nothing when the execution command is OFF. For this reason, when the SET instructions using the same device are executed two or more times in one scan, the specified device will be ON if any one of the execution commands is ON.
Page 126 PLS instructions using the same device The PLS instruction turns ON the specified device when the execution command is turned ON from OFF. It turns OFF the device at any other time (OFF to OFF, ON to ON, or ON to OFF). If two or more PLS instructions using the same device are executed in one scan, each instruction turns ON the device when the corresponding execution command is turned ON from OFF and turns OFF the device in other cases.
Page 127 PLF instructions using the same device The PLF instruction turns ON the specified device when the execution command is turned OFF from ON. It turns OFF the device at any other time (OFF to OFF, OFF to ON, or ON to ON). If two or more PLF instructions using the same device are executed in one scan, each instruction turns ON the device when the corresponding execution command is turned OFF from ON and turns OFF the device in other cases.
Page 128: Precautions For Use Of File Registers
3.10 Precautions for Use of File Registers This section explains the precautions for use of the file registers in the QCPU and LCPU. CPU modules that cannot use file registers The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers, use the CPU module of other than the Q00JCPU and Q00UJCPU.
Page 129 File register specifying method There are the block switching method and serial number access method to specify the file registers. ■Block switching method In the block switching method, specify the number of used file register points in units of 32K points (one block). For file registers of 32K points or more, specify the file registers by switching the block No.
Page 130 ■Restrictions The restrictions when specifying file registers to refresh devices are as follows. • On QCPU, Refresh cannot be performed correctly if the use of file register which has the same name as the program is specified by the PLC parameter. When the file register which has the same name as the program is used, refresh is performed to the data of the file register having the same name as the program that is set at the last number in the [Program] tab page of PLC parameter.
Page 131: Chapter 4 How To Read Instructions
HOW TO READ INSTRUCTIONS The description of instructions that are contained in the following chapters are presented in the following format. Ò Ó Ô Õ Ö × Ø Ù  Code used to write instruction (instruction symbol).  Shows if instructions are enabled or disabled for each CPU module type. Icon Description Basic model...
Page 132  Indicates ladder mode expressions and execution conditions for instructions. Execution condition Non-conditional Executed at ON Executed at the Executed at OFF Executed at the execution rising edge falling edge Code recorded on No symbol recorded description page For execution conditions, refer to Page 117 Conditions for Execution of Instructions. ...
Page 133: Sequence Instructions
Internal device R, ZR J\ U\G Constant Others data Word Word    When BL, S, TR, BL\S, or BL\TR is used, refer to the SFC control instructions in the MELSEC-Q/L/QnA Programming Manual (SFC). 5 SEQUENCE INSTRUCTIONS 5.1 Contact Instructions...
Page 134 Processing details ■LD, LDI • LD is the A contact operation start instruction, and LDI is the B contact operation start instruction. They read ON/OFF information from the designated device , and use that as an operation result. *1 When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of the designated bit. ■AND, ANI •...
Page 135 • A program linking contacts using the ANB and ORB instructions. [Ladder Mode] [List Mode] Instruction Device Step Bit designated for word device • A parallel program with the OUT instruction. [Ladder Mode] [List Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.1 Contact Instructions...
Page 136: Pulse Operation Start, Pulse Series Connection, Pulse Parallel Connection
Pulse operation start, pulse series connection, pulse parallel connection LDP, LDF, ANDP, ANDF, ORP, ORF High Basic Process Redundant Universal LCPU performance Bit device number / Word device bit designation X1/D0.1 X1/D0.1 X2/D0.2 ANDP X2/D0.2 ANDF X3/D0.3 X3/D0.3 (S): Devices used as contacts (bits) Setting Internal device R, ZR...
Page 137 ■ANDP, ANDF • ANDP is a rising edge pulse series connection instruction, and ANDF is a falling edge pulse series connection instruction. They perform an AND operation with the operation result to that point, and take the resulting value as the operation result. The ON/OFF data used by ANDP and ANDF are indicated in the table below: Device specified in ANDP or ANDF ANDP state...
Page 138: Pulse Not Operation Start, Pulse Not Series Connection, Pulse Not Parallel Connection
Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Bit device number / Word device bit designation X1/D0.1...
Page 139 ■ANDPI, ANDFI • ANDPI is a rising edge pulse NOT series connection, and ANDFI is a falling pulse NOT series connection. ANDPI and ANDFI execute an AND operation with the previous operation result, and take the resulting value as the operation result. The on or off data used by ANDPI and ANDFI are indicated in the table below.
Page 140: Association Instructions
Association Instructions Ladder block series connection, ladder block parallel connection ANB, ORB High Basic Process LCPU Redundant Universal performance Block A Block B Block A Block B For parallel connection of 1 contact, OR or ORI is used. Setting Internal device R, ZR J\...
Page 141 Program example • A program using the ANB and ORB instructions. [Ladder Mode] [List Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.2 Association Instructions...
Page 142: Operation Results Push, Operation Results Read, Operation Results Pop
Operation results push, operation results read, operation results MPS, MRD, MPP High Basic Process Redundant Universal LCPU performance In the ladder display, MPS, MRD and MPP are not displayed. Command Command Command Command Setting Internal device R, ZR J\ U\G Constant Others data...
Page 143 Operation error • There is no operation error in the MPS, MRD, or MPP instruction. Program example • A program using the MPS, MRD, and MPP instructions. [Ladder Mode] [List Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.2 Association Instructions...
Page 144 • A program using the MPS and MPP instructions successively. [Ladder Mode] [List Mode] Instruction Device Step 5 SEQUENCE INSTRUCTIONS 5.2 Association Instructions...
Page 145: Operation Results Inversion
Operation results inversion High Basic Process LCPU Redundant Universal performance Command Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Inverts the operation result immediately prior to the INV instruction. Operation result immediately prior to the INV instruction Operation result following the execution of the INV instruction Operation error •...
Page 146 • The INV instruction operates based on the results of calculation made until the INV instruction is given. Accordingly, use it in the same position as that of the AND instruction. The INV instruction cannot be used at the LD and OR positions. •...
Page 147: Operation Results Conversion
Operation results conversion MEP, MEF High Basic Process LCPU Redundant Universal performance Command Command Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details ■MEP • If operation results up to the MEP instruction are rising edge (from OFF to ON), goes ON (continuity status). If operation results up to the MEP instruction are anything other than rising edge, goes OFF (non-continuity status).
Page 148: Pulse Conversion Of Edge Relay Operation Results
Pulse conversion of edge relay operation results EGP, EGF High Basic Process Redundant Universal LCPU performance Command Command (D): Edge relay number where operation results are stored (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word ...
Page 149 Program example • A program using the EGP instruction in the subroutine program using the EGD instruction [Ladder Mode] [List Mode] Instruction Device Step [Operation] END processing Turns OFF as X0 remains ON. Turns ON at the leading Turns OFF as X1 remains ON. edge of X0.
Page 150: Output Instructions
Output Instructions Out (excluding timers, counters, and annunciators) High Basic Process LCPU Redundant Universal performance Bit device number (D) Command Word device bit designation (D) Command D0.5 (D): Number of the device to be turned ON and OFF (bits) Setting Internal device R, ZR J\...
Page 151 Program example • When using bit devices [Ladder Mode] [List Mode] Instruction Device Step • When bit designation has been made for word device [Ladder Mode] [List Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.3 Output Instructions...
Page 152: Low-Speed Timer, High-Speed Timer, Low-Speed Retentive Timer, High-Speed Retentive Timer
Low-speed timer, high-speed timer, low-speed retentive timer, high-speed retentive timer OUT T, OUTH T, OUT ST, OUTH ST High Basic Process Redundant Universal LCPU performance Command Set value Setting in the range from 1 to 32767 is valid. OUT T Timer number (D) (Low-speed timer) Command...
Page 153 Processing details • When the operation results up to the OUT instruction are ON, the timer coil goes ON and the timer counts up to the value that has been set; when the time up status (total numeric value is equal to or greater than the setting value), the contact responds as follows: •...
Page 154 Precautions When creating a program in which the operation of the timer contact triggers the operation of another timer, create the program for the timer that operates later first. In the following cases, all timers go ON at the same scan if the program is created in the order the timers operate. •...
Page 155 Program example • The following program turns Y10 and Y14 ON 10 seconds after X0 has gone ON. [Ladder Mode] [List Mode] Instruction Step Device (1) The setting value of the low-speed timer indicates its default time limit (100ms). • The following program uses the BCD data at X10 to X1F as the timer's set value. [Ladder Mode] Converts the BCD data at X10 to X1F to BIN and stores the converted value at D10.
Page 156: Counter
Counter OUT C High Basic Process Redundant Universal LCPU performance Set value Command Setting in the range from 1 to 32767 is valid. Counter number (D) OUT C Set value Command Data register value in the range from 1 to 32767 is valid. Counter number (D) (D): Counter number (bits) Setting value Counter setting value (BIN 16 bits...
Page 157 Program example • The following program turns Y30 ON after X0 has gone ON 10 times, and resets the counter when X1 goes ON. [Ladder Mode] [List Mode] Instruction Device Step • The following program sets the value for C10 at 10 when X0 goes ON, and at 20 when X1 goes ON. [Ladder Mode] Stores 10 at D0 when X0 goes ON.
Page 158: Annunciator Output
Annunciator output OUT F High Basic Process Redundant Universal LCPU performance Annunciator number (D) Command OUT F (D): Number of the annunciator to be turned ON (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word  (Only F) ...
Page 159 Program example • The following program turns F7 ON when X0 goes ON, and stores the value 7 from SD64 to SD79. [Ladder Mode] [List Mode] Instruction Device Step [Operation] X0 ON Adds 1 SD63 SD63 SD64 SD64 SD65 SD65 SD66 SD66 SD67...
Page 160: Setting Devices (Excluding Annunciators)
 (Other than T, ST, C)    When BL, S, TR, BL\S, or BL\TR is used, refer to the SFC control instructions in the MELSEC-Q/L/QnA Programming Manual (SFC). When F is used, refer to Page 162 Setting annunciators, resetting annunciators. Processing details •...
Page 161 Program example • The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9 goes ON. [Ladder Mode] [List Mode] Instruction Device Step • The following program sets the value of D0 bit 5 (b5) to 1 when X8 goes ON, and set the bit value to 0 when X9 goes ON. [Ladder Mode] [List Mode] Instruction...
Page 162: Resetting Devices (Excluding Annunciators)
Word    When BL, S, TR, BL\S, or BL\TR is used, refer to the SFC control instructions in the MELSEC-Q/L/QnA Programming Manual (SFC). When F is used, refer to Page 162 Setting annunciators, resetting annunciators. Processing details • When the execution command is turned ON, the status of the designated devices becomes as shown below:...
Page 163 Operation error • There is no operation error in the RST instruction. Program example • The following program sets the value of the data register to 0. [Ladder Mode] Stores the contents at X10 to X1F in D8 when X0 is turned ON. Resets D8 to 0 when X5 is turned ON.
Page 164: Setting Annunciators, Resetting Annunciators
Setting annunciators, resetting annunciators SET F, RST F High Basic Process Redundant Universal LCPU performance Command Command SET (D) : Number of the annunciator to be set (F number) (bits) RST (D) : Number of the annunciator to be reset (F number) (bits) Setting Internal device R, ZR...
Page 165 ■RST • The annunciator designated by (D) is turned OFF when the execution command is turned ON. • The annunciator numbers (F numbers) of annunciators that have gone OFF are deleted from the special registers (SD64 to SD79), and the value of SD63 is decremented by 1. •...
Page 166: Rising Edge Output, Falling Edge Output
Rising edge output, falling edge output PLS, PLF High Basic Process Redundant Universal LCPU performance Command Command (D): Pulse conversion device (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word    Processing details ■PLS •...
Page 167 ■PLF • Turns ON the designated device when the execution command is turned ON  OFF, and turns OFF the device in any other case the execution command is turned ON  OFF (i.e., at OFF  OFF, OFF  ON or ON  ON of the execution command).
Page 168 Program example • The following program executes the PLS instruction when X9 goes ON. [Ladder Mode] [List Mode] Step Instruction Device [Timing Chart] X9 OFF M9 OFF 1 scan • The following program executes the PLF instruction when X9 goes OFF. [Ladder Mode] [List Mode] Instruction...
Page 169: Bit Device Output Inversion
Bit device output inversion High Basic Process LCPU Redundant Universal performance Command (D): Device number of the device to be reversed (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word    Processing details • Reverses the output status of the device designated by (D) when the execution command is turned OFF  ON. Device Device status Prior to FF execution...
Page 170 • The following program reverses b10 (bit 10) of D10 when X0 goes ON. [Ladder Mode] [List Mode] Instruction Device Step [Timing Chart] D10 of b10 5 SEQUENCE INSTRUCTIONS 5.3 Output Instructions...
Page 171: Pulse Conversion Of Direct Output
Pulse conversion of direct output DELTA (P) High Basic Process LCPU Redundant Universal performance Command DELTA DELTA Command DELTAP DELTAP (D): Bit for which pulse conversion is to be conducted (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word...
Page 172 Program example The DELTA(P) instruction is used for setting preset values of high-speed counter modules. • The following program presets CH1 of the QD62 mounted at slot 0 of the main base unit, when X20 goes ON. [Ladder Mode] Stores the preset value (0) in the buffer memory addresses (0 and 1) of the QD62.
Page 173: Shift Instructions
Shift Instructions Bit device shift SFT(P) High Basic Process Redundant Universal LCPU performance Command Command SFTP SFTP (D): Head number of the devices to be shifted (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word  (Other than T, ST, C) ...
Page 174 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 175: Master Control Instructions
Master Control Instructions Setting the master control, resetting the master control MC, MCR High Basic Process Redundant Universal LCPU performance Command Master control ladder Nesting (N0 to N14) (Nesting) (D): Device number to be turned ON (bits) Setting Internal device R, ZR J\...
Page 176 ■MC • If the execution command of the MC instruction is ON when master control is started, the result of the operation from the MC instruction to the MCR instruction will be exactly as the instruction (ladder) shows. If the execution command of the MC instruction is OFF, the result of the operation from the MC instruction to the MCR instruction will be as shown below: Device Device status...
Page 177 Program example The master control instruction can be used in nesting. The different master control regions are distinguished by nesting (N). Nesting can be performed from N0 to N14. The use of nesting enables the creation of ladders which successively limit the execution condition of the program. A ladder using nesting would appear as shown below: [Ladder as displayed in the GPP ladder mode] [Ladder as it actually operates]...
Page 178 Precautions • Nesting can be used up to 15 times (N0 to N14). When using nesting, nests should be inserted from the lower to higher nesting number (N) with the MC instruction, and from the higher to the lower order with the MCR instruction. If this order is reversed, there will be no nesting architecture, and the CPU module will not be capable of performing correct operations.
Page 179: Termination Instructions
Termination Instructions Main routine program end FEND High Basic Process Redundant Universal LCPU performance FEND FEND Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • The FEND instruction is used in cases where the CJ instruction or other instructions are used to create a branch in the sequence program operations, and in cases where the main routine program is to be split from a subroutine program or an interrupt program.
Page 180 Program example • The following program uses the CJ instruction. [Ladder Mode] When XB is ON, the program jumps to label P23 and the steps that follow P23 are executed. Executed when XB is OFF. Indicates the termination of the sequence program to be executed when XB is OFF.
Page 181: Sequence Program End
Sequence program end High Basic Process LCPU Redundant Universal performance Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Indicates termination of programs, including main routine program, subroutine program, and interrupt programs. •...
Page 182 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 183: Other Instructions
Other Instructions Sequence program stop STOP High Basic Process Redundant Universal LCPU performance Command STOP STOP Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Resets the output (Y) and stops the CPU module operation when the execution command is turned ON. (The same result will take place if switch is turned to the STOP setting.) •...
Page 184 Program example • The following program stops the CPU module when X8 goes ON. [Ladder Mode] Stops the programmable controller when X8 goes ON. Sequence program [List Mode] Instruction Device Step 5 SEQUENCE INSTRUCTIONS 5.7 Other Instructions...
Page 185: No Operations
No operations NOP, NOPLF, PAGE n High Basic Process LCPU Redundant Universal performance In the ladder display, NOP is not displayed. Command NOPLF NOPLF PAGE n PAGE n Setting Internal device R, ZR J\ U\G Constant Others data Word Word ...
Page 186 Program example ■NOP • Contact closed: Deletes the AND or ANI instruction. [Ladder Mode] [List Mode] Before change Step Instruction Device Changing to NOP After change Instruction Device Step • Contact closed: LD, LDI changed to NOP. (Note carefully that changing the LD and LDI instructions to NOP completely changes the nature of the ladder.) [List Mode] [Ladder Mode]...
Page 187 ■NOPLF [Ladder Mode] [List Mode] Step Instruction Device • Printing the ladder will result in the following: NOPLF instruction, inserted as a delimiter NOPLF of ladder blocks, causes print out page to be changed forcibly. • Printing an instruction list with the NOPLF instruction will result in the following: NOPLF Changes print output page after printing NOPLF.
Page 188 ■PAGE n [List Mode] [Ladder Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.7 Other Instructions...
Page 189: Basic Instructions
BASIC INSTRUCTIONS Comparison Operation Instructions BIN 16-bit data comparisons LD, AND, OR High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (BIN 16 bits) Setting Internal device R, ZR...
Page 190 Program example • The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON if the data is identical. [Ladder Mode] [List Mode] Instruction Device Step • The following program compares BIN value K100 to the data at D3, and establishes continuity if the data in D3 is something other than 100.
Page 191: Bin 32-Bit Data Comparisons
BIN 32-bit data comparisons LDD, ANDD, ORD High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (BIN 32 bits) Setting Internal device R, ZR...
Page 192 Program example • The following program compares the data at X0 to X1F with the data at D3 and D4, and turns Y33 ON, if the data at X0 to X1F and the data at D3 and D4 match. [Ladder Mode] [List Mode] Device Step...
Page 193: Floating-Point Data Comparisons (Single Precision)
Floating-point data comparisons (single precision) LDE, ANDE, ORE Ver. High Basic Process Redundant Universal LCPU performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (real number) Setting Internal device R, ZR...
Page 194 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 195: Floating-Point Data Comparisons (Double Precision)
Floating-point data comparisons (double precision) LDED, ANDED, ORED High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ED Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (real number) Setting Internal device R, ZR...
Page 196 Program example • The following program compares 64-bit floating decimal point real number data at D0 to D3 with 64-bit floating decimal point real number data at D4 to D7. [Ladder Mode] [List Mode] Instruction Device Step • The following program compares the floating decimal point real number 1.23 with the 64-bit floating decimal point real number data at D4 to D7.
Page 197 Precautions • Since the number of digits of the real number that can be input by Programing Tool is up to 15 digits, the comparison with the real number whose number of significant digits is 16 or more cannot be made by the instruction shown in this section. When judging match/mismatch with the real number whose significant digits is 16 or more by the instruction in this section, compare it with the approximate values of the real number to be compared and judge by the sizes.
Page 198: Character String Data Comparisons
Character string data comparisons LD$, AND$, OR$ Basic High Process Redundant Universal LCPU performance indicates an instruction symbol of Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (character string) Setting Internal device R, ZR...
Page 199 • If the character strings are different, the first different sized character code will determine whether the character string is larger or smaller. (S1) (S2) (S1)+1 (S2)+1 (S1)+2 (S2)+2 "12345" "12435" Instruction symbol Comparison operation result Instruction symbol Comparison operation result Non-continuity $<= Continuity...
Page 200 Program example • The following program compares character strings stored following D0 and characters following D10. [Ladder Mode] [List Mode] Device Step Instruction • The following program compares the character string "ABCDEF" with the character string stored following D10. [Ladder Mode] [List Mode] Device Step...
Page 201: Bin 16-Bit Block Data Comparisons
BIN 16-bit block data comparisons BKCMP(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command BKCMP BKCMP Command BKCMP BKCMP (S1): Data to be compared or head number of the devices where the data to be compared is stored (BIN 16 bits) (S2): Head number of the devices where the comparison data is stored (BIN 16 bits) (D): Head number of the devices where the comparison operation result will be stored (bits) Number of comparison data blocks (BIN 16 bits)
Page 202 • The results of the comparison operations for the individual instructions are as follows: Instruction symbol Condition Comparison Instruction symbol Condition Comparison operation result operation result BKCMP= (S1)=(S2) ON (1) BKCMP= (S1)(S2) OFF (0) BKCMP<> (S1)(S2) BKCMP<> (S1)=(S2) BKCMP> (S1)>(S2) BKCMP>...
Page 203 • The following program compares, when X1C is turned ON, the constant K1000 with the data stored at D10 to D13, and stores the operation result at b4 to b7 in D0. [Ladder Mode] [List Mode] Device Step Instruction [Operation] 2000 (BIN) 1000 (BIN) 1000...
Page 204: Bin 32-Bit Block Data Comparisons
BIN 32-bit block data comparisons DBKCMP(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of Command DBKCMP DBKCMP Command DBKCMP...
Page 205 • The results of the comparison operations for the individual instructions are as follows: Instruction symbol Condition Comparison Instruction symbol Condition Comparison operation result operation result DBKCMP= (S1)=(S2) ON (1) DBKCMP= (S1)(S2) OFF (0) DBKCMP<> (S1)(S2) DBKCMP<> (S1)=(S2) DBKCMP> (S1)>(S2) DBKCMP>...
Page 206 • The following program compares the constant with the value data stored at D0 to D9, and then stores the operation result into D10.5 to D10.9, when M0 is turned on. [Ladder Mode] [List Mode] Instruction Device Step [Operation] -70000 D1,D0 D10.5 50000...
Page 207: Bin 16-Bit Data Comparisons (Small, Match, Large)
BIN 16-bit data comparisons (small, match, large) CMP(P) Ver. Ver. High Basic Process Redundant LCPU Universal performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command Command CMPP...
Page 208 Program example • Program that compares the value of D0 with the constant value K100 Compare K100 with D0. M0 turns on when K100 > D0. M1 turns on when K100 = D0. M2 turns on when K100 < D0. 6 BASIC INSTRUCTIONS 6.1 Comparison Operation Instructions...
Page 209: Bin 32-Bit Data Comparisons (Small, Match, Large)
BIN 32-bit data comparisons (small, match, large) DCMP(P) Ver. Ver. High Basic Process Redundant LCPU Universal performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command DCMP DCMP...
Page 210: Bin 16-Bit Data Band Comparisons
BIN 16-bit data band comparisons ZCP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command Command ZCPP ZCPP...
Page 211 Program example • Program that compares the band of the value of D0 with the lower limit value (K100) and the upper limit value (K120) Compare D0 with lower limit value (K100) and upper limit value (K120). M0 turns on when K100 > D0. M1 turns on when K100 ≤...
Page 212: Bin 32-Bit Data Band Comparisons
BIN 32-bit data band comparisons DZCP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command DZCP DZCP Command...
Page 213 Program example • Program that compares the bands of the values of D0 and D1 with the lower limit value (K100) and upper limit value (K120) Compare D0 and D1 with lower limit value (K100) and upper limit value (K120). M0 turns on when K100 >...
Page 214: Floating Point Comparisons (Single Precision)
Floating point comparisons (single precision) ECMP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command ECMP ECMP Command ECMPP ECMPP (S1): Comparison data or start number of the devices where the comparison data is stored (real number) (S2): Comparison data or start number of the devices where the comparison data is stored (real number) (D): Start bit device number to which the comparison result is output (Bit) Setting...
Page 215 Program example • Program that compares the values of D0 and D1 with the real number 1.23 [Ladder Mode] Compare E1.23 with D0 and D1. M0 turns on when E1.23 > D0 and D1. M1 turns on when E1.23 = D0 and D1. M2 turns on when E1.23 <...
Page 216: Floating Point Comparisons (Double Precision)
Floating point comparisons (double precision) EDCMP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command EDCMP EDCMP Command EDCMPP EDCMPP (S1): Comparison data or start number of the devices where the comparison data is stored (real number) (S2): Comparison data or start number of the devices where the comparison data is stored (real number) (D): Start bit device number to which the comparison result is output (Bit) Setting...
Page 217 Program example • Program that compares the values of D0 to D3 with the real number 1.23 [Ladder Mode] Compare E1.23 with D0 to D3. M0 turns on when E1.23 > D0 to D3. M1 turns on when E1.23 = D0 to D3. M2 turns on when E1.23 <...
Page 218: Floating Point Band Comparisons (Single Precision)
Floating point band comparisons (single precision) EZCP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command EZCP EZCP Command EZCPP EZCPP (S1): Start number of the devices where the lower limit value is stored (real number) (S2): Start number of the devices where the upper limit value is stored (real number) (S3): Data to be compared or start number of the device where the data to be compared is stored (real number) (D): Start bit device number to which the comparison result is output (Bit)
Page 219 Program example • Program that compares the values of D0 and D1 with the lower limit value (E-1.23) and upper limit value (E1.23) [Ladder Mode] Compare D0 and D1 with lower limit value (E-1.23) and upper limit value (E1.23). M0 turns on when E-1.23 > D0 and D1. M1 turns on when E-1.23 ≤...
Page 220: Floating Point Band Comparisons (Double Precision)
Floating point band comparisons (double precision) EDZCP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command EDZCP EDZCP Command EDZCPP EDZCPP (S1): Start number of the devices where the lower limit value is stored (real number) (S2): Start number of the devices where the upper limit value is stored (real number) (S3): Data to be compared or start number of the device where the data to be compared is stored (real number) (D): Start bit device number to which the comparison result is output (Bit)
Page 221 Program example • Program that compares the values of D0 to D3 with the lower limit value (E-1.23) and upper limit value (E1.23). [Ladder Mode] Compare D0 to D3 with lower limit value (E-1.23) and upper limit value (E1.23). M0 turns on when E-1.23 > D0 to D3. M1 turns on when E-1.23 ≤...
Page 222: Arithmetic Operation Instruction
Arithmetic Operation Instructions BIN 16-bit addition and subtraction operations +(P), -(P) [When two data are set] High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command Command +P, P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 16 bits) (D): Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) Setting Internal device...
Page 223 ■- • Subtracts 16-bit BIN data designated by (D) from 16-bit BIN data designated by (S) and stores the result of the subtraction at the device designated by (D). 5678 (BIN) 1234 (BIN) 4444 (BIN) • Values for (S) and (D) can be designated between -32768 and 32767 (BIN, 16 bits). •...
Page 224 +(P), -(P) [When three data are set] indicates an instruction symbol of Command Command +P, P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 16 bits) (D): Head number of the devices where the operation result will be stored (BIN 16 bits) Setting...
Page 225 Operation error • There is no operation error in the +(P) or -(P) instruction. Program example • The following program adds, when X5 is turned ON, the data at D3 and D0 and outputs the operation result at Y38 to Y3F. [Ladder Mode] [List Mode] Device...
Page 226: Bin 32-Bit Addition And Subtraction Operations
BIN 32-bit addition and subtraction operations D+(P), D-(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command D+, D Command D+P, D P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 32 bits) (D): Head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits) Setting Internal device...
Page 227 ■D- • Subtracts 32-bit BIN data designated by (D) from 32-bit BIN data designated by (S) and stores the result of the subtraction at the device designated by (D). D +1 b16 b15 b16 b15 b16 b15 567890 (BIN) 123456 (BIN) 444434 (BIN) •...
Page 228 D+(P), D-(P) [When three data are set] indicates an instruction symbol of D+/ D Command D+, D Command D+P, D P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 32 bits) (D): Head number of the devices where the multiplication/division operation result will be stored (BIN 32 bits) Setting...
Page 229 ■D- • Subtracts 32-bit BIN data designated by (S1) from 32-bit BIN data designated by (S2) and stores the result of the subtraction at the device designated by (D). b16 b15 b16 b15 b16 b15 567890 (BIN) 123456 (BIN) 444434 (BIN) •...
Page 230: Bin 16-Bit Multiplication And Division Operations
BIN 16-bit multiplication and division operations *(P), /(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of * Command *, / Command *P, / P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 16 bits) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 16 bits) (D): Head number of the devices where the multiplication/division operation result will be stored (BIN 32 bits) Setting...
Page 231 ■/ • Divides BIN 16-bit data designated by (S1) and BIN 16-bit data designated by (S2), and stores the result in the device designated by (D). Quotient Remainder 5678 (BIN) 1234 (BIN) 4 (BIN) 742 (BIN) • If a word device has been used, the result of the division operation is stored as 32 bits, and both the quotient and remainder are stored;...
Page 232: Bin 32-Bit Multiplication And Division Operations
BIN 32-bit multiplication and division operations D*(P), D/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command D*, D/ Command D*P, D/P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 32 bits) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 32 bits) (D): Head number of the devices where the multiplication/division operation result will be stored (BIN 64 bits) Setting...
Page 233 ■D/ • Divides BIN 32-bit data designated by (S1) and BIN 32-bit data designated by (S2), and stores the result in the device designated by (D). b31 b16 b31 b16 b31 b16 567890 (BIN) 123456 (BIN) 4 (BIN) 74066 (BIN) •...
Page 234: Bcd 4-Digit Addition And Subtraction Operations
BCD 4-digit addition and subtraction operations B+(P), B-(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of B+/B Command B+, B Command B+P, B P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 4 digits) (D): Head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits) Setting Internal device...
Page 235 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 236 B+(P), B-(P) [When three data are set] indicates an instruction symbol of B+/B- Command B+, B- Command B+P, B-P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 4 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting...
Page 237 Program example • The following program adds the D3 BCD data and the Z1 BCD data when X20 goes ON, and outputs the result to Y8 to Y17. [Ladder Mode] [List Mode] Step Instruction Device • The following program subtracts the BCD data at D20 from the BCD data at D10 when X20 goes ON, and stores the result at R10.
Page 238: Bcd 8-Digit Addition And Subtraction Operations
BCD 8-digit addition and subtraction operations DB+(P), DB-(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DB+/DB- Command DB+, DB- Command DB+P, DB-P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits) (D): Head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits) Setting Internal device...
Page 239 Operation error • In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/       4100 The (S) or (D) BCD data is outside the 0 to 99999999 range.
Page 240 DB+(P), DB-(P) [When three data are set] indicates an instruction symbol of DB+/ DB Command DB+, DB- Command DB+P, DB-P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits) (D): Head number of the devices where the addition/subtraction operation result is stored (BCD 8 digits) Setting...
Page 241 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 242: Bcd 4-Digit Multiplication And Division Operations
BCD 4-digit multiplication and division operations B*(P), B/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of B ,B/ Command , B/ Command P, B/P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 4 digits) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 4 digits) (D): Head number of the devices where the multiplication/division operation result will be stored (BCD 8 digits) Setting...
Page 243 Program example • The following program multiplies, when X20 is turned ON, the BCD data at X0 to XF by the BCD data at D8 and stores the operation result at D0 to D1. [Ladder Mode] [List Mode] Instruction Device Step [Operation] D1 (Upper 4 digits)
Page 244: Bcd 8-Digit Multiplication And Division Operations
BCD 8-digit multiplication and division operations DB*(P), DB/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DB* , DB/. Command DB , DB/ Command DB P, DB/P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 8 digits) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 8 digits) (D): Head number of the devices where the multiplication/division operation result will be stored (BCD 16 digits) Setting...
Page 245 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 246: Addition And Subtraction Of Floating-Point Data (Single Precision)
Addition and subtraction of floating-point data (single precision) E+(P), E-(P) [When two data are set] Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of E+/E- Command E+, E-...
Page 247 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 248 E+(P), E-(P) [When three data are set] indicates an instruction symbol of E+/E-. Command E+, E- Command E+P, E-P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting...
Page 249 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 250: Addition And Subtraction Of Floating-Point Data (Double Precision)
Addition and subtraction of floating-point data (double precision) ED+(P), ED-(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ED+/ED-. Command ED+, ED- Command ED+P, ED-P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) (D): Head number of the devices where the data to be added to/subtracted from is stored (real number) Setting Internal device...
Page 251 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 252 ED+(P), ED-(P) [When three data are set] indicates an instruction symbol of ED+/ED-. Command ED+, ED- Command ED+P, ED-P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting...
Page 253 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 254: Multiplication And Division Of Floating-Point Data (Single Precision)
Multiplication and division of floating-point data (single precision) E*(P), E/(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of E* , E/ Command E* , E/ Command...
Page 255 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 256: Multiplication And Division Of Floating-Point Data (Double Precision)
Multiplication and division of floating-point data (double precision) ED*(P), ED/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ED*, ED/. Command ED*, ED/ Command ED* P, ED/P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (real number) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting...
Page 257 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 258: Bin 16-Bit Data Block Addition And Subtraction Operations
BIN 16-bit data block addition and subtraction operations BK+(P), BK-(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BK+, BK- . Command BK+, BK- Command BK+P, BK-P (S1): Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 16 bits) (D): Head number of the devices where the operation result will be stored (BIN 16 bits) Number of addition/subtraction data blocks (BIN 16 bits)
Page 259 ■BK- • Subtracts n points of BIN data from the device designated by (S1) and n-points of BIN data from the device designated by (S2) and stores the result to the area starting from the device designated by (D). 8765 (BIN) 1234 (BIN)
Page 260 Program example • The following program adds, when X20 is turned ON, the data stored at D100 to D103 to the data stored at R0 to R3 and stores the operation result into the area starting from D200. [Ladder Mode] [List Mode] Step Instruction...
Page 261: Bin 32-Bit Data Block Addition And Subtraction Operations
BIN 32-bit data block addition and subtraction operations DBK+(P), DBK-(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of DBK+, DBK- . Command DBK+, DBK- (S1)
Page 262 • The following will happen if an overflow occurs in an operation result: The carry flag (SM700) in this case does not go ON. K2147483647 K 2147483647 ) ( 80000001 (00000002 (7FFFFFFF K2147483647 K 2147483647 ( FFFFFFFE ) ( 7FFFFFFF (80000001 ■DBK- •...
Page 263 Program example • The following program adds the value data stored at R0 to R5 to the constant, and then stores the operation result into D30 to D35, when M0 is turned on. [Ladder Mode] [List Mode] Device Step Instruction [Operation] 600000 723456...
Page 264: Linking Character Strings
Linking character strings $+(P) [When two data are set] Basic High Process Redundant Universal LCPU performance Command Command (S): Data for linking or head number of the devices where the data for linking is stored (character string) (D): Head number of the devices where the data to be linked is stored (character string) Setting Internal device R, ZR...
Page 265 Program example • The following program links the character string stored from D10 to D12 to the character string "ABCD" when X0 is ON. [Ladder Mode] [List Mode] Device Step Instruction [Operation] "ABCD" Automatically stores "00 ". 6 BASIC INSTRUCTIONS 6.2 Arithmetic Operation Instructions...
Page 266 $+(P) [When three data are set] Command Command (S1): Data for linking or head number of the devices where the data for linking is stored (character string) (S2): Data to be linked or head number of the devices where the data to be linked is stored (character string) (D): Head number of the devices where the linking result will be stored (character string) Setting Internal device...
Page 267: 16-Bit Bin Data Increment, 16-Bit Bin Data Decrement
16-bit BIN data increment, 16-bit BIN data decrement INC(P), DEC(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of INC/DEC. Command INC, DEC Command INCP, DECP (D): Head number of devices for INC (+1)/DEC (-1) operation (BIN 16 bits) Setting Internal device R, ZR...
Page 268 Program example • The following program outputs the present value at the counter C0 to C20 to the area Y30 to Y3F in BCD, every time X8 is turned ON. (When present value is less than 9999) [Ladder Mode] Outputs the present value of (0+Z1) to Y30 to Y3F in BCD.
Page 269: 32-Bit Bin Data Increment, 32-Bit Bin Data Decrement
32-bit BIN data increment, 32-bit BIN data decrement DINC(P), DDEC(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of DINC/DDEC. Command DINC, DDEC Command DINCP, DDECP (D): Head number of devices for DINC(+1) or DDEC(-1) operation (BIN 32 bits) Setting Internal device R, ZR...
Page 270 Program example • The following program adds 1 to the data at D0 and D1 when X0 is ON. [Ladder Mode] [List Mode] Instruction Device Step • The following program adds 1 to the data set at X10 to X27 when X0 goes ON, and stores the result at D3 and D4. [Ladder Mode] [List Mode] Device...
Page 271: Data Conversion Instructions
Data Conversion Instructions Conversion from BIN data to BCD 4-digit data, conversion from BIN data to BCD 8-digit data BCD(P), DBCD(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BCD/DBCD. Command BCD, DBCD Command BCDP, DBCDP (S): BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits) (D): Head number of the devices where BCD data will be stored (BCD 4/8 digits) Setting...
Page 272 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 273: Conversion From Bcd 4-Digit Data To Bin Data, Conversion From Bcd 8-Digit Data To Bin Data
Conversion from BCD 4-digit data to BIN data, conversion from BCD 8-digit data to BIN data BIN(P), DBIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BIN/DBIN. Command BIN, DBIN Command BINP, DBINP (S): BCD data or head number of the devices where the BCD data is stored (BCD 4/8 digits) (D): Head number of the devices where BIN data will be stored (BIN 16/32 bits) Setting Internal device...
Page 274 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 275: Conversion From Bin 16-Bit Data To Floating-Point Data (Single Precision), Conversion From Bin 32-Bit Data To Floating-Point Data (Single Precision)
Conversion from BIN 16-bit data to floating-point data (single precision), conversion from BIN 32-bit data to floating-point data (single precision) FLT(P), DFLT(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of FLT/DFLT.
Page 276 • Due to the fact that 32-bit floating decimal point type real numbers are processed by simple 32-bit processing, the number of significant digits is 24 bits if the display is binary and approximately 7 digits if the display is decimal. For this reason, if the integer exceeds the range of -16777216 to 16777215 (24-bit BIN value), errors can be generated in the conversion value.
Page 277: Conversion From Bin 16-Bit Data To Floating-Point Data (Double Precision), Conversion From Bin 32-Bit Data To Floating-Point Data (Double Precision)
Conversion from BIN 16-bit data to floating-point data (double precision), conversion from BIN 32-bit data to floating-point data (double precision) FLTD(P), DFLTD(P) High Basic Process Redundant LCPU Universal performance indicates an instruction symbol of FLTD/DFLTD. Command FLTD, DFLTD Command FLTDP, DFLTDP (S): Integer data to be converted to 64-bit floating decimal point data or head number of the devices where the integer data is stored (BIN 16/32 bits) (D): Head number of the devices where the converted 64-bit floating decimal point data will be stored (real number) Setting...
Page 278 Program example • The following program converts the BIN 16-bit data at D20 to a 64-bit floating decimal point type real number and stores the result at D0 to D3. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Conversion to real number 15923 15923 BIN value...
Page 279: Conversion From Floating-Point Data To Bin 16-Bit Data (Single Precision), Conversion From Floating-Point Data To Bin 32-Bit Data (Single Precision)
Conversion from floating-point data to BIN 16-bit data (single precision), conversion from floating-point data to BIN 32-bit data (single precision) INT(P), DINT(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of INT/DINT.
Page 280 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/Q01 4140 The specified device value is not within the following range: ...
Page 281: Conversion From Floating-Point Data To Bin 16-Bit Data (Double Precision), Conversion From Floating-Point Data To Bin 32-Bit Data (Double Precision)
Conversion from floating-point data to BIN 16-bit data (double precision), conversion from floating-point data to BIN 32-bit data (double precision) INTD(P), DINTD(P) High Basic Process Redundant LCPU Universal performance indicates an instruction symbol of INTD/DINTD. Command INTD, DINTD Command INTDP, DINTDP (S): 64-bit floating decimal point data to be converted to BIN value or head number of the devices where the floating decimal point data is stored (real number) (D): Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits) Setting...
Page 282 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/Q01 (S) is -0, a subnormal number, NaN (not a number), , or a 4140 ...
Page 283: Conversion From Bin 16-Bit To Bin 32-Bit Data
Conversion from BIN 16-bit to BIN 32-bit data DBL(P) High Basic Process LCPU Redundant Universal performance Command Command DBLP DBLP (S): BIN 16-bit data or head number of the devices where the BIN 16-bit data is stored (BIN 16 bits) (D): Head number of the devices where the converted BIN 32-bit data will be stored (BIN 32 bits) Setting Internal device...
Page 284: Conversion From Bin 32-Bit To Bin 16-Bit Data
Conversion from BIN 32-bit to BIN 16-bit data WORD(P) High Basic Process Redundant Universal LCPU performance Command WORD WORD Command WORDP WORDP (S): BIN 32-bit data or head number of the devices where the BIN 32-bit data is stored (BIN 32 bits) (D): Head number of the devices where the converted BIN 16-bit data will be stored (BIN 16 bits) Setting Internal device...
Page 285: Conversion From Bin 16-Bit Data To Gray Code, Conversion From Bin 32-Bit Data To Gray Code
Conversion from BIN 16-bit data to Gray code, conversion from BIN 32-bit data to Gray code GRY(P), DGRY(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of GRY, DGRY. Command GRY, DGRY Command GRYP, DGRYP (S): BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits) (D): Head number of the devices where the converted Gray code will be stored (BIN 16/32 bits) Setting Internal device...
Page 286 Program example • The following program converts the BIN data at D100 to Gray code when X10 is ON, and stores result at D200. [Ladder Mode] [List Mode] Device Step Instruction • The following program converts the BIN data at D10 and D11 to Gray code when X1C is ON, and stores it at D100 and D101.
Page 287: Conversion From Gray Code To Bin 16-Bit Data, Conversion From Gray Code To Bin 32-Bit Data
Conversion from Gray code to BIN 16-bit data, conversion from Gray code to BIN 32-bit data GBIN(P), DGBIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of GBIN/DGBIN. Command GBIN, DGBIN Command GBINP, DGBINP (S): Gray code data or head number of the devices where the Gray code data is stored (BIN 16/32 bits) (D): Head number of the devices where the converted BIN data will be stored (BIN 16/32 bits) Setting Internal device...
Page 288 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 289: Complement Of 2 Of Bin 16-Bit Data (Sign Inversion), Complement Of 2 Of Bin 32-Bit Data (Sign Inversion)
Complement of 2 of BIN 16-bit data (sign inversion), complement of 2 of BIN 32-bit data (sign inversion) NEG(P), DNEG(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of NEG/DNEG. Command NEG, DNEG Command NEGP, DNEGP (D): Head number of the devices where the data for which complement of 2 is performed is stored (BIN 16/32 bits) Setting Internal device R, ZR...
Page 290 Program example • The following program calculates a total for the data at D10 through D20 when XA goes ON, and seeks an absolute value if the result is negative. [Ladder Mode] M3 is turned ON if D10 < D20. Executes "D10 - D20".
Page 291: Floating-Point Sign Inversion (Single Precision)
Floating-point sign inversion (single precision) ENEG(P) Ver. High Basic Process Redundant Universal LCPU performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command ENEG ENEG Command ENEGP ENEGP (D): Head number of the devices where the 32-bit floating decimal point data whose sign is to be reversed is stored (real number) Setting Internal device R, ZR...
Page 292: Floating-Point Sign Inversion (Double Precision)
Floating-point sign inversion (double precision) EDNEG(P) High Basic Process Redundant Universal LCPU performance Command EDNEG EDNEG Command EDNEGP EDNEGP (D): Head number of the devices where the 64-bit floating decimal point data whose sign is to be reversed is stored (real number) Setting Internal device R, ZR...
Page 293: Conversion From Block Bin 16-Bit Data To Bcd 4-Digit Data
Conversion from block BIN 16-bit data to BCD 4-digit data BKBCD(P) High Basic Process LCPU Redundant Universal performance Command BKBCD BKBCD Command BKBCDP BKBCDP (S): Head number of the devices where BIN data is stored (BIN 16 bits) (D): Head number of the devices where the converted BCD data will be stored (BCD 4 digits) Number of variable data blocks (BIN 16 bits) Setting Internal device...
Page 294 Program example • The following program converts, when X20 is turned ON, the BIN data stored at D100 to D102 to BCD and stores the operation result into the area starting from D200. [Ladder Mode] [List Mode] Instruction Device Step [Operation] D100 BIN 5432 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0...
Page 295: Conversion From Block Bcd 4-Digit Data To Block Bin 16-Bit Data
Conversion from block BCD 4-digit data to block BIN 16-bit data BKBIN(P) High Basic Process LCPU Redundant Universal performance Command BKBIN BKBIN Command BKBINP BKBINP (S): Head number of the devices where BCD data is stored (BCD 4 digits) (D): Head number of the devices where the converted BIN data will be stored (BIN 16 bits) Number of variable data blocks (BIN 16 bits) Setting Internal device...
Page 296 Program example • The following program converts, when X20 is turned ON, the BCD data stored at D100 to D102 to BIN and stores the operation result into the area starting from D200. [Ladder Mode] [List Mode] Device Step Instruction [Operation] D100 BCD 8080 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0...
Page 297: Conversion From Single Precision To Double Precision
Conversion from single precision to double precision ECON(P) High Basic Process Redundant Universal LCPU performance Command ECON ECON Command ECONP ECONP (S): Conversion source data, or head number of the device where conversion source data is stored (Real number (single precision)) (D): Head number of the device where the converted data is stored (Real number (double precision)) Setting Internal device...
Page 298: Conversion From Double Precision To Single Precision
Conversion from double precision to single precision EDCON(P) High Basic Process Redundant Universal LCPU performance Command EDCON EDCON Command EDCONP EDCONP (S): Conversion source data, or head number of the device where conversion source data is stored (Real number (double precision)) (D): Head number of the device where the converted data is stored (Real number (single precision)) Setting Internal device...
Page 299: Data Transfer Instruction
    When BL, S, TR, BL\S, or BL\TR is used, refer to the SFC control instructions in the MELSEC-Q/L/QnA Programming Manual (SFC). Processing details ■MOV • Transfers the 16-bit data from the device designated by (S) to the device designated by (D).
Page 300 Program example • The following program stores input data from X0 to XB at D8. [Ladder Mode] [List Mode] Instruction Device Step • The following program stores the constant K155 at D8 when X8 goes ON. [Ladder Mode] [List Mode] Device Step Instruction...
Page 301: Floating-Point Data Transfer (Single Precision)
Floating-point data transfer (single precision) EMOV(P) Ver. High Basic Process Redundant Universal LCPU performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command EMOV EMOV Command EMOVP EMOVP (S): Data to be transferred or number of the device to which the data to be transferred is stored (real number) (D): The number of the device to which the transferred data will be stored (real number) Setting Internal device...
Page 302 Program example • The following program stores the real numbers at D10 and D11 at D0 and D1. [Ladder Mode] [List Mode] Instruction Device Step [Operation] 36.475 36.475 • The following program stores the real number -1.23 at D10 and D11 when X8 is ON. [Ladder Mode] [List Mode] Device...
Page 303: Floating-Point Data Transfer (Double Precision)
Floating-point data transfer (double precision) EDMOV(P) High Basic Process Redundant Universal LCPU performance Command EDMOV EDMOV Command EDMOVP EDMOVP (S): Data to be transferred or number of the device to which the data to be transferred is stored (real number) (D): The number of the device to which the transferred data will be stored (real number) Setting Internal device...
Page 304: Character String Transfer
Character string transfer $MOV(P) High Basic Process Redundant Universal LCPU performance Command $MOV $MOV Command $MOVP $MOVP (S): Character string to be transferred (maximum string length: 32 characters) or head number of the devices where the character string to be transferred is stored (character string) (D): Head number of the devices where the transferred character string will be stored (character string) Setting...
Page 305 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored in SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 306: 16-Bit Data Negation Transfer, 32-Bit Data Negation Transfer
16-bit data negation transfer, 32-bit data negation transfer CML(P), DCML(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of CML, DCML. Command CML, DCML Command CMLP, DCMLP (S): Data to be reversed or the number of the device where data to be reversed is stored (BIN 16/32 bits) (D): Number of the device where the reversing result will be stored (BIN 16/32 bits) Setting Internal device...
Page 307 Program example • The following program inverts the data from X0 to X7, and transfers result to D0. [Ladder Mode] [List Mode] Instruction Device Step [Operation] If "Number of bits of < Number of bits of " These bits are all regarded as 0. 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 •...
Page 308 • The following program inverts the data at X0 to X1F, and transfers results to D0 and D1. [Ladder Mode] [List Mode] Instruction Device Step [Operation] If "Number of bits of < Number of bits of " X8 X7 These bits are all regarded as 0. 0 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 b28 b27...
Page 309: Block 16-Bit Data Transfer
   When BL, S, TR, BL\S, or BL\TR is used, refer to the SFC control instructions in the MELSEC-Q/L/QnA Programming Manual (SFC). Processing details • Transfers in batch 16-bit data of n points from the device designated by (S) to location n points from the device designated by (D).
Page 310 Transfer ranges of ZR and R overlap when transferring 10000 blocks of data from ZR30000 (source) to R10 (block No.1 of the destination). • ZR transfer range  (30000) to (30000+10000-1)  (30000) to (39999) • R transfer range  (10+(132768)) to (10+(132768)+10000-1)  (32778) to (42777) Therefore, the range 32778 to 39999 overlaps and the data is not correctly transferred.
Page 311 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 312: Identical 16-Bit Data Block Transfer
Identical 16-bit data block transfer FMOV(P) High Basic Process Redundant Universal LCPU performance Command FMOV FMOV Command FMOVP FMOVP (S): Data to be transferred or the head number of the devices where the data to be transferred is stored (BIN 16 bits) (D): Head number of the devices of transfer destination (BIN 16 bits) Number of data to be transferred (BIN 16 bits) Setting...
Page 313 SM237 is available only for the following CPU modules. • The Universal model QCPU whose serial number (first five digits) is "10012" or later, • LCPU Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/...
Page 314: Identical 32-Bit Data Block Transfer
Identical 32-bit data block transfer DFMOV(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Command DFMOV DFMOV Command DFMOVP DFMOVP (S): Data to be transferred or head number of the devices where the data to be transferred are stored (BIN 32 bits) (D): Head number of the devices of transfer destination (BIN 32 bits) Number of data to be transferred (BIN 16 bits) Setting...
Page 315 • If (D) specifies data of a device with digit specification, the amount of data stored in the device specified by (D) will be transferred. If K5Y0 is specified by (D), the lower 20 bits of the word device specified by (S) will be the object. If both (S) and (D) specify data of a device with digit specification, the amount of data specified by (D) will be transferred regardless of the number of digits.
Page 316: 16-Bit Data Exchanges, 32-Bit Data Exchanges
16-bit data exchanges, 32-bit data exchanges XCH(P), DXCH(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of XCH, DXCH. Command XCH, DXCH Command XCHP, DXCHP (D1), (D2): Head number of the devices where the data to be exchanged is stored (BIN 16/32 bits) Setting Internal device R, ZR...
Page 317 Program example • The following program exchanges the present value of T0 with the contents of D0 when X8 goes ON. [Ladder Mode] [List Mode] Instruction Device Step • The following program exchanges the contents of D0 with the data from M16 to M31 when X10 goes ON. [Ladder Mode] [List Mode] Instruction...
Page 318: Block 16-Bit Data Exchanges
Block 16-bit data exchanges BXCH(P) High Basic Process Redundant Universal LCPU performance Command BXCH BXCH Command BXCHP BXCHP (D1), (D2) : Head number of the devices where the data to be exchanged is stored (BIN 16 bits) Number of exchanges (BIN 16 bits) Setting Internal device R, ZR...
Page 319 Program example • The following program exchanges 16-bit data for 3 points from D200 for 16-bit data for 3 points from R0 when X1C goes [Ladder Mode] [List Mode] Instruction Device Step [Operation] D200 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 D201 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0...
Page 320: Upper And Lower Byte Exchanges
Upper and lower byte exchanges SWAP(P) High Basic Process Redundant Universal LCPU performance Command SWAP SWAP Command SWAPP SWAPP (D): Head number of the devices where the data is stored (BIN 16 bits) Setting Internal device R, ZR J\ U\G Constant Others data...
Page 321: Shift
Shift SMOV(P) Ver. Ver. High Basic Process Redundant LCPU Universal performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command SMOV SMOV Command SMOVP SMOVP (S): Start number of the devices where the data of the specified digit is stored (Device name) Start position where data to be moved is stored (BIN 16 bits)
Page 322 • When the digit specification by bit is conducted for the transfer source device, the digit corresponding to the specified digit number  4 is specified from the bit device at head. The operation examples are shown below. [ SMOV K3X0 K3 K2 K2X100 K2 ] Start bit device Specified digits 12 bits (specified digits 3 ×...
Page 323: Program Branch Instructions
Program Branch Instructions Pointer branch CJ, SCJ, JMP High Basic Process Redundant Universal LCPU performance Command Command Label Command P**: Pointer number of jump destination (Device name) Setting Internal device R, ZR J\ U\G Constant Others data Word Word  ...
Page 324 Note the following points when using the jump instruction. • After the timer coil has gone ON, accurate measurements cannot be made if there is an attempt to jump the timer of a coil that has been turned ON using the CJ, SCJ or JMP instructions. •...
Page 325 Program example • The following program jumps to P3 when X9 goes ON. [Ladder Mode] [List Mode] Device Step Instruction • The following program jumps to P3 from the next scan after XC goes ON. [Ladder Mode] [List Mode] Step Instruction Device Precautions...
Page 326: Jump To End
Jump to END GOEND High Basic Process Redundant Universal LCPU performance Command GOEND GOEND Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Jumps to the FEND or END instruction in the same program file. Operation error •...
Page 327: Program Execution Control Instructions
Program Execution Control Instructions Interrupt disable, interrupt enable, interrupt program mask DI, EI, IMASK High Basic Process LCPU Redundant Universal performance ■When the Basic model QCPU is used Sequence program IMASK IMASK (S): Interrupt mask data or head number of the devices where the interrupt mask data is stored (BIN 16 bits) Setting Internal device R, ZR...
Page 328 ■IMASK • Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 8 points from the device designated by (S). • 1(ON)  Interrupt program execution enabled • 0(OFF)  Interrupt program execution disabled •...
Page 329 Program example • The following program is designed to enable the execution of only the interrupt programs having the interrupt pointer numbers I1 and I3 while X0 is ON. [Ladder Mode] [List Mode] Device Step Instruction 6 BASIC INSTRUCTIONS 6.6 Program Execution Control Instructions...
Page 330 DI, EI, IMASK ■When the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU or LCPU is used Sequence program IMASK IMASK (S): Head number of the devices where the interrupt mask data is stored (BIN 16 bits) Setting Internal device R, ZR J\...
Page 331 ■IMASK • Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 16 points from the device designated by (S). • 1(ON)  Interrupt program execution enabled • 0(OFF)  Interrupt program execution disabled •...
Page 332 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 333: Recovery From Interrupt Programs
Recovery from interrupt programs IRET High Basic Process LCPU Redundant Universal performance IRET IRET Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Indicates the completion of interrupt program processing. • Returns to sequence program processing following the execution of the IRET instruction. Operation error •...
Page 334: I/O Refresh Instructions
I/O Refresh Instructions I/O refresh RFS(P) High Basic Process LCPU Redundant Universal performance Command Command RFSP RFSP (S): Head number of the devices to be refreshed (bits) Number of refreshes (BIN 16 bits) Setting Internal device R, ZR J\ U\G Constant Others data...
Page 335 Program example • The following program refreshes X100 to X11F and Y200 to Y23F when M0 goes ON. [Ladder Mode] [List Mode] Instruction Device Step 6 BASIC INSTRUCTIONS 6.7 I/O Refresh Instructions...
Page 336: Other Convenient Instructions
Other Convenient Instructions Counter 1-phase input up or down UDCNT1 Basic High Redundant Process LCPU Universal performance Command UDCNT1 UDCNT1 (S): (S)+0: Input number for count input (bits) (S)+1: For setting count up/down (bits)  OFF  Count up (add numbers when counting) ...
Page 337 • With the UDCNT1 instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOPRUN.) For this reason, the pulses that can be counted must have longer ON and OFF times than the interrupt interval of the CPU module.
Page 338: Counter 2-Phase Input Up Or Down
Counter 2-phase input up or down UDCNT2 Basic High Redundant Process Universal LCPU performance Command UDCNT2 UDCNT2 (S): (S)+0: Input number for count input (A phase pulse) (bits) (S)+1: Input number for count input (B phase pulse) (bits) (D): Number of the counter to be enabled to start counting with the UDCNT2 instruction (Device name) Value to set (BIN 16 bits) Setting Internal device...
Page 339 • With the UDCNT2 instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOPRUN.) For this reason, the pulses that can be counted must have longer ON and OFF times than the interrupt interval of the CPU module.
Page 340: Teaching Timer
Teaching timer TTMR Basic High Redundant Process Universal LCPU performance Command TTMR TTMR (D): (D)+0: The device where measurement value is stored (BIN 16 bit) (D)+1: For CPU module system use (BIN 16 bit) Measurement value multiplier (BIN 16 bits) Setting Internal device R, ZR...
Page 341 Program example • The following program stores the amount of time that X0 is ON at D0. [Ladder Mode] [List Mode] Instruction Device Step 6 BASIC INSTRUCTIONS 6.8 Other Convenient Instructions...
Page 342: Special Function Timer
Special function timer STMR Basic High Redundant Process Universal LCPU performance Command STMR STMR (S): Timer number (word) Value to set (BIN 16 bits). (D): (D)+0: Off delay timer output (bits) (D)+1: One shot timer output after OFF (bits) (D)+2: One shot timer output after ON (bits) (D)+3: ON delay and Off delay timer output (bits) Setting Internal device...
Page 343 • The timer contact goes ON at the rising edge of the command for the STMR instruction, and after the falling edge is reached, the timer coil goes OFF at the falling edge of the STMR instruction command. The timer contact is used by the CPU module system, and cannot be used by the user.
Page 344 Program example • The following program turns Y0 and Y1 ON and OFF once each second (flicker) when X20 is ON. (Uses 100ms timer) [Ladder Mode] [List Mode] Instruction Device Step [Timing Chart] M1, Y0 M2, Y1 1 sec 1 sec Precautions Note that the STMR instruction operates when the instruction is used within the range written data by the online program change.
Page 345: Rotary Table Shortest Direction Control
Rotary table shortest direction control ROTC Basic High Redundant Process Universal LCPU performance Command ROTC ROTC (S): (S)+0: Measures the number of table rotations (for system use) (BIN 16 bits) (S)+1: Call station number (BIN 16 bits) (S)+2: Call item number (BIN 16 bits) Number of divisions of table (2 to 32767) (BIN 16 bits) Number of low-speed sections (value from 0 to less than n1) (BIN 16 bits) (D): (D)+0: A phase input signal (bits)
Page 346 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 347: Ramp Signal
Ramp signal RAMP Basic High Redundant Process Universal LCPU performance Command RAMP RAMP Initial value (BIN 16 bits) Final value (BIN 16 bits) (D1): (D1)+0: Present value (BIN 16 bits) (D1)+1: Number of executions (BIN 16 bits) Number of shifts (BIN 16 bits) (D2): (D2)+0: Completion device (bits) (D2)+1: Bit for selecting data retaining at completion (bit) Setting...
Page 348 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 349: Pulse Density Measurement
Pulse density measurement Basic High Redundant Process Universal LCPU performance Command (S): Number for the device to which pulses are input (bits) Measurement time or the number for the device where the measurement time is stored (unit: ms) (BIN 16 bits) (D): Devices where the measurement results will be stored (BIN 16 bits) Setting Internal device...
Page 350 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 351: Fixed Cycle Pulse Output
Fixed cycle pulse output PLSY Basic High Redundant Process Universal LCPU performance Command PLSY PLSY Frequency or the number of the device where frequency is stored (BIN 16 bits) Outputs count or the number of the device where the outputs count is stored (BIN 16 bits) (D): Number of the device to which pulses are output (bits) Setting Internal device...
Page 352 Program example • The following program outputs a 10Hz pulse 5 times to Y20 when X0 is ON. [Ladder Mode] [List Mode] Instruction Device Step 6 BASIC INSTRUCTIONS 6.8 Other Convenient Instructions...
Page 353: Pulse Width Modulation
Pulse width modulation Basic High Redundant Process Universal LCPU performance Command ON time or the number for the device where the ON time is stored (unit: ms) (BIN 16 bits) Frequency or the number for the device where the frequency is stored (unit: ms) (BIN 16 bits) (D): Number of the device to which pulses are output (bits) Setting Internal device...
Page 354 Program example • The following program outputs a 100ms pulse once each second to Y20 when X0 is ON. [Ladder Mode] [List Mode] Instruction Device Step 6 BASIC INSTRUCTIONS 6.8 Other Convenient Instructions...
Page 355: Matrix Input
Matrix input Basic High Redundant Process Universal LCPU performance Command (S): Head input device (bits) (D1): Head output device (bits) (D2): Head number of the devices where matrix input data will be stored (bits) Number of input rows (BIN 16 bit) Setting Internal device R, ZR...
Page 356 Program example • The following program fetches, when X0 is turned ON, the 16 points3 matrix starting from X10, and stores the matrix into the area starting from M0. [Ladder Mode] [List Mode] Instruction Device Step [Operation] 3rd row X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F...
Page 357: Application Instructions
APPLICATION INSTRUCTIONS Logical Operation Instructions The logical operation instructions perform logical sum, logical product or other logical operations in 1-bit units. Category Processing details Formula for operation Example Y = A  B Logical product Becomes 1 only when both input A and input B are 1; (AND) otherwise, is 0 Logical sum...
Page 358: Logical Products With 16-Bit Data, Logical Products With 32-Bit Data
Logical products with 16-bit data, logical products with 32-bit data WAND(P), DAND(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of WAND/DAND. Command WAND,DAND Command WANDP,DANDP (S): Data for a logical product operation or the head number of the devices where the data is stored (BIN 16/32 bits) (D): Head number of the devices where the logical product operation result will be stored (BIN 16/32 bits) Setting Internal device...
Page 359 Operation error • There is no operation error in the WAND(P) or DAND(P) instruction. Program example • The following program masks the digit in the 10s place of the 4-digit BCD value at D10 (second digit from the end) to 0 when XA is turned ON.
Page 360 WAND(P), DAND(P) [When three data are set] indicates an instruction symbol of WAND/DAND. Command WAND,DAND Command WANDP,DANDP (S1), (S2) : Data for a logical product operation or the head number of the devices where the data is stored (BIN 16/32 bits) (D): Head number of the devices where the logical product operation result will be stored (BIN 16/32 bits) Setting Internal device...
Page 361 Operation error • There is no operation error in the WAND(P) or DAND(P) instruction. Program example • The following program performs a logical product operation on the data from X10 to X1B and the data at D33 when XA is ON, and stores the results at D40.
Page 362 • The following program masks the digit in the hundred-thousands place of the 8-digit BCD value at D10 and D11 (sixth digit from the end) to 0 when XA is ON, and outputs the results to from Y10 to Y2B. [Ladder Mode] [List Mode] Step...
Page 363: Block Logical Products
Block logical products BKAND(P) High Basic Process LCPU Redundant Universal performance Command BKAND BKAND Command BKANDP BKANDP (S1) : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) (S2) : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) : Head number of the devices where the operation result will be stored (BIN 16 bits) Number of operation data blocks (BIN 16 bits)
Page 364 • The constant designated by (S2) can be between -32768 and 32767 (BIN 16-bit data). 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 b8 b7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BKAND...
Page 365: Logical Sums Of 16-Bit Data, Logical Sums Of 32-Bit Data
Logical sums of 16-bit data, logical sums of 32-bit data WOR(P), DOR(P) [When two data are set] High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of WOR/DOR. Command WOR, DOR Command WORP, DORP (S): Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits) (D): Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits) Setting Internal device...
Page 366 Operation error • There is no operation error in the WOR(P) or DOR(P) instruction. Program example • The following program performs a logical sum operation on the data at D10 and D20 when XA is turned ON, and stores the results at D10.
Page 367 WOR(P), DOR(P) [When three data are set] indicates an instruction symbol of WOR/DOR. Command WOR, DOR Command WORP, DORP (S1), (S2): Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits) (D): Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits) Setting Internal device...
Page 368 Operation error • There is no operation error in the WOR(P) or DOR(P) instruction. Program example • The following program performs a logical sum operation on the data from X10 to X1B, and the data at D33, and stores the result at Y30 to Y3B when XA is ON.
Page 369: Block Logical Sum Operations
Block logical sum operations BKOR(P) High Basic Process LCPU Redundant Universal performance Command BKOR BKOR Command BKORP BKORP (S1) : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) (S2) : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) : Head number of the devices where the operation result will be stored (BIN 16 bits)
Page 370 • The constant designated by (S2) can be between -32768 and 32767 (BIN 16-bit data). 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1...
Page 371: 16-Bit Exclusive Or Operations, 32-Bit Exclusive Or Operations
16-bit exclusive OR operations, 32-bit exclusive OR operations WXOR(P), DXOR(P) [When two data are set] High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of WXOR/DXOR. Command WXOR, DXOR Command WXORP, DXOR (S): Data for an exclusive OR operation or head number of the devices where the data is stored (BIN 16/32 bits) (D): Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits) Setting Internal device...
Page 372 Operation error • There is no operation error in the WXOR(P) or DXOR(P) instruction. Program example • The following program performs an exclusive OR operation on the data at D10 and D20 when XA is ON, and stores the result at D10. [Ladder Mode] [List Mode] Step...
Page 373 WXOR(P), DXOR(P) [When three data are set] indicates an instruction symbol of WXOR/DXOR. Command WXOR, DXOR Command WXORP, DXORP (S1), (S2): Data for an exclusive OR operation or head number of the devices where the data is stored (BIN 16/32 bits) (D): Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits) Setting Internal device...
Page 374 Operation error • There is no operation error in the WXOR(P) or DXOR(P) instruction. Program example • The following program conducts an exclusive OR operation on the data from X10 to X1B and the data at D33 when X10 is ON, and outputs the result to Y30 to Y3B.
Page 375: Block Exclusive Or Operations
Block exclusive OR operations BKXOR(P) High Basic Process LCPU Redundant Universal performance Command BKXOR BKXOR Command BKXORP BKXORP (S1) : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) (S2) : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) : Head number of the devices where the operation result will be stored (BIN 16 bits)
Page 376 • The constant designated by (S2) can be between -32768 and 32767 (BIN 16-bit data). 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 +(n 2)
Page 377: 16-Bit Data Exclusive Nor Operations, 32-Bit Data Exclusive Nor Operations
16-bit data exclusive NOR operations, 32-bit data exclusive NOR operations WXNR(P), DXNR(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of WXNR/DXNR. Command WXNR, DXNR Command WXNRP, DXNRP (S): Data for an exclusive NOR operation or head number of the devices where the data is stored (BIN 16/32 bits) (D): Head number of the devices where the exclusive NOR operation result will be stored (BIN 16/32 bits) Setting Internal device...
Page 378 Operation error • There is no operation error in the WXNR(P) or DXNR(P) instruction. Program example • The following program compares the bit patterns of the 16-bit data located from X30 to X3F with the bit patterns of the 16- bit data at D99 when XC is ON, and stores the number of identical bit patterns at D7.
Page 379 WXNR(P), DXNR(P) [When three data are set] indicates an instruction symbol of WXNR/DXNR. Command WXNR, DXNR Command WXNRP, DXNRP (S1), (S2): Data for an exclusive NOR operation or head number of the devices where the data is stored (BIN 16/32 bits) (D): Head number of the devices where the exclusive NOR operation result will be stored (BIN 16/32 bits) Setting Internal device...
Page 380 Operation error • There is no operation error in the WXNR(P) or DXNR(P) instruction. Program example • The following program performs an exclusive NOR operation on the 16-bit data from X30 to X3F and the data at D99 when X0 is turned ON, and stores the results to D7. [Ladder Mode] [List Mode] Step...
Page 381: Block Exclusive Nor Operations
Block exclusive NOR operations BKXNR(P) High Basic Process LCPU Redundant Universal performance Command BKXNR BKXNR Command BKXNRP BKXNRP (S1) : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) (S2) : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) : Head number of the devices where the operation result will be stored (BIN 16 bits)
Page 382 • The constant designated by (S2) can be between -32768 and 32767 (BIN 16-bit data). 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 b8b7 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0...
Page 383: Rotation Instructions
Rotation Instructions Right rotation of 16-bit data ROR(P), RCR(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ROR/RCR. Command ROR, RCR Command RORP, RCRP (D): Head number of the devices to rotate (BIN 16 bits) Number of rotations (0 to 15) (BIN 16 bits) Setting Internal device R, ZR...
Page 384 ■RCR • Rotates 16-bit data of the device designated by (D), including the carry flag, n-bits to the right. The carry flag is ON or OFF depending on the status prior to the execution of the ROR instruction. Carry flag (SM700) b14 b13 b12 b11 b10 b9 b6 b5 b4 b3 b2 b1 b0...
Page 385 Program example • The following program rotates the contents of D0, not including the carry flag, 3 bits to the right when XC is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Carry flag (SM700) b14 b13 b12 b11b10 b9 b6 b5 b4 b3 b2 b1 Carry flag (SM700)
Page 386: Left Rotation Of 16-Bit Data
Left rotation of 16-bit data ROL(P), RCL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ROL/RCL. Command ROL, RCL Command ROLP, RCLP (D): Head number of the devices to rotate (BIN 16 bits) Number of rotations (0 to 15) (BIN 16 bits) Setting Internal device R, ZR...
Page 387 ■RCL • Rotates the 16-bit data of the device designated by (D), including the carry flag, n-bits to the left. The carry flag turns ON or OFF depending on its status prior to the execution of RCL instruction. Carry flag b14 b13 b12 b11 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
Page 388 Program example • The following program rotates the contents of D0, not including the carry flag, 3 bits to the left when XC is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Carry flag (SM700) b14 b13 b12 b11b10 b9 b6 b5 b4 b3 b2 b1 Carry flag (SM700)
Page 389: Right Rotation Of 32-Bit Data
Right rotation of 32-bit data DROR(P), DRCR(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of DROR/DRCR. Command DROR, DRCR Command DRORP, DRCRP (D): Head number of the devices to rotate (BIN 32 bits) Number of rotations (0 to 31) (BIN 16 bits) Setting Internal device R, ZR...
Page 390 Operation error • There is no operation error in the DROR(P) or DRCR(P) instruction. Program example • The following program rotates the contents of D0 and D1, not including the carry flag, 4 bits to the right when XC is ON. [Ladder Mode] [List Mode] Step...
Page 391: Left Rotation Of 32-Bit Data
Left rotation of 32-bit data DROL(P), DRCL(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of DROL/DRCL. Command DROL, DRCL Command DROLP, DRCLP (D): Head number of the devices to rotate (BIN 32 bits) Number of rotations (0 to 31) (BIN 16 bits) Setting Internal device R, ZR...
Page 392 Operation error • There is no operation error in the DROL(P) or DRCL(P) instruction. Program example • The following program rotates the contents of D0 and D1, not including the carry flag, 4 bits to the left when XC is ON. [Ladder Mode] [List Mode] Step...
Page 393: Shift Instructions
Shift Instructions n-bit shift to right of 16-bit data, n-bit shift to left of 16-bit data SFR(P), SFL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of SFR/SFL. Command SFR, SFL Command SFRP, SFLP (D): Head number of the devices where shift data is stored (BIN 16 bits) Number of shifts (0 to 15) (BIN 16 bits) Setting Internal device...
Page 394 ■SFL • Shifts 16-bit data at device designated by (D) n bits to the left. Bits starting from the lowest bit to n bit are filled with 0s. b14 b13 b12 b11b10 b9 b6 b5 b4 b3 b2 b1 When n=8: Carry flag (SM700) b14 b13 b12 b11b10 b9...
Page 395 Program example • The following program shifts the data of D0 to the right by the number of bits designated by D100 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 D100 Carry flag (SM700)
Page 396: 1-Bit Shift To Right Of N-Bit Data, 1-Bit Shift To Left Of N-Bit Data
1-bit shift to right of n-bit data, 1-bit shift to left of n-bit data BSFR(P), BSFL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BSFR/BSFL. Command BSFR, BSFL Command BSFRP, BSFLP (D): Head number of the devices to be shifted (bits) Number of devices to which shift is executed (BIN 16 bits) Setting Internal device...
Page 397 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 398: N-Bit Shift To Right Of N-Bit Data, N-Bit Shift To Left Of N-Bit Data
n-bit shift to right of n-bit data, n-bit shift to left of n-bit data SFTBR(P), SFTBL(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of SFTBR/SFTBL.
Page 399 ■SFTBL(P) • This instruction shifts the n1 bits data in the devices starting from the device specified by (D) to the left by n2 bits. n1=10, n2=4 Carry flag (SM700) Filled with 0s • n1 and n2 are specified under the condition that n1 is larger than n2. If the value of n2 is equal to or larger than the value of n1, the remainder of n2 / n1 (n2 divided by n1) is used for a shift.
Page 400 Program example • The following program shifts the data of Y10 to Y17 (8 bits) specified by (D) to the right by 2 bits (n2), when M0 is turned on. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Carry flag (SM700) •...
Page 401: 1-Word Shift To Right Of N-Word Data, 1-Word Shift To Left Of N-Word Data
1-word shift to right of n-word data, 1-word shift to left of n-word data DSFR(P), DSFL(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DSFR/DSFL. Command DSFR, DSFL Command DSFRP, DSFLP (D): Head number of the devices to be shifted (BIN 16 bits) Number of devices to which shift is executed (BIN 16 bits) Setting Internal device...
Page 402 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 403: N-Word Shift To Right Of N-Word Data, N-Word Shift To Left Of N-Word Data
n-word shift to right of n-word data, n-word shift to left of n-word data SFTWR(P), SFTWL(P) Ver. High Basic Process Redundant LCPU Universal performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of SFTWR/SFTWL.
Page 404 ■SFTWL(P) • This instruction shifts the n1 words data in the devices starting from the device specified by (D) to the left by n2 words. n1=9, n2=4 Filled with 0 • The n2 words in the devices starting from the lowest device are filled with 0s. •...
Page 405 Program example • The following program shifts the 8 words (n1) data stored in the devices starting from D10 specified by (D) to the right by 2 words (n2), when M0 is turned on. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Filled with 0...
Page 406: Bit Shift Right
Bit shift right SFTR(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command SFTR SFTR Command SFTRP SFTRP (S): Start number (bit) of the bit devices to be stored in empty data after shifting to the right (D): Start number of bit device to shift to the right (bit) Bit data length of shift data (n2 ...
Page 407 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 408: Bit Shift Left
Bit shift left SFTL(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command SFTL SFTL Command SFTLP SFTLP (S): Start number (bit) of the bit devices to be stored in empty data after shifting to the left (D): Start number of bit device to shift to the left (bit) Bit data length of shift data (n2 ...
Page 409 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 410: Word Shift Right
Word shift right WSFR(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command WSFR WSFR Command WSFRP WSFRP (S): Start number of the word devices to be stored in empty data after shifting to the right (BIN 16 bits) (D): Start number of word device to shift to the right (BIN 16 bits) Word data length of shift data (n2 ...
Page 411 • An example of operation where digit specification is used for shift data (D) and the data (S) to be stored in the shift data is shown below. WSFR K1X0 K1Y0 Set the same digit when shifting the digit-specified bit devices. YD YC (1) Overflow (deletion data) (2) n2 words shift to the right (n2=2)
Page 412: Word Shift Left
Word shift left WSFL(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command WSFL WSFL Command WSFLP WSFLP (S): Start number of the word devices to be stored in empty data after shifting to the left (BIN 16 bits) (D): Start number of word device to shift to the left (BIN 16 bits) Word data length of shift data (n2 ...
Page 413 • An example of operation where digit specification is used for shift data (D) and the data (S) to be stored in the shift data is shown below. WSFL K1X0 K1Y0 Set the same digit when shifting the digit-specified bit devices. YD YC (1) Overflow (deletion data) (2) n2 words shift to the left (n2=2)
Page 414: Bit Processing Instructions
Bit Processing Instructions Bit set for word devices, bit reset for word devices BSET(P), BRST(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of BSET/BRST. Command BSET, BRST Command BSETP, BRSTP (D): Device whose bits are set/reset (BIN 16 bits) Position of the bit to be set/reset (0 to 15) (BIN 16 bits) Setting Internal device...
Page 415 Operation error • There is no operation error in the BSET(P) or BRST(P) instruction. Program example • The following program resets the 8th bit of D8 (b8) to 0 when XB is OFF, and sets the 3rd bit of D8 (b3) to 1 when XB is ON. [Ladder Mode] Resets b8 of D8.
Page 416: Bit Tests
Bit tests TEST(P), DTEST(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of TEST/DTEST. Command TEST, DTEST Command TESTP, DTESTP (S1): Number of the device where bit data to be extracted is stored (BIN 16/32 bits) (S2): Location of the bit data to be extracted (0 to 15 (TEST)/0 to 31 (DTEST)) (BIN 16 bits) (D): Number of the bit device where the extracted data will be stored (bits) Setting Internal device...
Page 417 Operation error • There is no operation error in the TEST(P) or DTEST(P) instruction. Program example • The following program turns M0 ON or OFF based on the status of the 10th bit in the 1-word data block (D0). [Ladder Mode] [List Mode] Step Instruction...
Page 418: Batch Reset Of Bit Devices
Batch reset of bit devices BKRST(P) High Basic Process Redundant Universal LCPU performance Command BKRST BKRST Command BKRSTP BKRSTP (D): Head number of the devices to be reset (bits) Number of the devices to be reset (BIN 16 bits) Setting Internal device R, ZR J\...
Page 419 Program example • The following program turns OFF devices from M0 to M7 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 Not changed •...
Page 420: Data Processing Instructions
Data Processing Instructions 16-bit data search, 32-bit data search SER(P), DSER(P) High Basic Process LCPU Redundant Universal performance Command SER, DSER Command SERP, DSERP (S1): Search data or head number of the devices where the search data is stored (BIN 16/32 bits) (S2): Data to be searched or head number of the devices where the data to be searched is stored (BIN 16 bits) (D): Head number of the devices where the search result will be stored (BIN 16 bits) Number of searches (BIN 16 bits)
Page 421 ■DSER • Searches n points from the device designated by (S2) in 32-bit units (2  n points in 16-bit units) regarding 32-bit data of the device designated by (S1) +1 and (S1) as a keyword. Then, the number of matches with the keyword is stored at the device designated by (D)+1, and the first matched device number (in the relative number from (S2)) is stored at the device designated by (D).
Page 422 Program example • The following program searches D100 to D105 for the contents of D0 when X20 is ON, and stores the search results at W0 and W1. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Search data Data to be searched D100 Search results D101...
Page 423: 16-Bit Data Bit Check, 32-Bit Data Check
16-bit data bit check, 32-bit data check SUM(P), DSUM(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of SUM/DSUM. Command SUM, DSUM Command SUMP, DSUMP (S): Head number of the devices where the total number of bits of "1" is counted (BIN 16/32 bits) (D): Head number of the devices where the total number of the bits will be stored (BIN 16/32 bits) Setting Internal device...
Page 424 Program example • The following program stores the number of bits which are ON from X8 to X17 into D0 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] 0 0 1 0 1 0 1 1 0 0 0 0 0 1 1 1 Stores the total number of bits where 1 is set at D0.
Page 425: Decoding From 8 To 256 Bits
Decoding from 8 to 256 bits DECO(P) High Basic Process LCPU Redundant Universal performance Command DECO DECO Command DECOP DECOP (S): Data to be decoded or the number of the device where the data to be decoded is stored (BIN 16 bits) (D): Head number of the devices where the decoding result will be stored (Device name) Valid bit length (1 to 8), 0: No processing (BIN 16 bits) Setting...
Page 426 Program example • The following program decodes the 3 bits from X0 and stores the results at M10 when X20 is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] When 6 is designated at X0 to X2 Decoding result If 3 bits are designated as significant bits, 8 points are occupied.
Page 427: Encoding From 256 To 8 Bits
Encoding from 256 to 8 bits ENCO(P) High Basic Process LCPU Redundant Universal performance Command ENCO ENCO Command ENCOP ENCOP (S): Head number of the device where the data to be encoded is stored (Device name) (D): Number of the device where the encoding result will be stored (BIN 16 bits) Valid bit length (1 to 8), 0: No processing (BIN 16 bits) Setting Internal device...
Page 428 Program example • The following program encodes the 3 bits from M10 when X20 is ON, and stores the results at D8. [Ladder Mode] [List Mode] Step Instruction Device [Operation] If 3 bits are designated as significant bits, 8 points are occupied. Storage device D8 Encoding result The location of the ON bit, counted from M10, is stored in BIN.
Page 429: 7-Segment Decode
7-segment decode SEG(P) High Basic Process LCPU Redundant Universal performance Command Command SEGP SEGP (S): Data to be decoded or head number of the devices where the data to be decoded is stored (BIN 16 bits) (D): Head number of the devices where the decoding result will be stored (BIN 16 bits) Setting Internal device R, ZR...
Page 430 • If (D) is a bit device, indicates the head number of the devices storing the 7-segment display data; if it is a word device, indicates the number of the device storing the data. Before execution After execution Bit device SEG K7 K2Y48 0 0 1 0 0 1 1 1 8 points...
Page 431: 4-Bit Dissociation Of 16-Bit Data
4-bit dissociation of 16-bit data DIS(P) High Basic Process LCPU Redundant Universal performance Command Command DISP DISP (S): Head number of the devices where data to be dissociated is stored (BIN 16 bits) (D): Head number of the devices where the dissociated data will be stored (BIN 16 bits) Number of dissociations (1 to 4), 0: No processing (BIN 16 bits) Setting Internal device...
Page 432 Program example • The following program dissociates the 16-bit data from D0 into 4-bit groups, and stores from D10 to D13 when X0 is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b12 b11 b4 b3 1 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1...
Page 433: 4-Bit Linking Of 16-Bit Data
4-bit linking of 16-bit data UNI(P) High Basic Process LCPU Redundant Universal performance Command Command UNIP UNIP (S): Head number of the devices where data to be linked is stored (BIN 16 bits) (D): Head number of the devices where the linked data will be stored (BIN 16 bits) Number of links (1 to 4), 0: No processing (BIN 16 bits) Setting Internal device...
Page 434 Program example • The following program links the lower 4 bits of D0 to D2 when X0 is ON, and stores them at D10. [Ladder Mode] [List Mode] Instruction Step Device [Operation] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1...
Page 435: Dissociation Of Random Data, Linking Of Random Data
Dissociation of random data, linking of random data NDIS(P), NUNI(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of NDIS/NUNI. Command NDIS, NUNI Command NDISP, NUNIP (S1): Head number of the devices where data to be dissociated/linked is stored (BIN 16 bits) (D): Head number of the devices where the dissociated/linked data will be stored (BIN 16 bits) (S2): Head number of the devices where the units of dissociation/linking will be stored (BIN 16 bits) Setting...
Page 436 • The number of dissociated bits designated at (S2) can be designated within a range of 1 to 16 bits. • Bits from the device number designated at (S2) to the device number where "0" is stored are processed as dissociated bits. •...
Page 437 Program example • The following program dissociates data of 4, 3, and 6 bits respectively from the lower bits of D0, and stores them from D10 to D12. [Ladder Mode] [List Mode] Device Step Instruction [Operation] b4b3 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 4 bits 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Filled with 0s.
Page 438 • The following program links the lower 4 bits of data from D10, the lower 3 bits of data from D11, and the lower 6 bits of data from D12, and stores at D0. [Ladder Mode] [List Mode] Step Instruction Device [Operation] 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0...
Page 439: Data Dissociation In Byte Units, Data Linking In Byte Units
Data dissociation in byte units, data linking in byte units WTOB(P), BTOW(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of WTOB/BTOW. Command WTOB, BTOW Command WTOBP, BTOWP (S): Head number of the devices where data to be dissociated/linked in byte units is stored (BIN 16 bits) (D): Head number of the devices where the result of dissociated/linking in byte units will be stored (BIN 16 bits) Number of byte data to be dissociated/linked (BIN 16 bits) Setting...
Page 440 • The "00H" code will automatically be stored at the upper 8 bits of the byte storage device designated by (D). Stores 00 • Even though the range of devices with the data to be dissociated ((S) to (S)+(n  2 - 1)) is the same as the range of devices for storing dissociated data ((D) to (D)+(n-1)), the instruction operates correctly.
Page 441 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 442: Maximum Value Search For 16-Bit Data, Maximum Value Search For 32-Bit Data
Maximum value search for 16-bit data, maximum value search for 32-bit data MAX(P), DMAX(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of MAX/DMAX. Command MAX, DMAX Command MAXP ,DMAXP (S): Start device where the data to be searched is stored (BIN 16/32 bits) (D): Start device where the maximum value search result will be stored (BIN 16/32 bits) Number of data blocks to be searched (BIN 16 bits) Setting...
Page 443 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 444: Minimum Value Search For 16-Bit Data, Minimum Value Search For 32-Bit Data
Minimum value search for 16-bit data, minimum value search for 32-bit data MIN(P), DMIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of MIN/DMIN. Command MIN, DMIN Command MINP, DMINP (S): Start device where the data to be searched is stored (BIN 16/32 bits) (D): Start device where the minimum value search result will be stored (BIN 16/32 bits) Number of data blocks to be searched (BIN 16 bits) Setting...
Page 445 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 446: Bin 16-Bit Data Sort Operations, Bin 32-Bit Data Sort Operations
BIN 16-bit data sort operations, BIN 32-bit data sort operations SORT, DSORT High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of SORT/DSORT. Command SORT, DSORT (S1): Head device number in the table to be sorted (BIN 16/32 bits) Number of data blocks to be sorted (BIN 16 bits) (S2): Number of data blocks to be compared in one sort operation (BIN 16 bits) (D1): Number of the bit device to be turned ON at the completion of the sort operation (bits)
Page 447 • The maximum number of executions until completion of the sort should be calculated according to the following equation: The maximum number of executions until completion = (n)  (n - 1) / 2 [times executed] When n=10, the number of executions is obtained as 10  (10 - 1) / 2=45 [times executed]. If (S2)=2, then the number of scans until the completion of sort is calculated as 45/2=22.5 ...
Page 448 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 449 • The following program sorts the BIN 32-bit data from D0 to D9 in ascending/descending order when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Data after sort D1, D0 -99999 D3, D2 -1111 Data before sort D5, D4 D1, D0 456789...
Page 450: Calculation Of Totals For 16-Bit Data
Calculation of totals for 16-bit data WSUM(P) High Basic Process Redundant Universal LCPU performance Command WSUM WSUM Command WSUMP WSUMP (S): Head number of the devices where data to be summed are stored (BIN 16 bits) (D): Head number of the devices where the sum will be stored (BIN 32 bits) Number of data blocks (BIN 16 bits) Setting Internal device...
Page 451: Calculation Of Totals For 32-Bit Data
Calculation of totals for 32-bit data DWSUM(P) High Basic Process LCPU Redundant Universal performance Command DWSUM DWSUM Command DWSUMP DWSUMP (S): Head number of the devices where data to be summed are stored (BIN 32 bits) (D): Head number of the devices where the sum will be stored (BIN 64 bits) Number of data blocks (BIN 16 bits) Setting Internal device...
Page 452: Calculation Of Averages For 16-Bit Data, Calculation Of Averages For 32-Bit Data
Calculation of averages for 16-bit data, calculation of averages for 32-bit data MEAN(P), DMEAN(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of MEAN/DMEAN.
Page 453 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 454: Check Code
Check code CCD(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command Command CCDP CCDP (S): Start number of target word device (BIN 16 bits) (D): Start number of word device in which calculated data is to be stored (BIN 16 bits) Number of data blocks (setting range: 1 to 256) (BIN 16 bits) Setting Internal device...
Page 455 • Calculation of horizontal parity value In 16-bit conversion mode, the shaded part in the following figure becomes the calculation target of the horizontal parity. The number of ON (1) bits is calculated to determine the parity value which becomes ON (1) when the number of ON (1) bits is finally odd or OFF (0) when it is finally even, and the horizontal parity value is stored in the device specified by (S)+1.
Page 456 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 457: Crc Operation
CRC operation CRC(P) Ver. Ver. High Basic Process Redundant LCPU Universal performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command Command CRCP CRCP (S): Start number of the devices where the target data of CRC value generation is stored (BIN 16 bits) (D): Number of the device where the CRC value generated is stored (BIN 16 bits) Number of 8-bit data blocks for which the CRC value is to be determined or the number for the device where the number of 8-bit data blocks is stored (setting range: 1 to 256) (BIN 16 bits)
Page 458 ■8-bit conversion mode (when SM772 is ON) CRC operation is performed for the lower 8 bits (lower byte) of the data in the device specified by (S). The operation result is stored using the two points from the device specified by (D): lower 8 bits (byte units) are stored in the device specified by (D) and upper 8 bits (byte units) are stored in the device specified by (D)+1.
Page 459: Structure Creation Instructions
Structure Creation Instructions FOR to NEXT instruction loop FOR, NEXT High Basic Process Redundant Universal LCPU performance Repeat program NEXT NEXT Number of repetitions of FOR to NEXT loop (1 to 32767) (BIN 16 bits) Setting Internal device R, ZR J\...
Page 460 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 461 • To force an end to the repetitious execution of the FOR to NEXT loop during the execution of the loop, insert a BREAK instruction. See Page 460 Forced end of FOR to NEXT instruction loop for details concerning the use of the BREAK instruction.
Page 462: Forced End Of For To Next Instruction Loop
Forced end of FOR to NEXT instruction loop BREAK(P) High Basic Process Redundant Universal LCPU performance Command BREAK BREAK Command BREAKP BREAKP (D): Number of the device where the remaining number of loops will be stored (BIN 16 bits) Number of the pointer (device name (pointer)) where the program is branched at the forced end of a loop. Setting Internal device R, ZR...
Page 463 Program example • The following program forces the FOR to NEXT loop to end when the value of D0 reaches 30 (when the FOR to NEXT loop has been executed 30 times). (The value 71 is stored at D1 when the BREAK instruction is executed.) [Ladder Mode] [List Mode] Step...
Page 464: Subroutine Program Calls
Subroutine program calls CALL(P) High Basic Process Redundant Universal LCPU performance Command CALL CALL Command CALLP CALLP Command CALL CALL Command CALLP CALLP Head pointer number of a subroutine program (Device name) (S1) to (S5): Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Setting Internal device R, ZR...
Page 465 • When function devices (FX, FY, FD) are used by a subroutine program, specify a device with (S1) to (S5) corresponding to the function device. The contents to the devices specified by (S1) to (S5) are as indicated below. • Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. •...
Page 466 ■Incorrect operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D1 is used in the subroutine program. [Program example] [Operation performed after subroutine program execution] Before the execution Immediately after the execution At the time of subroutine After the execution of subroutine program...
Page 467 [Operation performed after subroutine program execution] Before the execution Immediately after the execution At the time of subroutine After the execution of subroutine program of CALL instruction program execution of RET instruction Transfer Transfer 1000 1000 1000 1000 Indefinite Indefinite Indefinite Indefinite Indefinite...
Page 468 Program example • The following program executes a subroutine program with argument when X20 is turned ON. [Ladder Mode] [List Mode] Instruction Device Step 7 APPLICATION INSTRUCTIONS 7.6 Structure Creation Instructions...
Page 469: Return From Subroutine Programs
Return from subroutine programs High Basic Process LCPU Redundant Universal performance Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Indicates end of subroutine program • When the RET instruction is executed, returns to the step following the CALL (P), FCALL (P), ECALL (P), EFCALL (P) or XCALL instruction which called the subroutine program.
Page 470: Subroutine Program Output Off Calls
Subroutine program output OFF calls FCALL(P) High Basic Process Redundant Universal LCPU performance Command FCALL FCALL Command FCALLP FCALLP Command FCALL FCALL Command FCALLP FCALLP Head pointer number of a subroutine program (Device name) (S1) to (S5): Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Setting Internal device R, ZR...
Page 471 • If the FCALL (P) instruction is used in conjunction with the CALL(P) instruction, non-execution processing of a subroutine program is performed when the execution command is turned OFF, enabling forcible turning OFF of the OUT instruction and the PLS instruction (including P instructions). In case the FCALL (P) instruction is not used in conjunction with the CALL(P) instruction, non-execution processing of a subroutine program is not performed even if the execution command is turned OFF.
Page 472 • When function devices (FX, FY, FD) are used by a subroutine program, specify a device with (S1) to (S5) corresponding to the function device. The contents to the devices specified by (S1) to (S5) are as indicated below. • Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. •...
Page 473 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 474: Subroutine Calls Between Program Files
Subroutine calls between program files ECALL(P) Basic High Process Redundant Universal LCPU performance Command ECALL ECALL File name Command ECALLP ECALLP File name Command ECALL File name ECALL Command ECALLP File name ECALLP File name: Name of the program file to be called (character string) Head pointer number of a subroutine program (Device name) (S1) to (S5): Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Setting...
Page 475 • Only the file name of a program file stored in the drive 0 (program memory/internal RAM) can be designated for a file name. • It is not necessary to designate the extension (.QPG) with the file name. (Only .QPG files will be acted on.) •...
Page 476 ■Incorrect operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D1 is used in the subroutine program. [Program example] [Operation performed after subroutine program execution] At the time of Immediately after the Before the execution subroutine program...
Page 477 ■Correct operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D4 is used in the subroutine program. [Program example] [MAIN] [ABC] [Operation performed after subroutine program execution] Immediately after the At the time of Before the execution execution of ECALL...
Page 478 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 479: Subroutine Output Off Calls Between Program Files
Subroutine output OFF calls between program files EFCALL(P) Basic High Process Redundant Universal LCPU performance Command EFCALL EFCALL File name Command EFCALLP File name EFCALLP Command EFCALL File name EFCALL Command File name EFCALLP EFCALLP File name: Name of the program file to be called (character string) Head pointer number of a subroutine program (Device name) (S1) to (S5): Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Setting...
Page 480 • The EFCALL (P) instruction is used in combination with the ECALL (P) instruction. • If the EFCALL(P) instruction is used in conjunction with the ECALL(P) instruction, non-execution processing of a subroutine program is performed when the execution command is turned OFF, enabling forcible turning OFF of the OUT instruction and the PLS instruction (including P instructions).
Page 481 • When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function device with (S1) to (S5). [MAIN] [ABC] • Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. •...
Page 482 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 483: Subroutine Program Calls
Subroutine program calls XCALL Ver. High Basic Process Redundant Universal LCPU performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command XCALL XCALL Head pointer number of a subroutine program (Device name) (S1) to (S5): Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits) Setting Internal device R, ZR...
Page 484 • Operation of XCALL instruction varies according to the CPU module type. The following program example shows the operation of XCALL instruction for each CPU module. [Program example] Subroutine program (P1) call by XCALL instruction P1 subroutine program [ON/OFF timing of X0] Ò...
Page 485 • When function devices (FX, FY, FD) are used by a subroutine program, specify a device with (S1) to (S5) corresponding to the function device. The contents to the devices specified by (S1) to (S5) are as indicated below. • Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. •...
Page 486 • The device used for the argument of the XCALL instruction must not be used in a subroutine program. If used, it will not be possible to perform correct calculations. (Page 484 Incorrect operation example) ■Incorrect operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D1 is used in the subroutine program.
Page 487 ■Correct operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D4 is used in the subroutine program. [Program example] [Operation performed after subroutine program execution] Before the execution Immediately after the execution At the time of subroutine After the execution of subroutine program...
Page 488 Program example • The following program executes a subroutine program with argument when X20 is turned ON. [Ladder Mode] [List Mode] Device Step Instruction 7 APPLICATION INSTRUCTIONS 7.6 Structure Creation Instructions...
Page 489: Refresh
Refresh High Redundant Universal LCPU Basic Process performance Refer to Page 489 Select refresh (COM) for the COM instruction of the following CPU modules. • Basic model QCPU of serial No. 04122 or later • High Performance model QCPU of serial No. 04012 or later •...
Page 490 • Data communications using the COM instruction (1) Example of data communications when COM instruction is not used Host station program Data communications Program at other station I/O refresh at remote I/O station (2) Example of data communications when COM instruction has been used Host station program Data communications COM COM...
Page 491: Select Refresh (Com)
Select refresh (COM) Ver. Ver. Ver. High Basic Process Redundant Universal LCPU performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. • High Performance model QCPU: The serial number (first five digits) is "04012" or later. •...
Page 492 The following processing is also performed during service processing. • Monitor processing of other station • Read of another intelligent function module buffer memory by the serial communication module • All the processing items except I/O refresh are performed when SM775 is turned OFF. •...
Page 493 Refresh between the multiple CPUs by the COM instruction is performed under the following condition. • Receiving operation from other CPUs: When b4 of SD778 (auto refresh in the CPU shared memory) is 1. • Sending operation from host CPU: When b15 of SD778 (execution status of service processing) is 0. [LCPU] Bit of SD778 Executed...
Page 494: Select Refresh (Ccom(P))
Select refresh (CCOM(P)) CCOM(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Command CCOM CCOM Command CCOMP CCOMP Setting Internal device R, ZR J\...
Page 495: Index Modification Of Entire Ladder
Index modification of entire ladder IX, IXEND High LCPU Universal Basic Process Redundant performance Ladder where index modification is performed IXEND I X END (S): Head number of the devices where index modification data is stored (BIN 16 bits) Setting Internal device R, ZR J\...
Page 496 • Index modification for device numbers is accomplished in the manner as below: By setting a modification value to each of the devices, the set modification values are added to all the device numbers of the devices used in the ladder between the IX and IXEND instructions.
Page 497 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 498: Designation Of Modification Values In Index Modification Of Entire Ladders
Designation of modification values in index modification of entire ladders IXDEV, IXSET High LCPU Universal Basic Process Redundant performance IXDEV IXDEV IXSET IXSET Dummy contact Offset designation sections (S): Head number of the devices where index modification data is stored (pointer only) P (Pointer) (D): Head number of the devices where index modification data will be stored (except a pointer) (BIN 16 bits) Setting Internal device...
Page 499 • If two offsets for two identical types of device have been set in the offset designation area, the last value set will be valid. • The IXDEV and IXSET instructions should be treated as a pair. • Any value from 0 to 32767 is valid for ZR. (The offset value will be the remainder of the quotient of the designated device number divided by 32768.) •...
Page 500: Data Table Operation Instructions
Data Table Operation Instructions Writing data to the data table FIFW(P) High Basic Process LCPU Redundant Universal performance Command FIFW FIFW Command FIFWP FIFWP (S): Data to be written into the table or the number of the device where the data is stored (BIN 16 bits) (D): Head number of the table (BIN 16 bits) Setting Internal device...
Page 501 Program example • The following program stores the data at D0 to the data table following R0 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Table Table Number of stored data blocks 4321 4321 Data table range •...
Page 502: Reading Oldest Data From Tables
Reading oldest data from tables FIFR(P) High Basic Process Redundant Universal LCPU performance Command FIFR FIFR Command FIFRP FIFRP (S): Head number of the devices where the data read from the table will be stored (BIN 16 bits) (D): Head number of the table (BIN 16 bits) Setting Internal device R, ZR...
Page 503 Program example • The following program stores the R1 data from the table R0 to R7 at D0 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Data table Data table Number of stored data blocks Number of stored data blocks 4321 4321...
Page 504: Reading Newest Data From Data Tables
Reading newest data from data tables FPOP(P) High Basic Process Redundant Universal LCPU performance Command FPOP FPOP Command FPOPP FPOPP (S): Head number of the devices where the data read from the table will be stored (BIN 16 bits) (D): Head number of the table (BIN 16 bits) Setting Internal device R, ZR...
Page 505 Program example • The following program stores the data stored last in the data table R0 to R7 at D0 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Data table Data table -123 -123 1400 1400 1234 1234...
Page 506: Deletion Of Data From Data Tables, Insertion Of Data In Data Tables
Deletion of data from data tables, insertion of data in data tables FDEL(P), FINS(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of FDEL/FINS. Command FDEL, FINS Command FDELP, FINSP (S): Head number of the devices where data to be inserted is stored (BIN 16 bits), head number of the devices where the data to be deleted will be stored (BIN 16 bits) (D): Head number of the table (BIN 16 bits) Location on the table where data is inserted/deleted (BIN 16 bits)
Page 507 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 508: Buffer Memory Access Instructions
Buffer Memory Access Instructions Reading 1-word data from the intelligent function module, reading 2-word data from the intelligent function module FROM(P), DFRO(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of FROM/DFRO. Command FROM, DFRO Command FROMP, DFROP Head I/O number of an intelligent function module (BIN 16 bits) Head address of the buffer memory where data to be read is stored (BIN 16 bits)
Page 509 Data read from intelligent function modules is also possible with the use of an intelligent function module device. For intelligent function module device, refer to the User's Manual (Function Explanation, Program Fundamentals) for the CPU module used. Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/...
Page 510 • The value of n1 is specified by the upper 3 digits of hexadecimal 4 digits which represent the head I/O number of an intelligent function module. [QCPU] Power QY41 supply QX10 QX10 QX10 QX10 QY10 QY10 module 0000 0010 0020 0030 0040...
Page 511: Writing 1-Word Data To The Intelligent Function Module, Writing 2-Word Data To The Intelligent Function Module
Writing 1-word data to the intelligent function module, writing 2- word data to the intelligent function module TO(P), DTO(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of TO/DTO. Command TO, DTO Command TOP, DTOP Head I/O number of an intelligent function module (BIN 16 bits) Head address of the area where data is written (BIN 16 bits) (S): Data to be written or head number of the devices where the data to be written is stored (BIN 16/32 bits)
Page 512 ■DTO • Writes the data stored in n3  2 points starting from the device designated by (S) into the area starting from buffer memory address designated by n2 of the intelligent function module designated by n1. Intelligent function module CPU module buffer memory Device designated...
Page 513 Program example • The following program sets "A/D conversion disabled" to the CH1 and CH2 of the Q68ADV at I/O numbers 040 to 04F when X0 is turned on (writes "3" to the buffer memory address 0). [Ladder Mode] [List Mode] Step Instruction Device...
Page 514: Display Instructions
Display Instructions Print ASCII code Basic High Redundant Universal LCPU Process performance Command (S): ASCII code or head number of the devices where the ASCII code is stored (character string) (D): Head number of the output module to which the ASCII code will be output (bits) Setting Internal device R, ZR...
Page 515 • When SM701 is off, everything from the device specified by (S) to the NULL code "00H" will be the target of the operation. Device where ASCII code is stored Upper 8 bits Lower 8 bits Output Y b8 b7 Head of output ASCII code output Scheduled...
Page 516 Program example • The following program converts the string "ABCDEFGHIJKLMNOP" to ASCII code when X0 is turned ON and stores it from D0 to D7, and then outputs the ASCII code at D0 to D7 to Y14 to Y1D when X3 is turned ON (when SM701 is OFF). [Ladder Mode] When X0 turns ON, converts "ABCDEFGHIJKLMOP"...
Page 517: Print Comment
Print comment Basic High LCPU Redundant Universal Process performance Command (S): Head number of the device which prints the comment (Device name) (D): Head number of the output module which outputs the comment (bits) Setting Internal device R, ZR J\ U\G...
Page 518 [Timing Chart] Y30 to Y37 Preprocessing (several scans) 30ms (Strobe signal) (Flag indicating strobe signal is being output) 30ms × 16 = 480ms SM721 (File access in progress flag) PRC instruction cannot be executed again. SM720 (File access completion flag) None of Instructions other than PRC instruction (SP.FREAD, SP.FWRITE, instructions can...
Page 519 • For device comments used with the PRC instruction, use comment files stored in the standard ROM or memory card. Comment files stored in the program memory cannot be used. • The comment file used by the PRC instruction is set at the "PLC File Setting" option in the PLC parameter dialog box.
Page 520: Error Display And Annunciator Reset
Error display and annunciator reset LEDR Basic High Process Redundant Universal LCPU performance Command LEDR LEDR Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Resets the self-diagnosis error display so that annunciator display or operation can be continued. With one execution of this instruction, either error display or annunciator is reset.
Page 521 • The defaults for the error item numbers set in special registers SD207 to SD209 and order of priority are given in the table below: Priority Factor number Description Remark (Hexadecimal) AC DOWN Power supply cut SINGLE PS.DOWN Redundant base unit power supply voltage drop (QCPU only) SINGLE PS.ERROR Redundant power supply module fault (QCPU only) UNIT VERIFY ERR.
Page 522: Debugging And Failure Diagnosis Instructions
7.10 Debugging and Failure Diagnosis Instructions Special format failure check CHKST, CHK Basic High Universal LCPU Process Redundant performance Command CHKST CHKST Check condition (Only a contact is valid; b contact is ignored) Only input (X) can be used Up to 150 contacts can be connected Setting Internal device R, ZR...
Page 523 ■CHK • The CHK instruction is the instruction used for the bidirectional operation to confirm the nature of the system failure. When the CHK instruction is executed, a failure diagnosis check is conducted with the designated check conditions, and if a failure is detected, SM80 is turned ON, and the failure number is stored at SD80 as a BCD value.
Page 524 • Depending on the designated contact, the CHK instruction undergoes processing identical to that shown for the ladder below: CHKST (Detection by both advance and retraction end sensors during advance operation of the conveyor) Max. 150 contacts X +1 Y SM80 Coil No.
Page 525 • Place LD and AND instructions prior to the CHK instruction to establish a check condition. Check conditions cannot be set using other contact instructions. If a check condition has been set with LDI or ANI, the processing for the check condition they specify will not be conducted.
Page 526: Changing Check Format Of Chk
Changing check format of CHK CHKCIR, CHKEND Basic High LCPU Universal Process Redundant performance Command CHKST CHKST SM400 CHKCIR CHKCIR Ladder pattern to be checked Max. 9 coils SM400 CHKEND CHKEND (1) Page 520 Special format failure check Setting Internal device R, ZR J\...
Page 527 • The device numbers indicated at check conditions (X2 and X8 in the figure below) will assume index modification values for the individual device numbers (with the exception of annunciators (F)) described in the ladder patterns. X10 within the dotted lines in the figure below would be as follows: When the check condition corresponds to X2, the processing is performed by X12.
Page 528 • Failure checks check the ON/OFF status of OUT F by using the ladder pattern in the various check conditions. In all check conditions, SM80 will be turned ON if even one of the OUT F is ON in a ladder pattern. Further, the error numbers (contact numbers and coil numbers) corresponding to the OUT F...
Page 529 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored in SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 530: Character String Processing Instructions
7.11 Character String Processing Instructions Conversion from BIN 16-bit data to decimal ASCII, conversion from BIN 32-bit data to decimal ASCII BINDA(P), DBINDA(P) Basic High Process LCPU Redundant Universal performance indicates an instruction symbol of BINDA/DBINDA. Command BINDA, DBINDA Command BINDAP, DBINDAP (S): BIN data to be converted to ASCII (BIN 16/32 bits) (D): Head number of the devices where the conversion result will be stored (character string)
Page 531 ■DBINDA • Converts the individual digit numbers of decimal notation of the BIN 32-bit data designated by (S) into ASCII codes, and stores the results into the area starting from the device designated by (D). b8b7 ASCII code for billions place Sign ASCII code for ten-millions place ASCII code for hundred-mi l l i o ns pl a ce...
Page 532 Program example • The following example program uses the PR instruction to output the 16-bit BIN data W0 value by decimal to Y40 to Y48 as ASCII. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON. Because SM701 is OFF, the PR instruction will output ASCII code until 00H is encountered.
Page 533: Conversion From Bin 16-Bit Data To Hexadecimal Ascii, Conversion From Bin 32-Bit Data To Hexadecimal Ascii
Conversion from BIN 16-bit data to hexadecimal ASCII, conversion from BIN 32-bit data to hexadecimal ASCII BINHA(P), DBINHA(P) Basic High Process LCPU Redundant Universal performance indicates an instruction symbol of BINHA/DBINHA. Command BINHA, DBINHA Command BINHAP, DBINHAP (S): BIN data to be converted to ASCII (BIN 16/32 bits) (D): Head number of the devices where the conversion result will be stored (character string) Setting Internal device...
Page 534 ■DBINHA • Converts the individual digit numbers of hexadecimal notation of the BIN 32-bit data designated by (S) into ASCII codes, and stores the results into the area starting from the device designated by (D). b8b7 ASCII code for the 7th digit ASCII code for the 8th digit ASCII code for the 5th digit ASCII code for the 6th digit...
Page 535 Program example • The following program uses the PR instruction to output the hexadecimal value of the 16-bit BIN data at W0 in ASCII code to Y40 to Y48. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON. Because SM701 is OFF, the PR instruction will output ASCII code until 00H is encountered.
Page 536: Conversion From Bcd 4-Digit Data To Decimal Ascii Data, Conversion From Bcd 8-Digit Data To Decimal Ascii Data
Conversion from BCD 4-digit data to decimal ASCII data, conversion from BCD 8-digit data to decimal ASCII data BCDDA(P), DBCDDA(P) Basic High Process Redundant Universal LCPU performance indicates an instruction symbol of BCDDA/DBCDDA. Command BCDDA, DBCDDA Command BCDDAP, DBCDDAP (S): BCD data to be converted to ASCII (BCD 4 digits/8 digits) (D): Head number of the devices where the conversion result will be stored (character string) Setting Internal device...
Page 537 ■DBCDDA • Converts the individual digit numbers of hexadecimal notation of the BCD 8-digit data designated by (S) into ASCII codes, and stores the results into the area starting from the device designated by (D). b8b7 ASCII code for millions place ASCII code for ten-millions place ASCII code for hundred-thousands place ASCII code for ten-thousands place...
Page 538 Program example • The following program uses the PR instruction to convert BCD 4-digit data (the value at W0) to decimal, and outputs it in ASCII format to Y40 to Y48. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON. Because SM701 is OFF, the PR instruction will output ASCII code until 00H is encountered.
Page 539: Conversion From Decimal Ascii To Bin 16-Bit Data, Conversion From Decimal Ascii To Bin 32-Bit Data
Conversion from decimal ASCII to BIN 16-bit data, conversion from decimal ASCII to BIN 32-bit data DABIN(P), DDABIN(P) Basic High Process LCPU Redundant Universal performance indicates an instruction symbol of DABIN/DDABIN. Command DABIN, DDABIN Command DABINP, DDABINP (S): ASCII data to be converted to BIN value or head number of the devices where the ASCII data is stored (character string) (D): Head number of the devices where the conversion result will be stored (BIN 16/32 bits) Setting Internal device...
Page 540 ■DDABIN • Converts decimal ASCII data stored into the area starting from the device number designated by (S) into BIN 32-bit data, and stores it in the device number designated by (D). b8b7 Sign data ASCII code for billions place ASCII code for ten-millions place ASCII code for hundred-millions place b16b15...
Page 541 Program example • The following program converts the decimal, 5-digit ASCII data and sign set at D20 through D22 to BIN values, and stores the result at D0. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8b7 (space) (space) (Regarded as -00276) BIN value •...
Page 542: Conversion From Hexadecimal Ascii To Bin 16-Bit Data, Conversion From Hexadecimal Ascii To Bin 32-Bit Data
Conversion from hexadecimal ASCII to BIN 16-bit data, conversion from hexadecimal ASCII to BIN 32-bit data HABIN(P), DHABIN(P) Basic High Process Redundant Universal LCPU performance indicates an instruction symbol of HABIN/DHABIN. Command HABIN, DHABIN Command HABINP, DHABINP (S): ASCII data to be converted to BIN value or head number of the devices where the ASCII data is stored (character string) (D): Head number of the devices where the conversion result will be stored (BIN 16/32 bits) Setting Internal device...
Page 543 ■DHABIN • Converts hexadecimal ASCII data stored in the area starting from the device number designated by (S) into BIN 32-bit data, and stores it in the device number designated by (D). b8b7 ASCII code for the 7th digit ASCII code for the 8th digit b16 b15 ASCII code for the 5th digit ASCII code for the 6th digit...
Page 544 Program example • The following program converts the hexadecimal, 4-digit ASCII data set at D20 and D21 to BIN data, and stores the result at D0. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8b7 22977 Regarded as A63F BIN value A63F (-22977 in decimal value)
Page 545: Conversion From Decimal Ascii To Bcd 4-Digit Data, Conversion From Decimal Ascii To Bcd 8-Digit Data
Conversion from decimal ASCII to BCD 4-digit data, conversion from decimal ASCII to BCD 8-digit data DABCD(P), DDABCD(P) Basic High Process LCPU Redundant Universal performance indicates an instruction symbol of DABCD/DDABCD. Command DABCD, DDABCD Command DABCDP, DDABCDP (S): ASCII data to be converted to BCD value or head number of the devices where the ASCII data is stored (character string) (D): Head number of the devices where the conversion result will be stored (BCD 4 digits/8 digits) Setting Internal device...
Page 546 ■DDABCD • Converts decimal ASCII data stored in the area starting from the device designated by (S) to 8-digit BCD data, and stores it into the area starting from the device designated by (D). ASCII code for millions place ASCII code for ten-millions place ASCII code for ten-thousands place ASCII code for hundred-thousands place b31 b28...
Page 547 Program example • The following program converts the decimal ASCII data set from D20 to D22 to BCD 4-digit data, and outputs the results to Y40 to Y4F. [Ladder Mode] Outputs the converted BCD value to a display device. [List Mode] Step Instruction Device...
Page 548: Reading Device Comment Data
Reading device comment data COMRD(P) Basic High Process Redundant Universal LCPU performance Command COMRD COMRD Command COMRDP COMRDP (S): Head number of the devices where a comment to be read is stored (Device name) (D): Head number of the devices where the read comment will be stored (character string) Setting Internal device R, ZR...
Page 549 • If no comment has been registered for the device specified by (S) despite the fact that the comment range setting is made, all of the characters for the comment are processed as "20H" (space). • The device number plus 1 where the final character of (D) is stored differs depending on the ON/OFF status of SM701 (number of characters to output select signal).
Page 550 Precautions • The processing completes after several scans. • The COMRD(P)/PRC instruction is not executed if the start signal (execution command) of the COMRD(P)/PRC instruction is turned ON before completion of the instruction (while SM721 is ON). Execute the COMRD(P)/PRC instruction when SM721 is OFF.
Page 551: Character String Length Detection
Character string length detection LEN(P) Basic High Process Redundant Universal LCPU performance Command Command LENP LENP (S): Character string or head number of the devices where the character string is stored (character string) (D): Number of the device where the length of detected character string will be stored (BIN 16 bits) Setting Internal device R, ZR...
Page 552 Program example • The following program outputs the length of the character string from D0 to Y40 to Y4F as BCD 4-digit values. [Ladder Mode] Outputs the length of character string to a display device. [List Mode] Step Instruction Device [Operation] b8b7 BCD conversion...
Page 553: Conversion From Bin 16-Bit Data To Character String, Conversion From Bin 32-Bit Data To Character String
Conversion from BIN 16-bit data to character string, conversion from BIN 32-bit data to character string STR(P), DSTR(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of STR/DSTR.
Page 554 Processing details ■STR • Adds a decimal point to the BIN 16-bit data designated by (S2) at the location designated by (S1), converts the data to character string data, and stores it in the area starting from the device number designated by (D). b8b7 ASCII code for the Total number of digits...
Page 555 ■DSTR • Adds a decimal point to the BIN 32-bit data designated by (S2) at the location designated by (S1), converts the data to character string data, and stores it following the device number designated by (D). Total number of digits b8 b7 Number of digits in decimal fraction ASCII code for the...
Page 556 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 557 • The following program converts the BIN 32-bit data stored at D10 and D11 when X0 is turned ON in accordance with the digit designation of D0 and D1, and stores the result at from D20 to D26. [Ladder Mode] Sets the data.
Page 558: Conversion From Character String To Bin 16-Bit Data, Conversion From Character String To Bin 32-Bit Data
Conversion from character string to BIN 16-bit data, conversion from character string to BIN 32-bit data VAL(P), DVAL(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. (Compatible GX Developer: Version 8.00A or later) indicates an instruction symbol of VAL/DVAL.
Page 559 Processing details ■VAL • Converts character strings stored in the device numbers starting from that designated at (S) to BIN 16-bit data, and stores the number of digits and BIN data in (D1) and (D2). For conversions from character strings to BIN, all data from the device number designated by (S) to the device number where "00H"...
Page 560 ■DVAL • Converts the character string stored in the area starting from the device designated by (S) to BIN 32-bit data, and stores the digits numbers and BIN data in (D1) and (D2). For conversions from character strings to BIN, all data from the device number designated by (S) to the device number where "00H"...
Page 561 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 562 Program example • The following program reads the character string data stored from D20 to D22 as an integer, converts it to a BIN value, and stores it at D0 when X0 is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b8b7...
Page 563: Conversion From Floating-Point Data To Character String Data
Conversion from floating-point data to character string data ESTR(P) Ver. High Basic Process Redundant Universal LCPU performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command ESTR ESTR Command ESTRP ESTRP (S1): 32-bit floating decimal point data to be converted or head number of the devices where the data is stored (real number) (S2): Head number of the devices where display designation for the numerical value to be converted is stored (BIN 16 bits) (D): Head number of the devices where the converted character string will be stored (character string) Setting...
Page 564 ■When using decimal point format b8 b7 Decimal point format ASCII code for the ASCII code for the sign (total number of digits -1) Total number of digits th digit Number of digits in decimal fraction ASCII code for the ASCII code for the (total number of digits -3) (total number of digits -2)
Page 565 • The converted character string data is stored at the area starting from the device number (D) as indicated below: • The sign "20H" (space) will be stored if the 32-bit floating decimal point type real number is positive, and the sign "2DH" (minus sign) will be stored if it is negative.
Page 566 ■When using exponent format b8b7 Exponent format ASCII code for the ASCII code for the sign (total number of digits-1)th Total number of digits digit Number of digits in decimal fraction ASCII code for the ASCII code for decimal (total number of digits-2)th point (.) (2E digit ASCII code for the...
Page 567 • The converted character string data is stored at the area starting from the device number (D) as indicated below: • If the 32-bit floating decimal point type real number data is positive in value, the sign before the integer will be stored as ASCII code "20H" (space), and if it is a negative value, the sign will be stored as "2DH"...
Page 568 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 569 Program example • The following program converts the 32-bit floating point type real number data which had been stored at R0 and R1 in accordance with the conversion designation that is being stored at R10 to R12, and stores the result following D0 when X0 goes ON.
Page 570: Conversion From Character String To Floating-Point Data
Conversion from character string to floating-point data EVAL(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command EVAL EVAL Command EVALP EVALP (S): Character string data to be converted to 32-bit floating decimal point real number data or head number of the devices where the character string data is stored (character string) (D): Head number of the devices where the converted 32-bit floating decimal point real number data will be stored (real number) Setting...
Page 571 • Excluding the sign, decimal point, and exponent portion of the result, 6 digits of the character string designated by (S) to be converted to a 32-bit floating decimal point type real number will be effective. • When using decimal point format (QnUDVCPU) b8 b7 (space) (S)+1...
Page 572 • In a case where the ASCII code "30H (0) " exists between the character "E" and a number in an exponent format character string, the "30H" would be ignored when the conversion is performed. b8b7 (space) -1 . 0 4 5 3 E + 3 .
Page 573 Program example • The following program converts the character string stored in the area starting from R0 to a 32-bit floating decimal point type real number, and stores the result at D0 and D1 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction...
Page 574: Conversion From Hexadecimal Bin To Ascii
Conversion from hexadecimal BIN to ASCII ASC(P) Basic High Process Redundant Universal LCPU performance Command Command ASCP ASCP (S): Head number of the devices where BIN data to be converted to a character string is stored (BIN 16 bits) (D): Head number of the devices where the converted character string will be stored (character string) Number of characters to be stored (BIN 16 bits) Setting Internal device...
Page 575 • If an odd number of characters has been designated by n, the ASCII code "00H" will be automatically stored in the upper 8 bits of the final device in the range where the character string is to be stored. When 5 characters have been designated by n.
Page 576: Conversion From Ascii To Hexadecimal Bin
Conversion from ASCII to hexadecimal BIN HEX(P) Basic High Process Redundant Universal LCPU performance Command Command HEXP HEXP (S): Head number of the devices where a character string to be converted to BIN data is stored (character string) (D): Head number of the devices where the converted BIN data will be stored (BIN 16 bits) Number of characters to be stored (BIN 16 bits) Setting Internal device...
Page 577 • When the number of characters is specified for n, the range of characters designated by (S) as well as the device range designated by (D) in which the BIN data will be stored are automatically decided. • Accurate processing will be conducted even in cases where the range of devices where the ASCII code to be converted is being stored overlaps with the range of devices that will store the converted BIN data.
Page 578: Extracting Character String Data From The Right, Extracting Character String Data From The Left
Extracting character string data from the right, extracting character string data from the left RIGHT(P), LEFT(P) Basic High Process Redundant Universal LCPU performance indicates an instruction symbol of RIGHT/LEFT. Command RIGHT, LEFT Command RIGHTP, LEFTP (S): Character string or head number of the devices where the character string is stored (character string) (D): Head number of the devices where the character string consisting of n characters starting from the right or left of (S) will be stored (character string) Number of characters to be extracted (BIN 16 bits) Setting...
Page 579 ■LEFT • Stores n number of characters from the left side of the character string (the beginning of the character string) being stored in devices starting from that whose number is designated by (S), in devices starting from that whose number designated by (D).
Page 580 Program example • The following program stores 4 characters of data from the rightmost of the character string stored in the area starting from R0, and stores it into the area starting from D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction...
Page 581: Random Selection From Character Strings, Random Replacement In Character Strings
Random selection from character strings, random replacement in character strings MIDR(P), MIDW(P) Basic High Process LCPU Redundant Universal performance indicates an instruction symbol MIDR/MIDW. Command MIDR, MIDW Command MIDRP, MIDWP (S1): Character string or head number of the devices where the character string is stored (character string) (D): Head number of the devices where a character string data obtained as the result of operation will be stored (character string) (S2): Head number of the devices where the location of the first character and the number of characters will be stored (BIN 16 bits) ...
Page 582 • If the number of characters designated by (S2)+1 is "-1", stores the data up to the final character designated by (S) starting from the device designated by (D). b8b7 b8b7 Position of the 5th character "EFGHIJK" "ABCDEFGHIJK" ■MIDW • Extracts the character string data of (S2)+1 characters, starting from the left end of the character string data designated by (S1), and stores the extracted data to the character string data designated by (D) in the area starting from the position designated by (S2) from the left end.
Page 583 • If the number of characters designated by (S2)+1 exceeds the final character from the character string data designated by (D), data will be stored up to the final character. Before execution b8b7 b8b7 "ABCDEFGHI" After execution "012345678" b8b7 Position counted from the left end of character string data designated by Number of characters counted...
Page 584 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. For MIDR instruction Error Error details Q00J/ QnPH QnPRH LCPU code Q00/  ...
Page 585 Program example • The following program stores the 3rd character through the 6th character from the left of the character string stored in the area starting from D10 at devices starting from D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction...
Page 586: Character String Search
Character string search INSTR(P) Basic High Process Redundant Universal LCPU performance Command INSTR INSTR Command INSTRP INSTRP (S1): Character string to be searched or head number of the devices where the character string to be searched is stored (character string) (S2): Character string in which a search is performed or head number of the devices where the character string is stored (character string) (D): Head number of the devices where the result of search will be stored (BIN 16 bits) Location to start the search (BIN 16 bits)
Page 587 Program example • The following program searches from the 5th character from the left of the character string data stored in devices starting from R0 for the character string data in devices starting from D0, and stores the results at D100 when X0 goes ON. [Ladder Mode] [List Mode] Step...
Page 588: Insertion Of Character String
Insertion of character string STRINS(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Command STRINS STRINS Command STRINSP STRINSP (S): Character string to be inserted or head number (character string) of the devices where insert character strings are stored (D): Head number (character string) of the devices where insert character strings are stored Insert position (Setting range: 1 ...
Page 589 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 590: Deletion Of Character String
Deletion of character string STRDEL(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Command STRDEL STRDEL Command STRDELP STRDELP (D): Head number (character string) of the devices where character strings to be deleted are stored Deletion start position (Setting range 1 ...
Page 591 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 592: Floating-Point Data To Bcd
Floating-point data to BCD EMOD(P) Basic High Process Redundant Universal LCPU performance Command EMOD EMOD Command EMODP EMODP (S1): 32-bit floating decimal point real number data or head number of the devices where the floating decimal point real number data is stored (real number) (S2): Decimal fraction digits data (BIN 16 bits) (D): Head number of the devices where the data after break down into BCD will be stored (BIN 16 bits) Setting...
Page 593 • The 7th digit of the significant digits being stored at (D)+1 and (D)+2 is rounded off to make a 6-digit number. . 2 3456789 1234570 123456789 Rounded off 1234570 • When an input value is set using a programming tool, a rounding error may occur. For precautions, refer to Page 89 Precautions.
Page 594: From Bcd Format Data To Floating-Point Data
From BCD format data to floating-point data EREXP(P) Basic High Process Redundant Universal LCPU performance Command EREXP EREXP Command EREXPP EREXPP (S1): Head number of the devices where BCD type floating point format data is stored (BIN 16 bits) (S2): Decimal fraction digits data (BIN 16 bits) (D): The device where the converted 32-bit floating point real number data will be stored (real number) Setting Internal device...
Page 595 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 596: Special Function Instructions
7.12 Special Function Instructions SIN operation on floating-point data (single precision) SIN(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command SINP SINP (S): Angle data of which the SIN (sine) value is obtained or head number of the devices where the angle data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 597 Program example • The following program conducts a SIN operation on the angles stored in the four BCD digits from X20 to X2F and stores the results at D0 and D1 as 32-bit floating decimal point type real numbers. [Ladder Mode] Inputs an angle used for SIN operation ( Converts the input angle into...
Page 598: Sin Operation On Floating-Point Data (Double Precision)
SIN operation on floating-point data (double precision) SIND(P) High Basic Process Redundant Universal LCPU performance Command SIND SIND Command SINDP SINDP (S): Angle data of which the SIN (sine) value is obtained or head number of the devices where the angle data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 599 Program example • The following program conducts a SIN operation on the angles stored in the four BCD digits from X20 to X2F and stores the results at D0 to D3 as 64-bit floating decimal point type real numbers. [Ladder Mode] Inputs an angle used for SIN operation ( Converts the input angle into a...
Page 600: Cos Operation On Floating-Point Data (Single Precision)
COS operation on floating-point data (single precision) COS(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command COSP COSP (S): Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 601 Program example • The following program performs a COS operation on the angle data designated by the 4 BCD digits from X20 to X2F, and stores results as 32-bit floating decimal point type real numbers at D0 and D1. [Ladder Mode] Inputs an angle used for COS operation ( Converts the input angle into...
Page 602: Cos Operation On Floating-Point Data (Double Precision)
COS operation on floating-point data (double precision) COSD(P) High Basic Process Redundant Universal LCPU performance Command COSD COSD Command COSDP COSDP (S): Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 603 Program example • The following program performs a COS operation on the angle data designated by the 4 BCD digits from X20 to X2F, and stores results as 64-bit floating decimal point type real numbers at D0 to D3. [Ladder Mode] Inputs an angle used for COS operation ( Converts the input angle into a...
Page 604: Tan Operation On Floating-Point Data (Single Precision)
TAN operation on floating-point data (single precision) TAN(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command TANP TANP (S): Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 605 Program example • The following program performs a TAN operation on the angle data set by the 4 BCD digits from X20 to X2F, and stores the results as 32-bit floating decimal point type real numbers at D0 and D1. [Ladder Mode] Inputs an angle used for TAN operation (...
Page 606: Tan Operation On Floating-Point Data (Double Precision)
TAN operation on floating-point data (double precision) TAND(P) High Basic Process Redundant Universal LCPU performance Command TAND TAND Command TANDP TANDP (S): Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 607 Program example • The following program performs a TAN operation on the angle data set by the 4 BCD digits from X20 to X2F, and stores the results as 64-bit floating decimal point type real numbers at D0 to D3. [Ladder Mode] Inputs an angle used for TAN operation (...
Page 608: Arc Sine Operation On Floating-Point Data (Single Precision)
Arc sine operation on floating-point data (single precision) ASIN(P) Basic High Process Redundant Universal LCPU performance Command ASIN ASIN Command ASINP ASINP (S): SIN value of which the SIN (inverse sine) value is obtained or head number of the devices where the SIN value is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 609 Program example • The following program seeks the inverse sine of the 32-bit floating decimal point real number at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by SIN operation ( Converts the radian value...
Page 610: Arc Sine Operation On Floating-Point Data (Double Precision)
Arc sine operation on floating-point data (double precision) ASIND(P) High Basic Process Redundant Universal LCPU performance Command ASIND ASIND Command ASINDP ASINDP (S): SIN value of which the SIN (inverse sine) value is obtained or head number of the devices where the SIN value is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 611 Program example • The following program seeks the inverse sine of the 64-bit floating decimal point real number at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by SIN operation ( Converts the radian value into an angle (...
Page 612: Arc Cosine Operation On Floating-Point Data (Single Precision)
Arc cosine operation on floating-point data (single precision) ACOS(P) Basic High Process Redundant Universal LCPU performance Command ACOS ACOS Command ACOSP ACOSP (S): COS value of which the COS (inverse cosine) value is obtained or head number of the devices where the COS value is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 613 Program example • The following program seeks the inverse cosine of the 32-bit floating decimal point real number at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by COS operation ( Converts the radian value into an angle (...
Page 614: Arc Cosine Operation On Floating-Point Data (Double Precision)
Arc cosine operation on floating-point data (double precision) ACOSD(P) High Basic Process Redundant Universal LCPU performance Command ACOSD ACOSD Command ACOSDP ACOSDP (S): COS value of which the COS (inverse cosine) value is obtained or head number of the devices where the COS value is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 615 Program example • The following program seeks the inverse cosine of the 64-bit floating decimal point real number at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by COS operation ( Converts the radian value into an angle ( Converts the angle in 64-bit floating-point...
Page 616: Arc Tangent Operation On Floating-Point Data (Single Precision)
Arc tangent operation on floating-point data (single precision) ATAN(P) Basic High Process Redundant Universal LCPU performance Command ATAN ATAN Command ATANP ATANP (S): TAN value of which the TAN (inverse tangent) value is obtained or head number of the devices where the TAN value is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 617 Program example • The following program seeks the inverse tangent of the 32-bit floating decimal point real number at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by TAN operation ( Converts the radian value...
Page 618: Arc Tangent Operation On Floating-Point Data (Double Precision)
Arc tangent operation on floating-point data (double precision) ATAND(P) High Basic Process Redundant Universal LCPU performance Command ATAND ATAND Command ATANDP ATANDP (S): TAN value of which the TAN (inverse tangent) value is obtained or head number of the devices where the TAN value is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 619 Program example • The following program seeks the inverse tangent of the 64-bit floating decimal point real number at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by TAN operation ( Converts the radian value into an angle (...
Page 620: Conversion From Floating-Point Angle To Radian (Single Precision)
Conversion from floating-point angle to radian (single precision) RAD(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command RADP RADP (S): Angle to be converted to radian units or head number of the devices where the angle is stored (real number) (D): Head number of the devices where the value converted in radian units will be stored (real number) Setting Internal device...
Page 621 Program example • The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians, and stores results as 32-bit floating decimal point type real number at D20 and D21. [Ladder Mode] Inputs an angle to be converted into a radian value ( Converts the input a 32-bit floating-point real number (...
Page 622: Conversion From Floating-Point Angle To Radian (Double Precision)
Conversion from floating-point angle to radian (double precision) RADD(P) High Basic Process Redundant Universal LCPU performance Command RADD RADD Command RADDP RADDP (S): Angle to be converted to radian units or head number of the devices where the angle is stored (real number) (D): Head number of the devices where the value converted in radian units will be stored (real number) Setting Internal device...
Page 623 Program example • The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians, and stores results as 64-bit floating decimal point type real number at D20 to D23. [Ladder Mode] Inputs an angle to be converted into a radian value ( Converts the input angle into a 64-bit floating-point real number (...
Page 624: Conversion From Floating-Point Radian To Angle (Single Precision)
Conversion from floating-point radian to angle (single precision) DEG(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command DEGP DEGP (S): Radian angle to be converted to degrees or head number of the devices where the radian angle is stored (real number) (D): Head number of the devices where the value converted in degrees will be stored (real number) Setting Internal device...
Page 625 Program example • The following program converts the radian value set with 32-bit floating decimal point type real number at D20 and D21 to angles, and stores the result as a BCD value at Y40 to Y4F. [Ladder Mode] Converts a radian value into an angle ( Converts the angle in 32-bit floating-point real...
Page 626: Conversion From Floating-Point Radian To Angle (Double Precision)
Conversion from floating-point radian to angle (double precision) DEGD(P) High Basic Process Redundant Universal LCPU performance Command DEGD DEGD Command DEGDP DEGDP (S): Radian angle to be converted to degrees or head number of the devices where the radian angle is stored (real number) (D): Head number of the devices where the value converted in degrees will be stored (real number) Setting Internal device...
Page 627 Program example • The following program converts the radian value set with 64-bit floating decimal point type real number at D20 to D23 to angles, and stores the result as a BCD value at Y40 to Y4F. [Ladder Mode] Converts a radian value into an angle ( Converts the angle in 64-bit floating-point real number into an integer ( Outputs the converted integer to a display...
Page 628: Exponentiation Operation On Floating-Point Data (Single Precision)
Exponentiation operation on floating-point data (single precision) POW(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Command Command POWP POWP (S1): Exponentiation recipient data or head number of the devices where the exponentiation recipient data are stored (real number) (S2): Exponentiation data or head number of the devices where the data are stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting...
Page 629 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 630: Exponentiation Operation On Floating-Point Data (Double Precision)
Exponentiation operation on floating-point data (double precision) POWD(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Command POWD POWD Command POWDP POWDP (S1): Exponentiation recipient data or head number of the devices where the exponentiation recipient data are stored (real number) (S2): Exponentiation data or head number of the devices where the data are stored (real number)
Page 631 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 632: Square Root Operation For Floating-Point Data (Single Precision)
Square root operation for floating-point data (single precision) SQR(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command SQRP SQRP (S): Data of which the square root is obtained or head number of the devices where the data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 633 Program example • The following program seeks the square root of the value set by the 4 BCD digits from X20 to X2F, and stores the result as a 32-bit floating decimal point type real number at D0 and D1. [Ladder Mode] Inputs data used for square root operation (...
Page 634: Square Root Operation For Floating-Point Data (Double Precision)
Square root operation for floating-point data (double precision) SQRD(P) High Basic Process Redundant Universal LCPU performance Command SQRD SQRD Command SQRDP SQRDP (S): Data of which the square root is obtained or head number of the devices where the data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 635 Program example • The following program seeks the square root of the value set by the 4 BCD digits from X20 to X2F, and stores the result as a 64-bit floating decimal point type real number at D0 to D3. [Ladder Mode] Inputs data used for square root operation (...
Page 636: Exponent Operation On Floating-Point Data (Single Precision)
Exponent operation on floating-point data (single precision) EXP(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command EXPP EXPP (S): Data of which the exponential value is obtained or head number of the devices where the data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 637 Program example • The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X27, and stores the results as a 32-bit floating decimal point real number at D0 and D1. [Ladder Mode] Inputs the data used for exponent operation ( Checks the range of the value for operation.
Page 638: Exponent Operation On Floating-Point Data (Double Precision)
Exponent operation on floating-point data (double precision) EXPD(P) High Basic Process Redundant Universal LCPU performance Command EXPD EXPD Command EXPDP EXPDP (S): Data of which the exponential value is obtained or head number of the devices where the data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 639 Program example • The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X31, and stores the results as a 64-bit floating decimal point real number at D0 to D3. [Ladder Mode] Inputs data used for exponent operation ( Checks the range of the value used...
Page 640: Natural Logarithm Operation On Floating-Point Data (Single Precision)
Natural logarithm operation on floating-point data (single precision) LOG(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command LOGP LOGP (S): Data of which the natural logarithm is obtained or head number of the devices where the data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 641 Program example • The following program seeks the natural logarithm of the value "10" set by D50, and stores the result at D30 and D31. [Ladder Mode] Sets data used for natural logarithm operation ( Converts the operation data into a 32-bit floating-point real number ( Executes natural logarithm operation ( [List Mode] Step...
Page 642: Natural Logarithm Operation On Floating-Point Data (Double Precision)
Natural logarithm operation on floating-point data (double precision) LOGD(P) High Basic Process Redundant Universal LCPU performance Command LOGD LOGD Command LOGDP LOGDP (S): Data of which the natural logarithm is obtained or head number of the devices where the data is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting Internal device...
Page 643 Program example • The following program seeks the natural logarithm of the value "10" set by D50, and stores the result at D30 to D33. [Ladder Mode] Sets data used for natural logarithm operation ( Converts the operation data into a 64-bit floating-point real number ( Executes natural logarithm operation ( [List Mode]...
Page 644: Common Logarithm Operation On Floating-Point Data (Single Precision)
Common logarithm operation on floating-point data (single precision) LOG10(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Command LOG10 LOG10 Command LOG10P LOG10P (S): Data of which the common logarithm is obtained or head number of the devices where the data are stored (real number)
Page 645 Program example • The following program obtains the value for common logarithm of the 32-bit floating-point data type real number specified by D600 or D601, when X10 is turned on. Then the program stores the operation result into D123 or D124. [Ladder Mode] [List Mode] Instruction...
Page 646: Common Logarithm Operation On Floating-Point Data (Double Precision)
Common logarithm operation on floating-point data (double precision) LOG10D(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Command LOG10D LOG10D Command LOG10DP LOG10DP (S): Data of which the common logarithm is obtained or head number of the devices where the data are stored (real number)
Page 647 Program example • This following program obtains the value for common logarithm of the 64-bit floating-point data type real number specified by D600 to D603 when M0 is turned on. Then the program stores the operation result into D123 to D126. [Ladder Mode] [List Mode] Instruction...
Page 648: Random Number Generation, Series Updates
Random number generation, series updates RND(P), SRND(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command Command RNDP RNDP Command SRND SRND Command SRNDP SRNDP (D): Head number of the devices where random numbers will be stored (BIN 16 bits) (S): Random number serial data or the first number of the devices where the random number serial data is stored (BIN 16 bits) Setting Internal device...
Page 649: Bcd 4-Digit Square Roots, Bcd 8-Digit Square Roots
BCD 4-digit square roots, BCD 8-digit square roots BSQR(P), BDSQR(P) Basic High Process Redundant Universal LCPU performance BSQR/BDSQR Command BSQR,BDSQR Command BSQRP,BDSQRP (S): Data of which the square root is obtained or the number of the device where the data is stored (BSQR(P): BCD 4 digits, BDSQR(P): BCD 8 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting Internal device...
Page 650 Program example • The following program calculates the square root of BCD value 1325 and outputs the integer part to the 4 BCD digits from Y50 to Y5F, and the decimal fraction part to the 4 BCD digits from Y40 to Y4F. [Ladder Mode] Sets the data used for square root operation (...
Page 651 • The following program calculates the square root of BCD value 74625813 and outputs the integer part of the result to the 4 BCD digits at Y50 to Y5F, and the decimal fraction part to the 4 BCD digits from Y40 to Y4F. [Ladder Mode] Sets the data (BCD value) used for square root operation (...
Page 652: Bcd Type Sin Operation
BCD type SIN operation BSIN(P) Basic High Process Redundant Universal LCPU performance Command BSIN BSIN Command BSINP BSINP (S): Data of which the SIN (sine) value is obtained or the number of the device where the data is stored (BCD 4 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting Internal device...
Page 653 Program example • The program example below calculates the SIN of 3-digit BCD data designated by X20 to X2B, and outputs a 1-digit BCD part to the integer part from Y50 to Y53, and a 4-digit BCD fraction part from Y40 to Y4F. Y60 is turned ON if the results of the operation are negative.
Page 654: Bcd Type Cos Operations
BCD type COS operations BCOS(P) Basic High Process Redundant Universal LCPU performance Command BCOS BCOS Command BCOSP BCOSP (S): Data of which the COS (cosine) value is obtained or head number of the devices where the data is stored (BCD 4 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting Internal device...
Page 655 Program example • The following program calculates the cosine of the data designated by the 3 BCD digits from X20 to X2B and outputs the integer part of the result to 1 BCD digit from Y50 to Y53, and the decimal fraction part of the result to the 4 BCD digits from Y40 to Y4F.
Page 656: Bcd Type Tan Operation
BCD type TAN operation BTAN(P) Basic High Process Redundant Universal LCPU performance Command BTAN BTAN Command BTANP BTANP (S): Data of which the TAN (tangent) value is obtained or head number of the devices where the data is stored (BCD 4 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting Internal device...
Page 657 Program example • The following program calculates the tangent of the data stored in the 3 BCD digits from X20 to X2B, and stores the integer part of the results in the 4 BCD digits from Y50 to Y53, and the decimal fraction part in the 4 BCD digits from Y40 to Y4F. Y60 is turned ON if the results of the operation are negative.
Page 658: Bcd Type Arc Sine Operations
BCD type arc sine operations BASIN(P) Basic High Process Redundant Universal LCPU performance Command BASIN BASIN Command BASINP BASINP (S): Number of the device where data of which the SIN (inverse sine) value is obtained is stored (BCD 4 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting Internal device...
Page 659 Program example • The following program performs a SIN operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit decimal fraction part from X20 to X2F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
Page 660: Bcd Type Arc Cosine Operation
BCD type arc cosine operation BACOS(P) Basic High Process Redundant Universal LCPU performance Command BACOS BACOS Command BACOSP BACOSP (S): Number of the device where data of which the COS (inverse cosine) value is obtained is stored (BCD 4 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting Internal device...
Page 661 Program example • The following program performs a COS operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit decimal fraction part from X20 to X2F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
Page 662: Bcd Type Arc Tangent Operations
BCD type arc tangent operations BATAN(P) Basic High Process Redundant Universal LCPU performance Command BATAN BATAN Command BATANP BATANP (S): Number of the device where data of which the TAN (inverse tangent) value is obtained is stored (BCD 4 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting Internal device...
Page 663 Program example • The following program performs a TAN operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 4-digit integer part from X20 to X2F and the BCD 4-digit decimal fraction part from X30 to X3F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
Page 664: Data Control Instructions
7.13 Data Control Instructions Upper and lower limit controls for BIN 16-bit data, upper and lower limit controls for BIN 32-bit data LIMIT(P), DLIMIT(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of LIMIT/DLIMIT. Command LIMIT, DLIMIT Command LIMITP, DLIMITP (S1): Lower limit value (minimum output threshold value) (BIN 16/32 bits)
Page 665 ■DLIMIT • The function controls the output value to be stored at the device designated by ((D), (D)+1) by checking whether the input value (BIN 32 bits) designated by ((S3), (S3)+1) is within the range of upper and lower limit values specified by ((S1), (S1)+1) and ((S2), (S2)+1) or not.
Page 666 Program example • The following program conducts limit controls from 500 to 5000 on the data set as BCD values from X20 to X2F, and stores the result at D1 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation]...
Page 667: Bin 16-Bit Dead Band Controls, Bin 32-Bit Dead Band Controls
BIN 16-bit dead band controls, BIN 32-bit dead band controls BAND(P), DBAND(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of BAND/DBAND. Command BAND, DBAND Command BANDP, DBANDP (S1): Lower limit value of dead band (no output band) (BIN 16/32 bits) (S2): Upper limit value of dead band (no output band) (BIN 16/32 bits) (S3): Input value to be controlled by a dead band control (BIN 16/32 bits) (D): Head number of the devices where the output value controlled by the dead band control will be stored (BIN 16/32 bits)
Page 668 ■DBAND • Controls the output value to be stored at the device designated by (D) by checking whether the input value (BIN 32 bits) designated by ((S3), (S3)+1) is within the range of dead band upper and lower limit values specified by ((S1), (S1)+1) and ((S2), (S2)+1) or not.
Page 669 Program example • The following program performs the dead band control by applying the lower and upper limits of 0 and 1000 for the data set in BCD at X20 to X2F and stores the result of control at D1 when X0 is turned ON. [Ladder Mode] [List Mode] Step...
Page 670: Zone Control For Bin 16-Bit Data, Zone Control For Bin 32-Bit Data
Zone control for BIN 16-bit data, zone control for BIN 32-bit data ZONE(P), DZONE(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ZONE/DZONE. Command ZONE, DZONE Command ZONEP, DZONEP (S1): Negative bias value to be added to an input value (BIN 16/32 bits) (S2): Positive bias value to be added to an input value (BIN 16/32 bits) (S3): Input value used for a zone control (BIN 16/32 bits) (D): Head number of the devices where the output value controlled by the zone control will be stored (BIN 16/32 bits).
Page 671 ■DZONE • Adds bias value designated by ((S1), (S1)+1) or ((S2), (S2)+1) to input value designated by ((S3), (S3)+1), and stores the result at device number designated by ((D), (D)+1). Addition of the bias value is performed as follows: Condition Result Input value ((S3)+1, (S3)) + Negative bias value ((S1)+1, (S1)) ...
Page 672: Scaling (Coordinate Data By Point)
Scaling (coordinate data by point) SCL(P), DSCL(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of SCL/DSCL. Command SCL, DSCL (S1)
Page 673 • If the value does not result in an integer, this instruction rounds the value to the whole number. • Set the X coordinate of the scaling conversion data in ascending order. • Set the input value (S1) within the range of the scaling conversion data (within the range of (S2) devices). •...
Page 674 Precautions • There are two searching methods that depend on whether SM750 is on or off. SM750 Searching method Range of number of searches 1  Number of times  32767 Sequential search 1  Number of times  15 Binary search •...
Page 675 Program example • The following program executes scaling for the scaling conversion data of which the devices specified at D100 and up are set with the input value specified at D0, and then outputs the data at D20. [Ladder Mode] [List Mode] Step Instruction...
Page 676: Scaling (Coordinate Data By X And Y)
Scaling (coordinate data by X and Y) SCL2(P), DSCL2(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of SCL2/DSCL2. Command SCL2, DSCL2 (S1)
Page 677 • If the value does not result in an integer, this instruction rounds the value to the whole number. • Set the X coordinate of the scaling conversion data in ascending order. • Set the input value (S1) within the range of the scaling conversion data (within the range of (S2) devices). •...
Page 678 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 679: File Register Switching Instructions
7.14 File Register Switching Instructions Switching file register block numbers RSET(P) Ver. Ver. High Basic Process LCPU Redundant Universal performance • Q00JCPU cannot be used. • Universal model QCPU: Models other than Q00UJCPU Command RSET RSET Command RSETP RSETP (S): Block number data used to change the block number or the number of the device where the block number data is stored (BIN 16 bits) Setting Internal device R, ZR...
Page 680 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00/ QnPH QnPRH LCPU code 4100 The block number specified in (S) does not exist. ...
Page 681: File Setting For File Register
File setting for file register QDRSET(P) Ver. Basic High LCPU Process Redundant Universal performance • Universal model QCPU: Models other than Q00UJCPU Command QDRSET QDRSET Command QDRSETP QDRSETP (S): Character string data of the drive No./file name in which the file register is set, or head number of the devices where the character string data is stored (character string) Setting Internal device...
Page 682 • If the file name is changed with the QDRSET instruction, the file name returns to the name specified by the parameter when the CPU module is switched from STOP to RUN. To maintain the file name even after the CPU mode is changed from STOP to RUN, execute the QDRSET instruction with the SM402 special relay, which turns ON during one scan when the CPU enters from STOP to RUN mode.
Page 683: File Setting For Comments
File setting for comments QCDSET(P) Basic High Process Redundant Universal LCPU performance Command QCDSET QCDSET Command QCDSETP QCDSETP (S): Character string data of the drive No./file name in which the comment file is set, or head number of the devices where the character string data is stored (character string) Setting Internal device...
Page 684 Operation error • In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/       2410 The file name does not exist at the drive number specified in (S).
Page 685: Clock Instructions
7.15 Clock Instructions Reading clock data DATERD(P) High Basic Process Redundant Universal LCPU performance Command DATERD DATERD Command DATERDP DATERDP (D): Head number of the devices where the read clock data will be stored (BIN 16 bits) Setting Internal device R, ZR J\...
Page 686 Program example • The following program outputs the following clock data as BCD values: • Year: Y70 to Y7F • Month: Y68 to Y6F • Day: Y60 to Y67 • Hour: Y58 to Y5F • Minute: Y50 to Y57 • Second: Y48 to Y4F •...
Page 687: Writing Clock Data
Writing clock data DATEWR(P) High Basic Process LCPU Redundant Universal performance Command DATEWR DATEWR Command DATEWRP DATEWRP (S): Head number of the devices where clock data to be written into the clock device is stored (BIN 16 bits) Setting Internal device R, ZR J\...
Page 688 Program example • The following program writes the following clock data to the clock element as BCD values when X40 is turned ON. • Year: X30 to X3F • Month: X28 to X2F • Day: X20 to X27 • Hour: X18 to X1F •...
Page 689: Clock Data Addition Operation
Clock data addition operation DATE+(P) High Basic Process LCPU Redundant Universal performance Command DATE+ DATE+ Command DATE+P DATE+P (S1): Head number of the devices where the clock data to be adjusted by addition is stored (BIN 16 bits) (S2): Head number of the devices where the time data to be added for adjustment is stored (BIN 16 bits) (D): Head number of the devices where the result of addition of clock (time) data will be stored (BIN 16 bits) Setting Internal device...
Page 690 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 691: Clock Data Subtraction Operation
Clock data subtraction operation DATE-(P) High Basic Process LCPU Redundant Universal performance Command DATE- DATE- Command DATE-P DATE-P (S1): Head number of the devices where the clock time data to be adjusted by subtraction is stored (BIN 16 bits) (S2): Head number of the devices where time data to be subtracted for adjustment is stored (BIN 16 bits) (D): Head number of the devices where the result of subtraction of clock (time) data will be stored (BIN 16 bits) Setting Internal device...
Page 692 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 693: Time Data Conversion (From Hour/Minute/Second To Second)
Time data conversion (from hour/minute/second to second) SECOND(P) High Basic Process LCPU Redundant Universal performance Command SECOND SECOND Command SECONDP SECONDP (S): Head number of the devices where the clock data before conversion is stored (BIN 16 bits) (D): Head number of the devices where the clock data after conversion will be stored (BIN 32 bits) Setting Internal device R, ZR...
Page 694 Program example • The following program converts the clock time data read from the clock element into second when X20 is turned ON, and stores the result at D100 and D101. [Ladder Mode] [List Mode] Step Instruction Device [Operation] • Time data read operation triggered by DATERDP instruction. Clock device Year Month...
Page 695: Time Data Conversion (From Second To Hour/Minute/Second)
Time data conversion (from second to hour/minute/second) HOUR(P) High Basic Process LCPU Redundant Universal performance Command HOUR HOUR Command HOURP HOURP (S): Head number of the devices where clock data before conversion is stored (BIN 32 bits) (D): Head number of the devices where the clock data after conversion will be stored (BIN 16 bits) Setting Internal device R, ZR...
Page 696 Program example • The following program converts the seconds stored at D0 and D1 into an hour, minute, second format, and stores the result at devices starting from D100 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] •...
Page 697: Hour Meter
Hour meter HOURM Ver. Ver. High Basic Process Redundant LCPU Universal performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command HOURM HOURM (S): Start number of the device where the data of the time (to be set in increments of hour) during which (D2) is turned ON (BIN 16 bits) (D1): Start number of the device where the data of the current value in increments of hour is stored (BIN 16 bits) (D2): Start bit device number to which an alarm is to be output (Bit) Setting...
Page 698: Hour Meter
Hour meter DHOURM Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command DHOURM DHOURM (S): Start number of the device where the data of the time (to be set in increments of hour) during which (D2) is turned ON (BIN 32 bits) (D1): Start number of the device where the data of the current value in increments of hour is stored (BIN 32 bits) (D2): Start bit device number to which an alarm is to be output (Bit) Setting...
Page 699: Date Comparison
Date comparison LDDT, ANDDT, ORDT Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported DT=/DT<>/DT</DT<=/DT>/DT>= indicates an instruction symbol of Command Command (S1): Head number of the devices where the data to be compared are stored (BIN 16 bits) (S2): Head number of the devices where the data to be compared are stored (BIN 16 bits) Value of the data to be compared or the number of the stored data to be compared (BIN 16 bits)
Page 700 • This instruction sets BIN values for each item. • This instruction sets the year of four digits selected from 1980 to 2079 with the BIN value specified by (S1) or (S2). • This instruction sets the month selected from 1 to 12 (January to December) with the BIN value specified by (S1)+1 or (S2)+1.
Page 701 • The following table shows the comparison operation results for each instruction. Instruction symbol Condition Comparison Instruction symbol Condition Comparison operation result operation result (S1)=(S2) Conductive status (S1)(S2) No-conductive status DT<> (S1)(S2) DT<> (S1)=(S2) DT> (S1)>(S2) DT> (S1)(S2) DT<= (S1)(S2) DT<= (S1)>(S2) DT<...
Page 702 Program example • The following program compares the data stored in D0 with the data (year, month, and day) stored in D10, and makes Y33 be conductive status when the data stored in D0 meet the data stored in D10. [Ladder Mode] [List Mode] Instruction...
Page 703: Time Comparison
Time comparison LDTM, ANDTM, ORTM Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of TM=/TM<>/TM</TM<=/TM>/TM>=. Command Command (S1): Head number of the devices where the data to be compared are stored (BIN 16 bits) (S2): Head number of the devices where the data to be compared are stored (BIN 16 bits) Value of the data to be compared or the number of the stored data to be compared (BIN 16 bits)
Page 704 • This instruction sets BIN values for each item. • This instructions sets the time selected from 0 to 23 (midnight to 23 o'clock) with the BIN value specified by (S1) or (S2). (Uses the 24-hour clock.) • This instructions sets the minute selected from 0 to 59 (0 to 59 minutes) with BIN value specified by (S1)+1 or (S2)+1. •...
Page 705 • If the data stored in the devices to be compared are not recognized as date data, SM709 will be turned on after the instruction execution and no-conductive status will be made. Once SM709 is turned on, on-status will be retained till when the CPU modules are reset or powered off.
Page 706 Program example • The following program compares the data stored in D0 with the data (hour, minute, and second) stored in D10, and makes Y33 be conductive status when the data stored in D0 meet the data stored in D10. [Ladder Mode] [List Mode] Instruction...
Page 707: Clock Data Comparison
Clock data comparison TCMP(P) Ver. Ver. High Basic Process Redundant LCPU Universal performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command TCMP TCMP Command TCMPP TCMPP (S1): Start number of the devices where the comparison target time data "hour" is stored (0 to 23) (BIN 16 bits) (S2): Start number of the devices where the comparison target time data "minute"...
Page 708 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored in SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 709: Time Data Band Comparison
Time data band comparison TZCP(P) Ver. Ver. High Basic Process Redundant LCPU Universal performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command TZCP TZCP Command TZCPP TZCPP (S1): Start number of the devices where the lower limit values (hour, minute, second) of the comparison target time data are stored (three points occupied) (device name) (S2): Start number of the devices where the upper limit values (hour, minute, second) of the comparison target time data are stored (three points occupied) (device name)
Page 710 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored in SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 711: Expansion Clock Instructions
7.16 Expansion Clock Instructions Reading expansion clock data S(P).DATERD Ver. Ver. Ver. Basic High Process LCPU Redundant Universal performance • High Performance model QCPU: The serial number (first five digits) is "07032" or later. • Process CPU: The serial number (first five digits) is "07032" or later. •...
Page 712 Program example • The following program outputs the following clock data as BCD values: • Year: Y70 to Y7F • Month: Y68 to Y6F • Day: Y60 to Y67 • Hour: Y58 to Y5F • Minute: Y50 to Y57 • Second: Y48 to Y4F •...
Page 713 Precautions • This instruction reads clock data and stores those to a specified device even if a wrong clock data is set to the CPU module (example: Feb. 30th). When setting clock data with the DATEWR instruction or GX Developer, make sure to set a correct data.
Page 714: Expansion Clock Data Addition Operation
Expansion clock data addition operation S(P).DATE+ Ver. Ver. Ver. Basic High Process Redundant Universal LCPU performance • High Performance model QCPU: The serial number (first five digits) is "07032" or later. • Process CPU: The serial number (first five digits) is "07032" or later. •...
Page 715 Devices, (S1)+3, (S2)+3, and (D)+3 are not used for operation. A clock data read by the S(P).DATERD instruction can be directly added. Hour Minute (D)+1 Second (D)+2 Day of week (D)+3 Millisecond (D)+4 When the clock data is read by the S(P).DATERD instruction, day of week is inserted between "second" and "millisecond". If the S(P).DATE+ instruction is used to read the clock data, the data can be directly used for addition since it does not perform the calculation for the day of a week.
Page 716 Program example • The following program adds 1 hour to the clock data read from the clock element, and stores the results into the area starting from D100 when X20 is turned ON. [Ladder Mode] Reads out the clock element data to D0 or later.
Page 717: Expansion Clock Data Subtraction Operation
Expansion clock data subtraction operation S(P).DATE- Ver. Ver. Ver. Basic High Process Redundant Universal LCPU performance • High Performance model QCPU: The serial number (first five digits) is "07032" or later. • Process CPU: The serial number (first five digits) is "07032" or later. •...
Page 718 Devices, (S1)+3, (S2)+3, and (D)+3 are not used for operation. A clock data read by S(P).DATERD instruction can be directly subtracted. Hour Minute (D)+1 Second (D)+2 Day of week (D)+3 Millisecond (D)+4 When the clock data is read by the S(P).DATERD instruction, day of week is inserted between "second" and "millisecond". If the S(P).DATE- instruction is used to read the clock data, the data can be directly used for subtraction since it does not perform the calculation for the day of the week.
Page 719 Program example • The following program subtracts the time data stored in the area starting from D10 from the clock data read from the clock element when X1C is turned ON, and stores the result into the area starting from D100. [Ladder Mode] Reads out the clock element data to D0 or later.
Page 720: Program Control Instructions
7.17 Program Control Instructions Processing when the execution type is converted with the program control instruction is as follows. Execution type before Executed Instruction change PSCAN PSTOP POFF PLOW Scan execution type No change-remains scan Becomes stand-by type. Output turned OFF in next Becomes low speed type execution.
Page 721: Program Standby
Program standby PSTOP(P) Basic High Process Redundant Universal LCPU performance Command PSTOP PSTOP Command PSTOPP PSTOPP (S): Character string for the name of the program file to be set in the stand-by status or head number of the devices where the character string data is stored (character string) Setting Internal device...
Page 722: Program Output Off Standby
Program output OFF standby POFF(P) Basic High Process Redundant Universal LCPU performance Command POFF POFF Command POFFP POFFP (S): File name of the program to be set in the standby status by turning OFF the output, or the device where the file name is stored (character string) Setting Internal device R, ZR...
Page 723 Program example • The following program makes the program with the file name ABC non-executionable and places it in the standby status when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 7 APPLICATION INSTRUCTIONS 7.17 Program Control Instructions...
Page 724: Program Scan Execution Registration
Program scan execution registration PSCAN(P) Basic High Process Redundant Universal LCPU performance Command PSCAN PSCAN Command PSCANP PSCANP (S): File name of the program to be set as a scan execution type, or head number of the devices where the file name is stored (character string) Setting Internal device R, ZR...
Page 725 Program example • The following program sets the program with file name ABC as scan execution type when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 7 APPLICATION INSTRUCTIONS 7.17 Program Control Instructions...
Page 726: Program Low Speed Execution Registration
Program low speed execution registration PLOW(P) Basic High LCPU Redundant Universal Process performance Command PLOW PLOW Command PLOWP PLOWP (S): File name of the program to be set as a low speed execution type, or head number of the devices where the file name is stored (character string) Setting Internal device R, ZR...
Page 727: Program Execution Status Check
Program execution status check LDPCHK, ANDPCHK, ORPCHK Basic High LCPU Universal Process Redundant performance File name PCHK LDPCHK Command PCHK File name ANDPCHK Command ORPCHK PCHK File name (S): File name of the program whose execution status will be checked (character string) Setting Internal device R, ZR...
Page 728 The PCHK instruction is in conduction when the program of the specified file name (target program) is in execution, and the instruction is in non-conduction when the program is in non-execution. When the target program is set to non-execution (stand-by type) with the POFF instruction, the PCHK instruction is in conduction while the non-execution processing of the target program is being performed.
Page 729: Pid Instruction
Process control instruction • QnPHCPU MELSEC-Q Programming/Structured Programming Manual (Process Control • QnPRHCPU Instructions) PID control instruction • QnACPU MELSEC-Q/L/QnA Programming Manual (PID Control Instructions) • QnCPU • QnHCPU • QnPRHCPU • QnUCPU • QnUDVCPU • LCPU PID operation instruction •...
Page 730 Operation method of PID operation instruction (reference) The instruction performs the PID operation using the speed type or process value differential type operational expression. The operational expression of direct action or reverse action is performed according to the data in bit 0 of (S3)+1 (operation setting (ACT)) Each value required in the operation calculates using parameters specified (S3) or later.
Page 731: Pid Control
PID control Ver. Ver. High Basic Process Redundant LCPU Universal performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command (S1): Device number where the set value (SV) is stored (device name) (S2): Device number where the process value (PV) is stored (device name) (S3): Start number of devices where parameters are stored (device name) (D): Device number where the manipulated value (MV) is stored (device name) Setting...
Page 732 • The setting items of the parameter (S3) are listed below. Setting item Description Remark (S3) Sampling time (T 1 to 32767 ms The instruction cannot be used with a value smaller than the operation cycle. (S3)+1 Operation setting Bit 0 0: Direct action Specify the operation direction.
Page 733 Precautions • The instruction can be executed multiple times (no limit in the number of loops). However, be careful not to duplicate (S3) used for operation and the device number specified by (D). Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/...
Page 734 Error Error details Q00J/ QnPH QnPRH LCPU code Q00/       9121 Auto tuning by the limit cycle method resulted in an error by exceeding the auto tuning measurement time as follows. •  >,  <0, <0 9122 Auto tuning by the limit cycle method went out of the range of proportional...
Page 735: Parameters
Parameters This section explains the parameters of the PID operation instruction (PID). Sampling time (T ): (S3) Setting range: 1 to 32767ms Set the cycle (ms) for PID operation. • PID control or auto tuning (limit cycle method) "Operation cycle of programmable controller"<"sampling time" •...
Page 736 Action setting (ACT): (S3)+1 ■Direct action/reverse action: (S3)+1 Bit 0 Setting range: OFF = direct action/ON = reverse action Select the direct action or reverse action for the PID control direction. • In the case of auto tuning (limit cycle method) For auto tuning, the user needs to set the relevant PID control direction, direct action or reverse action.
Page 737 ■Alert setting (rate of change in input, rate of change in output): (S3)+1 Bits 1, 2 Setting range: OFF = Disable alert for change in input/Enable alert for change in input The rates of changes in input and output can be checked. The result of checking can be confirmed by (S3)+24. (For the operation of input/output value upper/lower limit alarm output, see (S3)+24 (warning output flag operation).
Page 738 Input filter (): (S3)+2 Setting range: 0 to 99[%] PID control: proportional operation, integral operation, derivative operation The input filter () is a software filter that reduces the variations caused by process value (PV) noise. Effects of noise can be suppressed by setting the time constant of the filter according to the characteristics and noise levels of the control target.
Page 739 Proportional gain (K ): (S3)+3 Setting range: 1 to 32767[%] PID control: proportional operation The manipulated value (MV) increases in proportion to the error (difference between the set value (SV) and process value (PV)) in the proportional operation. This proportion is called the proportional gain (K ) and is expressed in the following relational expression.
Page 740 Integral time (T ): (S3)+4 Setting range: 0 to 32767 [100ms] (0 is treated as . (No integration)) PID control: integral operation The time taken from when an error occurs in the integral operation to when the output of the integral operation becomes the output of the proportional operation is called the integral time expressed in T When T is reduced, the integral operation becomes stronger.
Page 741 The integral operation is an operation to change the output to remove the error generated in succession. This can eliminate the residual error occurring in the proportional operation. Error (EV) Time Output by P action + I action Output by I action Output by P action Proportional gain (K ) ×...
Page 742 Derivative time (T ): (S3)+6 Setting range: 0 to 32767 [10ms] PID control: derivative operation PID control is used to sensitively react to changes caused in the process value (PV) by disturbance and minimize the changes. • Increasing the derivative time (T ) enhances the movement to prevent the controlled system from varying greatly due to disturbance.
Page 743 PID operation in cooling (direct action) > T > T PI action (D action not performed) Change caused by disturbance (PID action) (PID action) (PID action) Time > T > T Response to the disturbance (PID action) (PID action) PI action (D action not performed) (PID action) Time 7 APPLICATION INSTRUCTIONS...
Page 744 Warning output flag operation: (S3)+24 When the specified rate of input/output changes is exceeded, each bit of (S3)+24 turns on as an alarm flag immediately after the execution of the PID operation instruction. • Rate of input change (bit 1 of (S3)+1 is ON) Rate of change Time Sampling time (TS)
Page 745: Auto Tuning
Auto tuning This section explains the auto tuning function of the PID operation instruction. The auto tuning function automatically sets the proportional gain and integral time that are important constants in order to optimize PID control. The auto tuning function can be implemented in two methods: limit cycle method and step response method.
Page 746 ■Determining the three PID constants (limit cycle method) [Reference] To obtain good control result of PID control, optimal values of individual constants (parameters) appropriate to the controlled system need to be determined. Here, the limit cycle method is explained as a method of determining the amplitude (a) and vibration cycle (, ...
Page 747 Step response method ■Parameters set by auto tuning (limit cycle method) • (S3)+1 (action setting (ACT)) bit 0 (action direction) • (S3)+3 (proportional gain (K • (S3)+4 (integral time (T • (S3)+6 (derivative time (T ■Auto tuning procedure Transfer the output values for auto tuning to (D) (manipulated value (MV)). Set the output value for auto tuning to the "maximum output allowable for the output equipment ...
Page 748 ■Determining the three PID constants (step response method) [Reference] To obtain good control result of PID control, optimal values of individual constants (parameters) appropriate to the controlled system need to be determined. Here, the step response method is explained as a method of determining the optimal values of three PID constants (proportional gain (K ), integral time (T ), and derivative time (T...
Page 749: Example Of Practical Program (Step Response Method)
Example of practical program (step response method) This section provides a sample program to implement auto tuning using the step response method in the following system. System and operation example ■System configuration CPU module PID control converter Sensor module Control target (example: converter constant...
Page 750 ■Operation of output value • PID control D502 × 1ms <On time> 2 seconds (2000ms) 2 seconds (2000ms) 2 seconds (2000ms) <Cycle> • Auto tuning with maximum output 90% 1.8 seconds (1800ms) 1.8 seconds (1800ms) 1.8 seconds (1800ms) 2 seconds (2000ms) 2 seconds (2000ms) 2 seconds (2000ms) 7 APPLICATION INSTRUCTIONS...
Page 751 Program example in auto tuning (step response method) + PID control • Device Device Description Start PID control after auto tuning. Start PID control (without auto tuning). Auto tuning setting flag Auto tuning operation flag Stop auto tuning. PID running Auto tuning operation flag •...
Page 752 Program example in auto tuning (step response method) only • Device Device Description Start auto tuning. Start auto tuning. PID operation Stop auto tuning. Auto tuning operation flag • Program Set the SV. <50°C> Set the auto tuning output cycle. <On time: 1.8 seconds>...
Page 753: Troubleshooting
Troubleshooting Error code If an error occurs in the set value of a control parameter or the data used for PID operation, the operation error flag (SM0) turns on and an error code is stored in SD0 according to the error content. For the error code, refer to the User's Manual (Hardware Design, Maintenance and Inspection) of the CPU module used.
Page 754: Other Instructions
7.19 Other Instructions Watchdog timer reset WDT(P) High Basic Process LCPU Redundant Universal performance Command Command WDTP WDTP Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Resets watchdog timer during the execution of a sequence program. •...
Page 755 Program example • The following program has a watchdog timer setting of 200ms, when due to the execution conditions program execution requires 300ms from step 0 to the END (FEND) instruction. [When WDT instruction is used] Program where Program where scan time is scan time is 150 ms.
Page 756: Timing Pulse Generation
Timing pulse generation DUTY High Basic Process Redundant Universal LCPU performance Command DUTY DUTY Number of scans for ON (BIN 16 bits) Number of scans for OFF (BIN 16 bits) (D): User timing clock (SM420 to SM424, SM430 to SM434) (bits) Setting Internal device R, ZR...
Page 757 Program example • The following program turns SM420 ON for 1 scan, and OFF for 3 scans if X0 is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] SM420 1 scan 3 scans 7 APPLICATION INSTRUCTIONS 7.19 Other Instructions...
Page 758: Time Check
Time check TIMCHK Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. command TIMCHK TIMCHK (S1): Device where the measured current value will be stored (unit: 100ms) (BIN 16 bits) (S2): The set value for measurement or the device where the set value is stored (unit: 100ms) (Setting range: 0 ...
Page 759: Direct 1-Byte Read From File Register
Direct 1-byte read from file register ZRRDB(P) High Basic Process LCPU Redundant Universal performance Command ZRRDB ZRRDB Command ZRRDBP ZRRDBP Serial byte number for the file register to be read (BIN 32 bits) (D): Number of the device where the read data will be stored (BIN 16 bits) Setting Internal device R, ZR...
Page 760 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 761: File Register Direct 1-Byte Write
File register direct 1-byte write ZRWRB(P) High Basic Process LCPU Redundant Universal performance Command ZRWRB ZRWRB Command ZRWRBP ZRWRBP Serial byte number for the file register to be written (BIN 32 bits) (S): Number of the device where the data to be written is stored (BIN 16 bits) Setting Internal device R, ZR...
Page 762 • If n=12340 is specified, the data will be written to the lower 8 bits of ZR6170. Write destination b8 b7 b8 b7 designation 12340 Ignored ZR6170 b8 b7 • If n=43257 is specified, the data will be written to the upper 8 bits of ZR21628. Write destination designation b8 b7...
Page 763: Indirect Address Read Operations
Indirect address read operations ADRSET(P) High Basic Process LCPU Redundant Universal performance Command ADRSET ADRSET Command ADRSETP ADRSETP (S): Number of the device whose indirect address is read out (Device name) (D): Head number of the device where the indirect address of the device designated by (S) will be stored (BIN 32 bits) Setting Internal device R, ZR...
Page 764: Numerical Key Input Using Keyboard
Numerical key input using keyboard Basic High LCPU Redundant Universal Process performance Command (S): Head number of the devices (X) to which a numeral will be input (bits) Number of digits of the numeral to be input (BIN 16 bits) (D1): Head number of the devices where the input numeral will be stored (BIN 16 bits) (D2): Number of the bit device to turn ON at the completion of input (bits) Setting...
Page 765 • Numerical input to input (X) designated by (S) undergoes bit development at (S) through (S)+7 and is input as the ASCII code corresponding to the numbers. ASCII code which can be input is from 30H (0) to 39H (9), and from 41H (A) to 46H (F).
Page 766 • The number of digits that can be designated by n is from 1 to 8. • Fetching of the input data is completed when any of the inputs shown below has been made. At the completion, the bit device designated by (D2) is turned ON. •...
Page 767 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 768: Batch Save Of Index Register, Batch Recovery Of Index Register
Batch save of index register, batch recovery of index register ZPUSH(P), ZPOP(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ZPUSH/ZPOP. Command ZPUSH, ZPOP Command ZPUSHP, ZPOPP (D): Head number of the devices to/from which contents of an index register are saved/recovered (BIN 16 bits) Setting Internal device R, ZR...
Page 769 • When using a High Performance model QCPU/Process CPU/Redundant CPU (D)+0 Number of saves · 1st nesting (18 words for the 1st nesting) Reserved by the system (2 words) 2nd nesting · • When using Universal model QCPU/LCPU (D)+0 Number of saves ·...
Page 770 Program example • The following program saves the contents of the index register to the fields following D0 before calling the subroutine following P0 that uses the index register. [Ladder Mode] [List Mode] Step Instruction Device 7 APPLICATION INSTRUCTIONS 7.19 Other Instructions...
Page 771: Reading Module Information
Reading module information UNIRD(P) High Basic Process LCPU Redundant Universal performance Command UNIRD UNIRD Command UNIRDP UNIRDP Value (0 to FFn) which the start I/O number of the module information read source is divided by 16 (BIN 16 bits) (D): Head number of the devices where the module information will be stored (device name) The number of points of read data (0 to 256) (BIN 16 bits) Setting Internal device...
Page 772 Item Description QCPU LCPU Module ready status 1: Normal 0: Module error occurred Empty Fixed to 0 Module type 1: A series module Fixed to 0 0: Q series module Module installation status 1: Modules are installed. 0: No modules are installed. *1 The Universal model QCPU used in the multiple CPU system is turned ON during the online module change of the module controlled by the other CPU.
Page 773 Program example • The following program stores the module information at I/O numbers 10H and 20H into the devices starting from D0 when X0 is turned ON. Module information Device X/Y0 module information X/Y10 module information X/Y20 module information X/YFE0 module information X/YFF0 module information [Ladder Mode] [List Mode]...
Page 774 • 32-point module for A series b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 For an A series module, all of these bits turn 0 because information is not stored. A series module Module is installed b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 All of these bits turn 0 because information is stored to "D0".
Page 775: Reading Module Model Name
Reading module model name TYPERD(P) Ver. High Basic Process Redundant Universal LCPU performance • Universal model QCPU: The serial number (first five digits) is "11043" or later. Command TYPERD TYPERD Command TYPERDP TYPERDP Setting Internal device R, ZR J\ U\G Constant Others data...
Page 776 When the target module occupies one slot LCPU (L26CPU-BT) CPU module (L26CPU-BT) Power Built-in Built-in LX40 LX40 LX40 L60A LY41 LY10 LY10 LY10 supply CC-Link NT1P module Start I/O number configured in the I/O 0000 0010 0030 0040 0050 0060 0070 0090 00A0...
Page 777 • (D)+0 and (D)+1 to (D)+9 store the execution result of the instruction and module model name, respectively. A value stored in (D) is as follows: ■When the model name has been written to the target module (example: QJ71GP21-SX) b8 b7 Stores 0.
Page 778 ■Others • The specified slot is empty or the target module is during online module change. • The specified value (n) is not the start I/O number. • The specified value (n) is within the allowable setting range, but cannot be set in the I/O assignment setting screen of the PLC parameter dialog box. b8 b7 Stores -1.
Page 779: Trace Set, Trace Reset
Trace set, trace reset TRACE, TRACER Ver. Basic High Process Redundant Universal LCPU performance • Universal model QCPU: Models other than Q00UJCPU Command TRACE TRACE Command TRACER TRACER Setting Internal device R, ZR J\ U\G Constant Others data Word Word ...
Page 780 ■TRACE • The TRACE instruction is an instruction which performs the following: turn ON SM803, perform the sampling for the number of the sampling trace after executing the TRACE instruction, latch the sampling traces result, and stop the sampling trace. •...
Page 781: Writing Data To Designated File
Writing data to designated file SP.FWRITE Ver. Ver. Basic High Process Redundant Universal LCPU performance • Universal model QCPU: Models other than Q00UJCPU, Q00UCPU, and Q01UCPU • Built-in Ethernet port LCPU: Supported • L02SCPU and L02SCPU-P cannot be used. Command SP.FWRITE SP.FWRITE Setting...
Page 782 Setting Meaning Setting range Set by Data type data (D0) Head number of the devices storing the control data. The following control data is required. BIN 16 bits Device Item Contents/setting data Setting range Set by (D0) Execution/ Designate the execution type. 0000H User completion...
Page 783 Setting Meaning Setting range Set by Data type data (D1) Bit device that turned ON at the completion of the processing. ((D1)+1 is also turned ON at error completion.) Device Item Contents/setting data Setting range Set by  (D1) Completion Indicates the completion of the processing.
Page 784 ■When writing binary data • If the extension of the target file is omitted, ".BIN" is used as an extension. • When the designated file does not exist, a new file is created and the data is saved from the beginning of the file. The attributes of this new file are set using the archive attributes.
Page 785 ■When writing data after CSV format conversion • If the extension is omitted, ".CSV" is used as an extension. • When the existing file is specified: [High Performance model QCPU of which the first five digits of the serial number are "01111" or lower] File contents are all deleted and data are saved, starting at the beginning.
Page 786 • When data is written after CSV format conversion and the designated number of columns is other than "0", the data is stored as table data with designated number of columns in a CSV format file. When data is written after CSV format conversion and the designated No. of columns is other than "0": D20 D99 M0 SP.FWRITE * Designation in word units...
Page 787 • When data is added by the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU of which the first five digits of the serial number are 01112 or higher: [Specify the file to which data will be written.] (If a file exists, delete it and create a new file again.) Execution type = CSV format File position...
Page 788 • Below is the method for calculating the file size (total number of bytes) when a CSV format file is written to the ATA card. Total number of bytes = Total bytes excluding final line + bytes of final line (Number of bytes on a line = number of columns + 1 + total bytes of all data values on line *4 For all lines but the final line, this is the specified number of columns.
Page 789 Program example • When X10 is turned ON, the following program adds four bytes of binary data (00H, 01H, 02H, and 03H) to file "ABCD.BIN" in the memory card inserted to drive 2. • Assume that 8 points from (D0) are reserved for the control data devices. [Ladder Mode] Sets the execution/completion type Sets the designation of the number of columns...
Page 790 • When X10 is turned ON, the following program creates a file named "ABCD.CSV" in the memory card inserted to drive 2, and writes four bytes of data (00H, 01H, 02H, and 03H) as two-column table data in CSV format. •...
Page 791: Reading Data From Designated File
Reading data from designated file SP.FREAD Ver. Ver. Basic High Process Redundant Universal LCPU performance • Universal model QCPU: Models other than Q00UJCPU, Q00UCPU, and Q01UCPU • Built-in Ethernet port LCPU: Supported • L02SCPU and L02SCPU-P cannot be used. Command SP.FREAD SP.FREAD Setting...
Page 792 Setting Meaning Setting range Set by Data type data (D0) (D0)+4 File position Designate the file position to start reading when binary 00000000H to User BIN 16 bits (D0)+5 data reading is designated by (D0). FFFFFFFFH 00000000H: Starting at the beginning of the file 00000001H to FFFFFFFEH: From the designated position (The unit for the value is determined by word/ byte unit designation.)
Page 793 Precautions • At (S0) (drive designation), only the ATA card drive (2) can be set.(For QCPU) Note that when the Flash card is loaded, the SP.FREAD instruction cannot be used to perform read. The SRAM card, standard RAM or standard ROM drive cannot be set.
Page 794 ■When reading binary data • If the extension of the target file is omitted, ".BIN" is used as an extension. • When the designated file does not exist, an error occurs. • If the position specified is greater than the existing file size: •...
Page 795 • When the designated number of columns is 0, the data is read by ignoring the rows in CSV format file. When data is read after CSV format conversion and the designated No. of columns is 0: Data created by EXCEL Measured value Main / sub item Length...
Page 796 • If the number of columns varies in each row, the data is also read by ignoring the rows. Such file cannot be created using EXCEL. This happens when CSV file is modified by a user. If the number of columns varies in each row when the data is read: Data saved as a CSV file Main / sub item Measured value...
Page 797 • When data is read after CSV format conversion and the designated number of columns is other than 0, the data is read as the table with designated number of columns in CSV format file. The elements outside of the designated columns are ignored.
Page 798 • If the number of columns varies in each row, the elements outside of the designated columns are ignored and "0" is added to the places where elements do not exist. If the number of columns varies in each row when the data is read: Main / sub item , , Measured value Excess CR LF...
Page 799 • With the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU whose first five digits of the serial number are "01112" or later, it is possible to divide read operation into multiple times. [Specify the row desired to start read.] Execution type = CSV format Starting row number...
Page 800 • When read is performed in the continuation mode, the previous addition cannot be made normally if the "execution type", "No. of columns designation" and "data type specification" settings differ from those at the previous time. • The previous addition cannot be made normally if the SP.FREAD instruction or SP.FWRITE instruction with another setting is executed while data is being read continuously in the continuation mode.
Page 801 Program example • The following program reads 4 bytes of binary data from the beginning of file "ABCD.BIN" in the memory card inserted to drive 2 when X10 is turned ON. • Assume that 8 points from (D0) are reserved for the control data devices. •...
Page 802 • The following program reads file "ABCD.CSV" in the memory card inserted to drive 2 as two-column table data in CSV format when X10 is turned ON. • Assume that 8 points from (D0) are reserved for the control data devices. •...
Page 803: Writing Data To Standard Rom
Writing data to standard ROM SP.DEVST High Basic Process Redundant Universal LCPU performance Command SP.DEVST SP.DEVST Write offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit) (S): Head device number written to the standard ROM (device name) The number of write points (BIN 16-bit) (D): (D)+0: Completion device (bit) (D)+1: Error completion device (bit)
Page 804 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 805: Reading Data From Standard Rom
Reading data from standard ROM S(P).DEVLD High Basic Process Redundant Universal LCPU performance Command S.DEVLD S.DEVLD Command SP.DEVLD SP.DEVLD Read offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit) (D): Head device number read from the standard ROM (device name) The number of reading points (BIN 16-bit) Setting Internal device...
Page 806 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 807: Loading Program From Memory Card
Loading program from memory card PLOADP Basic High LCPU Redundant Universal Process performance Command PLOADP PLOADP (S): Drive No. storing the program to be loaded, character string data of the file name, or head number of the devices storing the character string data (BIN 16 bits) (D): Device that turns ON for 1 scan by the instruction completion (bits) Setting...
Page 808 • The PLC file settings of the loaded program are set as follows: ■File usage for each program All the usage of file register, device initial value, comment, and local device of the program transferred by this instruction are set as "Use PLC file setting". However, an error will be returned if both of the conditions below are met when the program is transferred using this instruction.
Page 809 Precautions • The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously. If two or more of the above instructions are executed simultaneously, the instruction executed later will not be executed. When using the above instructions, provide interlocks manually to avoid simultaneous execution. •...
Page 810: Unloading Program From Program Memory
Unloading program from program memory PUNLOADP Basic High LCPU Redundant Universal Process performance Command PUNLOADP PUNLOADP (S): Character string data of the program file name to be unloaded, or head number of the devices storing the character string data (BIN 16 bits) (D): Device turned ON for 1 scan on completion of the instruction (bits) Setting Internal device...
Page 811 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 812: Loading And Unloading
Loading and unloading PSWAPP Basic High LCPU Redundant Universal Process performance Command PSWAPP PSWAPP (S1): Character string data of the file name of the program to be unloaded, or head number of the devices storing the character string data (BIN 16 bits) (S2): Drive No.
Page 813 • The PLC file settings of the program on which the PSWAPP instruction has been conducted are set as follows: • When the boot setting has been made in the PLC parameter, the program where the boot setting has been made is transferred to the program memory. To execute the program replaced by the PSWAPP instruction, change the boot setting and the program setting in the PLC parameter for the corresponding program name.
Page 814: High-Speed Block Transfer Of File Register
High-speed block transfer of file register RBMOV(P) Ver. Basic High LCPU Process Redundant Universal performance • Universal model QCPU: Models other than Q00UJCPU Command RBMOV RBMOV Command RBMOVP RBMOVP (S): Head number of the devices where the data to be transferred is stored (BIN 16 bits) (D): Head number of the devices of transfer destination (BIN 16 bits) Number of data to be transferred (BIN 16 bits) Setting...
Page 815 Transfer ranges of ZR and R overlap when transferring 10000 points of data from ZR30000 (source) to R10 (block No.1 of the destination). • ZR transfer range  (30000) to (30000+10000-1)  (30000) to (39999) • R transfer range  (10+(1  32768)) to (10+(1  32768)+10000-1)  (32778) to (42777) Therefore, the range 32778 to 39999 overlaps.
Page 816 ■Transfer from file registers to internal devices/internal devices to file registers Instruction Target memory 1 word 1000 words 10000 words where file register is Min. Max. Min. Max. Min. Max. stored QnHCPU RBMOV Standard RAM 20.0s 91.0s 775.0s QnPHCPU SRAM card 22.0s 305.0s 2900.0s...
Page 817 ■Transfer from file registers to file registers Instruction Target memory 1 word 1000 words 10000 words where file register is Min. Max. Min. Max. Min. Max. stored QnHCPU RBMOV Standard RAM 20.0s 91.0s 775.0s QnPHCPU SRAM card 22.5s 545.0s 5300.0s QnPRHCPU BMOV Standard RAM...
Page 818 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 819: User Message
User message UMSG Ver. High Basic Process Redundant Universal LCPU performance • Built-in Ethernet port LCPU: Supported • L02SCPU and L02SCPU-P cannot be used. Command UMSG UMSG (S): String to display on display unit, or lead number (string) of device storing string to display Setting Internal device R, ZR...
Page 820 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 821 • This program displays "Line-A Working" on the display unit when M0 is set to "on". [Ladder Mode] [List Mode] Step Instruction Device "Line-A Working" "Line-A Working" [Operation] b15 to b8 b7 to b0 User message Line-A Working Run UMSG instruction 0000 •...
Page 822: Chapter 8 Instructions For Data Link
INSTRUCTIONS FOR DATA LINK Abbreviation of instruction symbols In this chapter, instruction names are abbreviated as follows if not specified particularly. • S(P).ZCOM  ZCOM • S(P).RTREAD  RTREAD • S(P).RTWRITE  RTWRITE Network Refresh Instructions Refresh for the designated module S(P).ZCOM High Basic...
Page 823 Processing details • When the ZCOM instruction is executed, the CPU module temporarily suspends processing of the sequence program and conducts refresh processing of the network modules designated by Jn/Un. (For LCPU whose serial number (first five digits) is "13011" or earlier, the designation by Jn cannot be made.) Execution of ZCOM Execution of ZCOM Execution of ZCOM...
Page 824 ■CC-Link IE Controller Network and MELSECNET/H (PLC to PLC network) When the scan time for the sequence program of host station is longer than the scan time for the other station, the ZCOM instruction is used to ensure the data reception from the other station. •...
Page 825 ■MELSECNET/H (remote I/O network) The link refresh of the remote master station is performed by the "END processing" of the CPU module. Since link scan is performed at completion of link refresh, link scan 'synchronizes' with the program of the CPU module. When the ZCOM instruction is used at the remote master station, link refresh is performed at the point of ZCOM instruction execution, and link scan is performed at completion of link refresh.
Page 826 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 827: Reading/Writing Routing Information
Reading/Writing Routing Information Reading routing information S(P).RTREAD Ver. Basic High Process Redundant Universal LCPU performance • LCPU: The serial number (first five digits) is "13012" or later. Command S.RTREAD S.RTREAD Command SP.RTREAD SP.RTREAD Transfer destination network No. (1 to 239) (BIN 16 bits) (D): Head number of the devices that stores the read data (Device name) Setting Internal device...
Page 828 Program example • The following program reads the routing information for the network number specified by D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] [Routing parameter setting] Transfer Relay network Relay station destination number number network number Dummy...
Page 829: Registering Routing Information
Registering routing information S(P).RTWRITE Ver. Basic High Process Redundant Universal LCPU performance • LCPU: The serial number (first five digits) is "13012" or later. Command S.RTWRITE S.RTWRITE Command SP.RTWRITE SP.RTWRITE Transfer destination network No. (1 to 239) (BIN 16 bits) (S): Head number of the devices where the data to be written is stored (Device name) Setting Internal device...
Page 830 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 831: Refresh Device Write/Read Instructions
Refresh Device Write/Read Instructions Refresh device write (in 1-bit units) S(P).REFDVWRB Ver. Ver. High Basic Process Redundant LCPU Universal performance • QnUD(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "14072" or later • QnUDVCPU: the serial number (first five digits) is "16043" or later. •...
Page 832 Processing details • The contents of the data stored in the area starting from (S1) are as indicated below. Device Item Setting contents Setting range (S1)+0 Station number Station number for the station assigned the refresh device which writes data. 1 to 120 When the link special relay (SB) is specified as type of (S1)+1, the setting is disabled.
Page 833 When a refresh range per station is assigned in transfer settings, specify number of write points so that the range written data from the specified offset is within the range assigned in the same transfer setting. An error occurs if the number of write points over the range assigned in each transfer setting is specified. •...
Page 834 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 835: Refresh Device Write (In 16-Bit Units)
Refresh device write (in 16-bit units) S(P).REFDVWRW Ver. Ver. High Basic Process Redundant LCPU Universal performance • QnUD(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "14072" or later • QnUDVCPU: the serial number (first five digits) is "16043" or later. •...
Page 836 • Number of points specified in n2 is written from the device specified in (S2) to the offset specified in (S1)+2 of the refresh device assigned for the device specified in (S1)+1 of the target station specified in n1 and (S1)+0. [Structure] Master Specified...
Page 837 • The station type which can and cannot specify with the start I/O number is as follows. Specification Station type possibility Enabled CC-Link master station, CC-Link master station (compatible with redundant function), CC-Link IE Field Network master station Disabled CC-Link local station, CC-Link standby master station, CC-Link IE Field Network local station, CC-Link IE Field Network submaster station •...
Page 838 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 839 Precautions • Do not execute the instruction in an interrupt program. If the instruction is executed, no processing is performed. In addition, the completion device ((D1)+0), the completion device ((D1)+1), and SM739 do not turn on. If the instruction is executed in a fixed scan execution type program, they also do not turn on.
Page 840: Refresh Device Read (In 1-Bit Units)
Refresh device read (in 1-bit units) S(P).REFDVRDB Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUD(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "14072" or later • QnUDVCPU: the serial number (first five digits) is "16043" or later. •...
Page 841 • Number of points specified in n2 is read from the device specified in (D1) to the offset specified in (S1)+2 of the refresh device assigned for the device specified in (S1)+1 of the target station specified in n1 and (S1)+0. [Structure] Master Specified...
Page 842 • The station type which can and cannot specify with the start I/O number is as follows. Specification Station type possibility Enabled CC-Link master station, CC-Link master station (compatible with redundant function), CC-Link IE Field Network master station Disabled CC-Link local station, CC-Link standby master station, CC-Link IE Field Network local station, CC-Link IE Field Network submaster station •...
Page 843 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 844: Refresh Device Read (In 16-Bit Units)
Refresh device read (in 16-bit units) S(P).REFDVRDW Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUD(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "14072" or later • QnUDVCPU: the serial number (first five digits) is "16043" or later. •...
Page 845 • Number of points specified in n2 is read from the device specified in (D1) to the offset specified in (S1)+2 of the refresh device assigned for the device specified in (S1)+1 of the target station specified in n1 and (S1)+0. [Structure] Master Specified...
Page 846 • The station type which can and cannot specify with the start I/O number is as follows. Specification Station type possibility Enabled CC-Link master station, CC-Link master station (compatible with redundant function), CC-Link IE Field Network master station Disabled CC-Link local station, CC-Link standby master station, CC-Link IE Field Network local station, CC-Link IE Field Network submaster station •...
Page 847 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 848: Chapter 9 Multiple Cpu Dedicated Instructions
MULTIPLE CPU DEDICATED INSTRUCTIONS Writing to the CPU Shared Memory of Host CPU The S.TO or TO instruction is used to write to the CPU shared memory of the host station in the multiple CPU system. The following table indicates the usability of the S.TO and TO instructions. CPU module S.TO instruction TO instruction...
Page 849 Operation of the TO instruction The TO instruction can write device memory data to the following memories. • CPU shared memory of host CPU module • Buffer memory of intelligent function module The following figure shows the processing performed when the TO instruction is executed in CPU No. 1. Intelligent CPU No.
Page 850: Writing To Host Cpu Shared Memory
Writing to host CPU shared memory S(P).TO Ver. Ver. High LCPU Redundant Basic Process Universal performance • Q00CPU, Q01CPU: The serial number (first five digits) is "04122" or later. • High Performance model QCPU: Function version B or later Command S.TO S.TO Command...
Page 851 Processing details • Writes device data of words n3 to n4 to the CPU shared memory address specified by n2 of the host CPU module or later address. When writing is completed, the completion bit specified by (D) turns ON. Host CPU CPU shared memory Device memory...
Page 852 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 853: Writing To Host Cpu Shared Memory
Writing to host CPU shared memory TO(P), DTO(P) Ver. High Process LCPU Redundant Basic Universal performance • Q00CPU, Q01CPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of TO/DTO. Command TO, DTO Command TOP, DTOP Start I/O number of the host CPU module (BIN 16 bits) ...
Page 854 • When a constant is specified to (S), writes the same data (value specified to (S)) to the area of n3 words from the specified CPU shared memory. CPU shared memory of host CPU (n1) Constant (When "5" is designated Writes the n3 words same data to...
Page 855 ■DTO • Writes device data of words (S) to (n32) to the CPU shared memory address specified by n2 of the host CPU module or later address. Host CPU CPU shared memory Device memory of host CPU (n1) n3 2 Writes the data of (n3 2) words...
Page 856 Program example • The following program stores 10 points of data from D0 into address 10000 of the CPU shared memory of CPU No. 1 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device • The following program stores 20 points of data from D0 into address 10000 of the CPU shared memory of CPU No. 4 when X0 is turned ON.
Page 857: Reading From The Cpu Shared Memory Of Another Cpu
Reading from the CPU Shared Memory of Another The FROM(P)/DFRO(P) instruction of Multiple CPU system can be read from the following memories. • Buffer memory of intelligent function module • CPU shared memory of other CPU module • CPU shared memory of host CPU module (applicable for the Basic model QCPU and Universal model QCPU) The following figure shows the processing performed when the FROM(P) instruction is executed in CPU No.
Page 858: Reading From Other Cpu Shared Memory
Reading from other CPU shared memory FROM(P), DFRO(P) Ver. Ver. High LCPU Redundant Basic Process Universal performance • Q00CPU, Q01CPU: The serial number (first five digits) is "04122" or later. • High Performance model QCPU: Function version B or later ■When Basic model QCPU, Universal model QCPU is used indicates an instruction symbol of FROM/DFRO.
Page 859 Processing details ■FROM • Reads the data of n3 words from the CPU shared memory address designated by n2 of the CPU module designated by n1, and stores that data into the area starting from the device designated by (D). CPU shared memory of Device memory the designated CPU (n1)
Page 860 ■DFRO • Reads the data of (n32) words from the CPU shared memory address designated by n2 of the CPU module designated by n1, and stores that data into the area starting from the device designated by (D). CPU shared memory of the Device memory designated CPU (n1) Reads the data...
Page 861 FROM(P) ■When High Performance model QCPU, Process CPU is used Command FROM FROM Command FROMP FROMP Start I/O number of the reading target CPU module (3E0H to 3E3H) (BIN 16 bits) Head address of data to be read (BIN 16 bits) (D): Head number of the devices where the read data is stored (BIN 16 bits) Number of read data (BIN 16 bits) Setting...
Page 862 • When 0 is specified in n3 as the number of data to be read, no processing is performed. • The number of data to be read changes depending on the target CPU module. CPU module Number of read points High Performance model QCPU 1 to 4096 Process CPU...
Page 863: Chapter 10 Multiple Cpu High-Speed Transmission Dedicated Instructions
MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS 10.1 Overview The multiple CPU high-speed transmission dedicated instruction directs the Universal model QCPU to write/read device data to/from the Universal model QCPU in another CPU. The following shows an operation when CPU No.1 writes device data to CPU No.2 with the multiple CPU high-speed transmission dedicated instruction.
Page 864 Writable/readable devices ■Writable/readable device names The following table shows the devices that can be written to/read from the Universal model QCPU in another CPU with the multiple CPU high-speed transmission dedicated instruction. Category Type Device name Setting of target Remark device (:Settable, :Settable with conditions)
Page 865 ■String specification The string specification is a method to specify a device in another CPU to be written/read by character string. [Program for string specification with the DP.DDWR instruction] DP.DDWR H3E1 D100 "D200" Specifies "D200", a device in another CPU to be written by character string.
Page 866 Managing the multiple CPU high speed transmission area The multiple CPU high speed transmission area is managed by blocks in units of 16 words. The following table shows the number of blocks that can be used in each CPU and the number of blocks used in the instruction.
Page 867 The instructions that can be executed concurrently For the Universal model QCPU, the multiple CPU high-speed transmission dedicated instructions can be concurrently executed within the range satisfying the following formula. The number of blocks that Total number of blocks used for the can be used in each CPU instructions concurrently executed When the number of blocks used for the multiple CPU high-speed transmission dedicated instructions exceeds the total...
Page 868 Interlock when using the multiple CPU high-speed transmission dedicated instruction Special relays SM796 to SM799 (maximum number of used blocks for multiple CPU high-speed transmission dedicated instruction setting) can be used as an interlock for the multiple CPU high-speed transmission dedicated instruction. When executing the multiple CPU high-speed transmission dedicated instructions concurrently, use SM796 to SM799 as an interlock for the instructions.
Page 869 Program example ■Program example when SM796 to SM799 are used as an interlock The following shows a program that executes the D.DDWR instruction to CPU No.2 at the rise of X0, and executes the D.DDWR instruction to CPU No.3 at the rise of X1. The maximum number of used blocks for multiple CPU high-speed transmission dedicated instruction SM402 SD797...
Page 870 ■Program example when the multiple CPU high-speed transmission dedicated instructions are executed to CPU modules by turns When the multiple CPU high-speed transmission dedicated instructions are executed to Universal model QCPUs by turns, release an interlock to prevent the concurrent execution. Use the cyclic transmission area device (from U3En\G10000) as an interlock.
Page 871 • Program example when the multiple CPU high-speed transmission dedicated instruction is executed at CPU No.2 SM402 SD796 Turn-on for one Maximum number of scan after RUN used blocks (CPU No.1) During execution the Read instruction DDRD instruction U3E1\G10000.0 is turned on while CPU No.2 is executing the DP.DDRD instruction. U3E0\G10000.0 SM796 U3E1\...
Page 872 ■Program example when data exceeding 100 words are written/read with the multiple CPU high-speed transmission dedicated instruction The maximum number of write/read points that can be processed with the multiple CPU high-speed transmission dedicated instruction is 100 words. Data exceeding 100 words can be written/read by executing the multiple CPU high-speed transmission dedicated instruction at several times.
Page 873 • Program example when the D(P).DDWR instructions are executed concurrently The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction. As shown on the program example, multiple CPU device write/read instructions can be executed concurrently. When reading/writing devices with the multiple CPU high-speed transmission dedicated instructions concurrently, the more the total number of blocks in the multiple CPU high speed transmission area (send area), the more the time taken to complete reading/writing with the multiple CPU high-speed transmission dedicated instruction can be shortened.
Page 874: Writing Devices To Another Cpu
10.2 Writing Devices to Another CPU D(P).DDWR Ver. High Basic Process LCPU Redundant Universal performance • Universal model QCPU: The serial number (first five digits) is "10012" or later. • Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU cannot be used. Command D.DDWR D.DDWR Command DP.DDWR...
Page 875 Processing details • In multiple CPU system, data stored in a device specified by host CPU (S2) or later is stored by the number of write points specified by ((D2)+1) into a device specified by another CPU (n) (D1) or later. Start device number of the storage Start device number of the location where read has been stored...
Page 876 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 877 Precautions • Digit specification of bit device is possible for n, (S2), and (D1). Note that when the digit specification of bit device is made to (S2) or (D1), the following conditions must be met. • Digits are specified by 16 bits (4 digits). •...
Page 878: Reading Devices From Another Cpu
10.3 Reading Devices from Another CPU D(P).DDRD Ver. High Basic Process LCPU Redundant Universal performance • Universal model QCPU: The serial number (first five digits) is "10012" or later. • Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU cannot be used. Command D.DDRD D.DDRD Command DP.DDRD...
Page 879 Processing details In multiple CPU system, data stored in a device specified by another CPU (n) (D1) or later is stored by the number of read points specified by (S1)+1 into a device specified by host CPU (S2) or later. Start device number of the storage Start device number of the location where write data has stored...
Page 880 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 881 Precautions • Digit specification of bit device is possible for n, (S2), and (D1). Note that when the digit specification of bit device is made to (S2) or (D1), the following conditions must be met. • Digits are specified by 16 bits (4 digits). •...
Page 882: Chapter 11 Redundant System Instructions (For Redundant Cpu)
REDUNDANT SYSTEM INSTRUCTIONS (FOR REDUNDANT CPU) 11.1 System Switching SP.CONTSW High Basic Process LCPU Universal Redundant performance Command SP.CONTSW SP.CONTSW (S): Value other than 0 and used to identify the processing that issued the system switching request (BIN 16 bits) (D): Error completion device number (bits) Setting Internal device...
Page 883 Processing details • Switches between the control system and standby system at the END processing of the scan executed with the SP.CONTSW instruction. • When using the SP.CONTSW instruction for system switching, the "manual switching enable flag (SM1592)" must have been turned ON (enabled) in advance.
Page 884 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
Page 885: Appendices
APPENDICES Appendix 1 Operation Processing Time Definition Processing time taken by the QCPU, LCPU is the total of the following processing times. • Total of each instruction processing time • END processing time (including I/O refresh time) • Processing time for the function that increases the scan time Instruction processing time For the processing time of each instruction, refer to the following.
Page 886: Operation Processing Time Of Basic Model Qcpu
Operation processing time of Basic model QCPU The processing time for the individual instructions are shown in the table on the following pages. Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time rather than as being strictly accurate.
Page 887 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU When not executed 0.88 0.55 When After time up 0.88 0.55 executed When added 0.88 0.55 0.96 0.60 When not executed 0.88 0.55 When After time up 0.88 0.55 executed When added 0.88 0.55 0.96...
Page 888 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU FEND Error check performed No error check performed • Battery check • Fuse blown check • I/O module verification  0.20 0.16 0.10  NOPLF 0.20 0.16 0.10 PAGE ■Basic instructions The processing time when the instruction is not executed is calculated as follows: •...
Page 889 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU OR< When not executed 0.70 0.56 0.35 When In conductive status 0.80 0.64 0.40 executed In non-conductive status 0.80 0.64 0.40 LD>= In conductive status 0.80 0.64 0.40 In non-conductive status 0.80 0.64 0.40...
Page 890 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU LDD>= In conductive status 0.80 0.50 In non-conductive status 0.80 0.50 ANDD>= When not executed 0.80 0.64 0.40 When In conductive status 0.80 0.50 executed In non-conductive status 0.80 0.50 ORD>= When not executed 0.80 0.64...
Page 891 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU DB- (S) (D)  DB-P (S) (D)  DB- (S1) (S2) (D) DB-P (S1) (S2) (D)  B* (S1) (S2) (D) B*P (S1) (S2) (D)  B/ (S1) (S2) (D) B/P (S1) (S2) (D) DB* (S1) (S2) (D) ...
Page 892 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU $MOV 0 characters $MOVP 32 characters  0.70 0.56 0.35 CMLP DCML  0.90 0.72 0.45 DCMLP BMOV (S) (D) n BMOVP (S) (D) n n=96 FMOV (S) (D) n FMOVP (S) (D) n n=96 ...
Page 893 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU DOR (S1) (S2) (D) When executed 0.75 DORP (S1) (S2) (D) BKOR (S1) (S2) (D) n BKORP (S1) (S2) (D) n n=96 WXOR (S) (D) When executed 0.80 0.50 WXORP (S) (D) WXOR (S1) (S2) (D) When executed 0.96...
Page 894 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU BRST (D) n BRSTP (D) n n=15  TEST (S1) (S2) (D) TESTP (S1) (S2) (D) DTEST (S1) (S2) (D)  DTESTP (S1) (S2) (D) BKRST (D) n BKRSTP (D) n n=96 SER (S1) (S2) (D) n All match...
Page 895 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU WSUM (S) (D) n WSUMP (S) (D) n n=96 DWSUM (S) (D) n DWSUMP (S) (D) n n=96 FOR n  NEXT  BREAK BREAKP  CALL Pn CALLP Pn CALL Pn (S1) to (S5) ...
Page 896 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU  DATERD DATERDP DATEWR  DATEWRP DATE+ No digit increase DATE+P Digit increase DATE- No digit increase DATE - P Digit increase  SECOND SECONDP  HOUR HOURP  WDTP  DUTY ...
Page 897 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU ORE= Single When not executed precision When In conductive status 42.0 35.0 32.5 executed In non-conductive 37.0 31.0 28.5 status LDE<> Single In conductive status 46.0 38.0 35.5 precision In non-conductive status 43.5 36.0 33.0...
Page 898 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU E+ (S) (D) Single (S)=0, (D)=0 29.5 25.0 23.0 E+P (S) (D) precision (S)=2 , (D)=2 65.5 60.5 49.5 E+ (S1) (S2) (D) Single (S1)=0, (S2)=0 31.0 27.0 24.0 E+P (S1) (S2) (D) precision (S1)=2 , (S2)=2...
Page 899 Instruction Condition (device) Processing time (s) Q00JCPU Q00CPU Q01CPU FROM Reading from n3=1  host CPU  n3=320 shared memory  Reading from n3=1 other CPU n3=320  shared memory  Writing to host n3=1 CPU shared  n3=320 memory ...
Page 900: Operation Processing Time Of High Performance Model Qcpu/Process Cpu/Redundant Cpu
Operation processing time of High Performance model QCPU/ Process CPU/Redundant CPU The processing time for the individual instructions are shown in the table on the following pages. Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time rather than as being strictly accurate.
Page 901 Instruction Condition (device) Processing time (s) QnPH QnPRH OUTH When not executed 0.63 0.27 0.27 0.27 When After time up 0.63 0.27 0.27 0.27 executed When added 0.63 0.27 0.27 0.27 0.63 0.27 0.27 0.27 When not executed 0.158 0.068 0.068 0.068 When executed...
Page 902 ■Basic instructions The processing time when the instruction is not executed is calculated as follows: • Q02CPU: 0.079  (No. of steps for each instruction + 1) s • Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU, Q12PRHCPU, Q25PRHCPU: 0.034  (No. of steps for each instruction + 1) s Instruction Condition (device) Processing time (s)
Page 903 Instruction Condition (device) Processing time (s) QnPH QnPRH AND< When not executed 0.24 0.10 0.10 0.10 When executed In conductive 0.24 0.10 0.10 0.10 status In non-conductive 0.24 0.10 0.10 0.10 status OR< When not executed 0.24 0.10 0.10 0.10 When executed In conductive 0.24...
Page 904 Instruction Condition (device) Processing time (s) QnPH QnPRH ORD> When not executed 0.39 0.17 0.17 0.17 When executed In conductive 0.55 0.24 0.24 0.24 status In non-conductive 0.55 0.24 0.24 0.24 status LDD<= In conductive status 0.55 0.24 0.24 0.24 In non-conductive status 0.55 0.24...
Page 905 Instruction Condition (device) Processing time (s) QnPH QnPRH ANDE= Single When not executed 0.55 0.24 0.24 0.24 precision When In conductive executed status 14.9 In non-conductive status 14.9     Double When not executed precision   When In conductive executed status...
Page 906 Instruction Condition (device) Processing time (s) QnPH QnPRH LDE> Single In conductive status precision 14.9 In non-conductive status 14.9   Double In conductive status precision 14.9   In non-conductive status 14.9 ANDE> Single When not executed 0.55 0.24 0.24 0.24 precision...
Page 907 Instruction Condition (device) Processing time (s) QnPH QnPRH ORE<= Single When not executed 0.55 0.24 0.24 0.24 precision When In conductive executed status 14.9 In non-conductive status 14.9   Double When not executed 0.55 0.24 precision   When In conductive executed status...
Page 908 Instruction Condition (device) Processing time (s) QnPH QnPRH ANDE>= Single When not executed 0.55 0.24 0.24 0.24 precision When In conductive executed status 14.9 In non-conductive status 14.9 Double When not executed 0.55 0.24   precision   When In conductive executed status...
Page 909 Instruction Condition (device) Processing time (s) QnPH QnPRH OR$> When not executed 0.56 0.24 0.24 0.24 When executed In conductive status In non-conductive status LD$<= In conductive status In non-conductive status AND$<= When not executed 0.56 0.23 0.23 0.23 When executed In conductive status In non-conductive...
Page 910 Instruction Condition (device) Processing time (s) QnPH QnPRH + (S1) (S2) (D) When executed 0.47 0.20 0.20 0.20 +P (S1) (S2) (D) - (S) (D) When executed 0.39 0.17 0.17 0.17 -P (S) (D) - (S1) (S2) (D) When executed 0.47 0.20 0.20...
Page 911 Instruction Condition (device) Processing time (s) QnPH QnPRH E- (S1) (S2) (D) Single (S1)=0, (S2)=0 E-P (S1) (S2) (D) precision (S1)=2 , (S2)=2 Double (S1)=0, (S2)=0   precision   (S1)=2 , (S2)=2 E* (S1) (S2) (D) Single (S1)=0, (S2)=0 E*P (S1) (S2) (D) precision (S1)=2...
Page 912 Instruction Condition (device) Processing time (s) QnPH QnPRH  DGRY DGRYP GBIN  GBINP  DGBIN DGBINP  NEGP  DNEG DNEGP ENEG  ENEGP BKBCD (S) (D) n BKBCDP (S) (D) n n=96 BKBIN (S) (D) n BKBINP (S) (D) n n=96 (S)=D0, (D)=D1 0.24...
Page 913 Instruction Condition (device) Processing time (s) QnPH QnPRH RAMP     PLSY       *1 The Qn/QnH changes in processing time depending on the serial No. of the CPU module. Top: The first five digits of the serial No. are "05031" or lower Bottom: The first five digits of the serial No.
Page 914 ■Application instructions The processing time when the instruction is not executed is calculated as follows: • Q02CPU: 0.079  (No. of steps for each instruction + 1) s • Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU, Q12PRHCPU, Q25PRHCPU: 0.034  (No. of steps for each instruction + 1) s Instruction Condition (device) Processing time (s)
Page 915 Instruction Condition (device) Processing time (s) QnPH QnPRH DRCR (D) n DRCRP (D) n n=31 DROL (D) n DROLP (D) n n=31 DRCL (D) n DRCLP (D) n n=31 SFR (D) n 0.75 0.75 0.75 SFRP (D) n n=15 0.85 0.85 0.85 SFL (D) n...
Page 916 Instruction Condition (device) Processing time (s) QnPH QnPRH  NDIS (S1) (D) (S2) NDISP (S1) (D) (S2) NUNI (S1) (D) (S2)  NUNIP (S1) (D) (S2) WTOB (S) (D) n WTOBP (S) (D) n n=96 BTOW (S) (D) n BTOWP (S) (D) n n=96 MAX (S) (D) n MAXP (S) (D) n...
Page 917 Instruction Condition (device) Processing time (s) QnPH QnPRH IXDEV+IXSET Number of contacts 1 Number of contacts 14 FIFW Number of data points 0 FIFWP Number of data points 96 FIFR Number of data points 1 FIFRP Number of data points 96 FPOP Number of data points 1 FPOPP...
Page 918 Instruction Condition (device) Processing time (s) QnPH QnPRH DHABIN (S)=1 DHABINP (S)=FFFFFFFFH DABCD (S)=1 DABCDP (S)=9999 DDABCD (S)=1 DDABCDP (S)=99999999  COMRD COMRDP 1 character LENP 96 characters  STRP  DSTR DSTRP  VALP  DVAL DVALP  ESTR ESTRP EVAL Decimal point format all 2-digit specification...
Page 919 Instruction Condition (device) Processing time (s) QnPH QnPRH Single precision RADP   Double precision Single precision DEGP   Double precision Single precision SQRP   Double precision 1812 Single precision (S)=-10 EXPP (S)=1   Double precision (S)=-10 2386 1026 (S)=1...
Page 920 Instruction Condition (device) Processing time (s) QnPH QnPRH DATE+ No digit increase DATE+P Digit increase DATE- No digit increase DATE - P Digit increase  SECOND SECONDP  HOUR HOURP 1 character 32 characters PKEY Initial time No reception  PSTOP PSTOPP POFF...
Page 921 • Instructions available from function version B Instruction Condition/number of points processed Processing time (s) QnPH QnPRH  With auto refresh of CPU Refresh range: 2K words (0.5K words shared memory assigned equally to all CPUs) Refresh range: 4K words (1K words ...
Page 922 ■Table of the time to be added when file register, module access device or link direct device is used Device name Data Device specification Processing time (s) location QnCPU QnHCPU QnPHCPU QnPRHCPU File register (ZR) When standard RAM is Source 5.56 2.40 2.40...
Page 923: Operation Processing Time Of Universal Model Qcpu
Operation processing time of Universal model QCPU The processing time for the individual instructions are shown in the table on the following pages. Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time rather than as being strictly accurate.
Page 924 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic In conductive status 0.360 0.240 0.180 0.120 instruction In non-conductive status AND= When not executed 0.360 0.240 0.180 0.120 When In conductive status executed In non-conductive...
Page 925 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic LD< In conductive status 0.360 0.240 0.180 0.120 instruction In non-conductive status AND< When not executed 0.360 0.240 0.180 0.120 When In conductive status executed...
Page 926 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic LDD> In conductive status 0.360 0.240 0.180 0.120 instruction In non-conductive status ANDD> When not executed 0.360 0.240 0.180 0.120 When In conductive status executed...
Page 927 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic + (S) (D) When executed 0.360 0.240 0.180 0.120 instruction + (S1) (S2) (D) When executed 0.480 0.320 0.240 0.160 - (S) (D) When executed 0.360...
Page 928 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic Single (S)=0 0.300 0.220 0.180 0.140 instruction precision (S)=32766.5 0.300 0.220 0.180 0.140 DINT Single (S)=0 0.300 0.220 0.180 0.140 precision (S)=1234567890.3 0.300...
Page 929 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ROR (D) n 2.250 10.800 2.250 10.800 2.250 10.800 2.300 7.800 instruction n=15 2.250 10.800 2.350 10.800 2.350 10.800 2.400 7.800 RCR (D) n 2.250...
Page 930 • When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, and Q100UDEHCPU Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Sequence When executed 0.020 0.0095 0.0095...
Page 931 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic AND<> When not executed 0.060 0.0285 0.0285 0.0285 instruction When In conductive executed status In non-conductive status OR<>...
Page 932 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic OR< When not executed 0.060 0.0285 0.0285 0.0285 instruction When In conductive executed status In non-conductive status LD>= In conductive status...
Page 933 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic ANDD> When not executed 0.060 0.0285 0.0285 0.0285 instruction When In conductive executed status In non-conductive status ORD>...
Page 934 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic ORD>= When not executed 0.060 0.0285 0.0285 0.0285 instruction When In conductive executed status In non-conductive status + (S) (D) When executed...
Page 935 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic When executed 0.120 0.057 0.057 0.057 instruction DBCD When executed 0.200 0.095 0.095 0.095 When executed 0.060 0.0285 0.0285...
Page 936 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application WOR (S1) (S2) When executed 0.080 0.038 0.038 0.038 instruction DOR (S) (D) When executed 0.060 0.0285 0.0285...
Page 937 *1 Can be used only for the Q03UDCPU, Q04UDHCPU, and Q06UDHCPU whose first five digits of serial number is "10012" or later. *2 Can be used only for the Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q13UD(E)HCPU, and Q26UD(E)HCPU whose first five digits of serial number is "10102" or later. For the instructions for which a rising edge instruction (P) is not described, the processing time is the same as an ON execution instruction.
Page 938 • When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. Sequence When executed 0.0019 0.0078 0.0019 0.0078 0.0019 0.0078 instruction When executed 0.0058 0.015 0.0058 0.015...
Page 939 Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. Basic LD> In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023 instruction In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023 AND> When not executed 0.0078 0.023...
Page 940 Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. Basic OR>= When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023 instruction When In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023 executed In non-conductive 0.0098...
Page 941 Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. Basic ANDD<= When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023 instruction When In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023 executed In non-conductive 0.0098...
Page 942 Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. Basic D* (S1) (S2) (D) When executed 0.023 0.023 0.023 0.023 0.023 0.023 instruction D/ (S1) (S2) (D) When executed 0.033 0.054 0.033 0.054 0.033...
Page 943 Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. Basic  0.0058 0.015 0.0058 0.015 0.0058 0.015 instruction  DCML 0.0058 0.015 0.0058 0.015 0.0058 0.015 BMOV SM237=OFF 2.400 7.500 2.400 7.500 2.400 7.500...
Page 944 Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. Application WXNR (S) (D) When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023 instruction WXNR (S1) (S2) (D) When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031...
Page 945 ■Table of the time to be added when file register, extended data register, extended link register, and module access device are used • When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU Device name Data Device Addition time (s) specification Q00UJCPU Q00UCPU Q01UCPU Q02UCPU location...
Page 946 • When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, and Q100UDEHCPU Device name Data Device Addition time (s) specification Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, location Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU File register (R) When Source 0.100 0.048 0.048 0.048 standard Destination 0.100...
Page 947 • When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU Device name Data Device specification Addition time (s) location Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU File register (R) When the Source 0.074 0.043 0.043 extended SRAM Destination 0.023 0.023 0.023 cassette is not Word Source 0.074...
Page 948 ■Table of the time to be added when F/T(ST)/C device is used in OUT/SET/RST instruction • When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU Instruction Device Condition Addition time (s) name name Q00UJCPU Q00UCPU Q01UCPU Q02UCPU When not executed 2.900 2.900 2.900 2.100 When executed...
Page 949 • When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU Instruction Device Condition Addition time (s) name name Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. When not executed 1.100 3.900 1.100 3.900 1.100 3.900 When executed 15.000 49.000 15.000 49.000...
Page 950 Processing time of instructions other than subset instruction The following table shows the processing time of instructions other than subset instructions. • The processing time shown in "Table of the processing time of instructions other than subset instructions" applies when the device used in an instruction does not meet the device condition for subset processing. (For device condition that does not trigger subset processing, refer to Page 108 Subset processing.) For instructions not shown in the following table, refer to Page 921 Subset instruction processing time.
Page 951 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic LDE= Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.100 instruction precision In non-conductive status 4.400 20.900 4.400 20.900 4.400...
Page 952 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic LDE< Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 11.500 instruction precision In non-conductive status 4.400 20.900 4.400 20.900 4.400...
Page 953 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic LDED> Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 25.100 instruction precision In non-conductive status 4.700 37.400 4.700 37.400 4.700...
Page 954 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic LD$= In conductive status 8.300 38.500 8.300 38.500 8.300 38.500 5.500 14.900 instruction In non-conductive status 8.300 38.500 8.300 38.500 8.300 38.500 5.500...
Page 955 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic AND$<= When not executed 0.360 0.240 0.180 0.120 instruction When executed In conductive 7.100 36.500 7.100 36.500 7.100 36.500 6.000 16.000 status In non-...
Page 956 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic BKCMP< 15.300 36.100 15.300 36.100 15.300 36.100 8.300 23.000 instruction (S1) (S2) (D) n=96 66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.500 BKCMP>=...
Page 957 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic $+ (S) (D)  15.400 64.300 15.400 64.300 15.400 64.300 14.400 34.000 instruction  $+ (S1) (S2) 19.700 71.000 19.700 71.000 19.700 71.000...
Page 958 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic TTMR  5.300 20.900 5.300 20.900 5.300 20.900 3.900 6.100 instruction STMR  8.900 49.800 8.900 49.800 8.900 49.800 7.200 30.000 ROTC ...
Page 959 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ENCO (S) M1=ON 7.650 11.900 7.650 11.900 7.650 11.900 5.300 6.300 instruction (D) n M4=ON 7.500 11.700 7.500 11.700 7.500 11.700 5.200 6.200...
Page 960 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application EFCALL * Pn  105.000 214.000 105.000 214.000 105.000 214.000 76.200 134.000 instruction *: Program name  EFCALL * Pn 164.000 271.000 164.000...
Page 961 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application CCOM When selecting I/O refresh only 18.100 89.100 18.100 89.100 18.100 89.100 12.800 79.000 instruction When selecting CC-Link refresh only 33.300 132.000 33.300...
Page 962 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application DHABIN (S) (S)=1 6.800 18.200 6.800 18.200 6.800 18.200 6.000 8.500 instruction (S)=FFFFFFFFH 7.100 18.600 7.100 18.600 7.100 18.600 6.300 8.900 DABCD (S) (S)=1...
Page 963 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application RADD Double precision 5.200 43.100 5.200 43.100 5.200 43.100 4.100 16.400 instruction Single precision 3.200 11.500 3.200 11.500 3.200 11.500 2.500 4.700 DEGD...
Page 964 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application BTAN  12.100 33.700 12.100 33.700 12.100 33.700 9.000 17.000 instruction BASIN  13.300 32.800 13.300 32.800 13.300 32.800 12.200 15.100 BACOS ...
Page 965 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application LDDT< Comparison of In conductive 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400 instruction specified date status In non- 8.200 25.500 8.200 25.500...
Page 966 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ORDT>= When not executed 0.480 0.320 0.240 0.160 instruction Comparison of In conductive 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300 specified date status...
Page 967 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application LDDT<> Comparison of In conductive 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400 instruction specified date status In non- 8.200 25.500 8.200 25.500...
Page 968 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ORDT> When not executed 0.480 0.320 0.240 0.160 instruction Comparison of In conductive 8.200 25.500 8.200 25.500 8.200 25.500 7.400 23.300 specified date status...
Page 969 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ANDTM< When not executed 0.480 0.320 0.240 0.160 instruction Comparison of In conductive 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000 specified clock status...
Page 970 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ANDTM= When not executed 0.480 0.320 0.240 0.160 instruction Comparison of In conductive 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000 specified clock status...
Page 971 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application LDTM> Comparison of In conductive 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300 instruction specified clock status In non- 8.200 25.500 8.200 25.500...
Page 972 Category Instruction Condition (device) Processing time (s) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Application RBMOV (S) When standard RAM 1 point   12.200 34.900 12.200 34.900 9.400 31.300 instruction (D) n is used 1000 points ...
Page 973 • When using Q03UD(E)HCPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, and Q100UDEHCPU Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max.  Sequence 0.020 0.0095 0.0095 0.0095...
Page 974 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic ORE<> Single When not executed 0.060 0.0285 0.0285 0.0285 instruction precision When In conductive 3.600 6.000 3.300 5.500...
Page 975 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic LDE>= Single In conductive status 3.800 6.000 3.300 5.500 0.0285 0.0285 instruction precision In non-conductive status 3.800 5.900 3.400...
Page 976 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic ANDED> Double When not executed 0.060 0.0285 0.0285 0.0285 instruction precision When In conductive 3.800 7.700 3.300 7.300...
Page 977 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic ORED>= Double When not executed 0.060 0.0285 0.0285 0.0285 instruction precision When In conductive 4.100 9.600 3.700 9.200...
Page 978 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic LD$<= In conductive status 5.000 6.300 4.400 5.700 4.400 5.700 4.400 5.700 instruction In non-conductive status 4.800 6.400 4.200...
Page 979 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic BKCMP> 8.200 10.800 7.500 10.100 7.500 10.100 7.500 10.100 instruction (S1) (S2) (D) n=96 59.500 63.400 47.700 50.500...
Page 980 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic BK- (S1) (S2) 9.700 12.000 8.900 11.300 8.900 11.300 8.900 11.300 instruction (D) n n=96 61.300 63.600 45.600...
Page 981 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Basic RFS X n 4.200 5.900 3.700 5.600 3.700 5.600 3.700 5.600 instruction n=96 11.400 13.800 10.700 12.400 10.700...
Page 982 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application BKAND (S1) 9.000 11.700 8.300 11.000 8.300 11.000 8.300 11.000 instruction (S2) (D) n n=96 57.400 63.100 43.800...
Page 983 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application UNI (S) (D) n 5.000 5.300 3.500 4.800 3.500 4.800 3.500 4.800 instruction 5.600 6.000 4.000 5.100 4.000...
Page 984 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max.  Application XCALL 3.800 5.700 3.700 5.200 3.700 5.200 3.700 5.200 instruction When selecting I/O refresh only 12.800 29.100 12.400...
Page 985 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. No display  no display Application LEDR 2.400 2.600 1.900 2.000 1.900 2.000 1.900 2.000 instruction LED instruction execution ...
Page 986 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ANDTM= When not executed 0.008 0.038 0.038 0.038 instruction Comparison of In conductive 7.000 11.500 6.300 10.800 6.300...
Page 987 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ORTM<> When not executed 0.008 0.038 0.038 0.038 instruction Comparison of In conductive 7.300 11.500 6.600 10.800 6.600...
Page 988 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application LDTM<= Comparison of In conductive 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800 instruction specified clock status In non- 7.300...
Page 989 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ANDTM< When not executed 0.008 0.038 0.038 0.038 instruction Comparison of In conductive 7.000 11.500 6.300 10.800 6.300...
Page 990 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ORTM>= When not executed 0.008 0.038 0.038 0.038 instruction Comparison of In conductive 7.300 11.500 6.600 10.800 6.600...
Page 991 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application LDDT<> Comparison of In conductive 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900 instruction specified date status In non- 7.400...
Page 992 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ANDDT> When not executed 0.008 0.038 0.038 0.038 instruction Comparison of In conductive 7.200 11.400 6.500 10.700 6.500...
Page 993 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application ORDT<= When not executed 0.008 0.038 0.038 0.038 instruction Comparison of In conductive 7.400 11.500 6.700 10.800 6.700...
Page 994 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application LDDT>= Comparison of In conductive 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900 instruction specified date status In non- 7.400...
Page 995 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application INSTR No match 19.300 21.800 16.600 18.400 16.600 18.400 16.600 18.400 instruction Match Head 10.300 12.800 9.100 10.900...
Page 996 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application POW (S1) Single (S1)=12.3E+5 8.750 11.400 8.400 10.900 8.400 10.900 8.400 10.900 instruction (S2) (D) precision (S2)=3.45E+0 POWD (S1)
Page 997 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Application QCDSET SRAM card to standard ROM 306.000 346.000 305.000 346.000 305.000 346.000 305.000 346.000 instruction Standard ROM to SRAM card 311.000 342.000...
Page 998 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Data link S.ZCOM When mounting CC-Link module 19.600 26.500 19.300 26.000 19.300 26.000 19.300 26.000 instruction (master station side) When mounting CC-Link module 19.600...
Page 999 Category Instruction Condition (device) Processing time (s) Q03UD(E)CPU Q04UD(E)HCPU, Q10UD(E)HCPU, Q50UDEHCPU, Q06UD(E)HCPU Q13UD(E)HCPU, Q100UDEHCPU Q20UD(E)HCPU, Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Min. Max. Multiple S.TO n1 n2 Writing to host CPU n4=1 34.700 34.900 33.500 34.400 33.500 34.400 33.500 34.400 n3 n4 (D) shared memory...
Page 1000 • When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max.  Sequence 0.0019 0.0078 0.0019 0.0078 0.0019 0.0078 instruction When not executed 0.0019 0.0078 0.0019 0.0078...
Page 1001 Category Instruction Condition (device) Processing time (s) Q03UDVCPU Q04UDVCPU Q06UDVCPU, Q13UDVCPU, Q26UDVCPU Min. Max. Min. Max. Min. Max. Basic LDE> Single In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023 instruction precision In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023 ANDE>...

Mitsubishi Electric MELSEC-Q/L Programming Manual

Chapter 1 General Description

Chapter 2 Instruction Tables

Chapter 3 Configuration of Instructions

Chapter 4 How to Read Instructions

Chapter 5 Sequence Instructions

CHAPTER 6 Basic Instructions

Chapter 7 Application Instructions

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Summary of Contents for Mitsubishi Electric MELSEC-Q/L