Lc4256V-75Tn100 Cp (X6046B00) Cpld(Mel) - Yamaha TYROS 2 Service Manual

Tyros2
LC4256V-75TN100 CP (X6046B00) CPLD (MEL)
PinNo. NAME
GND
1
2 TDI
DGA_AUDIO_IN
3
I/O
4
DGA_OUT
5
I/O
6
GND
7
I/O
8
9 IDERD_O
IDEWR_O
10
11 IDEMACK_O
CLOCK_INPUT
12
13 VCCO
DMACLR
14
15 I/O
I/O
16
17 I/O
GND
18
19 HDIRQ
XHDIRQ
20
21 I/O
I/O
22
23 FS64DGA
TCK
24
25 VCC
GND
26
27 I
I/O
28
29 I/O
I/O
30
31 I/O
GND
32
33 VCCO
I/O
34
35 I/O
I/O
36
37 I/O
CK512
38
39 FS128
I/O
40
41 I/O
I/O
42
43 I/O
I/O
44
45 VCCO
GND
46
47 I/O
I/O
48
I/O
49
I/O
50
32
I/O FUNCTION/CONNECTION
DGND
-
for CPLD data writing (JTAG pin)
I
Digital audio signal output
O
(to +3.3V )
D
Digital audio signal input
I
(to +3.3V )
D
DGND
-
(to +3.3V )
D
IDE READ signal (active-low)
I
I IDE WRITE signal (active-low)
DMA ACKNOWLEDGE signal (active-low)
I
I DMA REQUEST signal(active-low)
Power supply +3.3V
-
D
I DMA CLEAR signal (active-low)
(to +3.3V )
D
- DGND
INTERRUPT signal (HDD to CPU) (active-high)
I
O INTERRUPT signal (HDD to CPU) (active-low)
(to +3.3V )
D
Bit clock for data between DGA and MAT
I
I Clock for CPLD data communication (JTAG pin)
Power supply +3.3V
D
- DGND
(to +3.3V )
D
- DGND
Power supply +3.3V
-
D
(to +3.3V )
D
I Master clock (22.5792KHz)
Bit clock for data between SWP50 and MAT (11.2894MHz)
I
(to +3.3V )
D
Power supply +3.3V
-
D
DGND
-
(to +3.3V )
D
PinNo. NAME I/O
51
-
GND
52
TMS
53
O
MELO_0
54
I/O
55
O
MELO_2
56
MELI_0 I
57
-
GND
58
I/O
59
I/O
60
I/O
61
I/O
62
I
63 -
VCCO
64
I/O
65
I/O
66
I/O
67 O
DGAMCLK
68
GND -
69 O
DGAWCLK
70
I/O
71 O
IDEMARQ512D
72
DMAERR O
73 I
I
74
TDD O
75 -
VCCO
76
GND
77
I
78
I/O
79 O
WCLK1
80
I/O
81 O
WCLK0
82
GND -
83 -
VCCO
84
ADLR O
85
I/O
86
FS640UT O
87
I/O/GOE1
88
FS I
89 I
FS256
90
VCCO -
91
I/O/GOE0
92
I/O
93
I/O
94
I/O
95 -
VCCO
96
-
GND
97
I/O
98
I/O
99
I/O
100
O
IDMARQ_0512HDL
DM:IC53
FUNCTION/CONNECTION
DGND
for CPLD data communication (JTAG pin)
Data for Playback tracks1 and 2
(to +3.3V )
D
Data for PLAYBACK tracks 3 and 4
Data for RECORD tracks 1 and 2
DGND
(to +3.3V )
D
Power supply +3.3V
D
(to +3.3V )
D
System master clock (22.5792MHz)
DGND
System word clock (44.1kHz)
(to +3.3V )
D
IDE DMA request
(Not used)
(to DGND)
for CPLD data communication
Power supply +3.3V
D
DGND
(to +3.3V )
D
(to DGND)
Word clock for DAC (Not used)
(to DGND)
Word clock for DAC (Not used)
DGND
Power supply +3.3V
D
LR signal for DAC (Not used)
(to DGND)
Maste clock for DAC (Not used)
(to DGND)
Sampling frequency (44.1kHz)
256FS (11.2896MHz)
Powe supply +3.3V
D
(to +3.3V )
D
Power supply +3.3V
D
Ground
(to +3.3V )
D
Output in case that the DMA request
signal is negated by the rising or falling
edge of 512FS. (Not used.)
MO
TR
OWNE
BEDIE
MODE