Bus Architecture - Commodore C-128 Service Manual

BUS ARCHITECTURE
FOLD OUT SCHEMATIC PAGES 64-67 FOR EASY REFERENCE.
The Processor Bus
The Processor Bus is the data and address buses that are directly connected to the 8502 processor.
These buses are designated DO - 07 for the eight bit data bus and AO -A 15 for the sixteen bit address
bus. These buses tie the processor to most of the system ROM and 1/0 devices, including at least
part of all System ROM, all built-in Function ROM, the MMU, the PLA, the 8563 Video Processor,
the SID, and both CIA chips.
The Processor Bus is in direct communication with the Z-80 co-processor as well. All address lines
are shared directly by both processors. In order to allow the Z-80 to operate on a 6502 family bus,
it is necessary to latch data going into the Z-80 and gate the data leaving the Z-80. Thus, the Z-80
has a small local data bus, designated ZOO -ZD7. During a write cycle, when AEC is high, Z-80 data
is gated to the Processor Bus. During a read cycle, Processor Bus data is gated to the Z-80 data bus.
This read data is transparently latched by the 1 MHz system clock.
The read and write cycles referred to are, unless otherwise specified, 8502 type bus cycles. The
Z-80 Read Enable and Write Enable outputs are conditioned using logic to interface with an 8502
bus cycle, so no distinction is made as to the differences between cycles of the different processors.
As mentioned above, the Z-80 is not in direct communication with the Processor Data Bus, due
to the necessity of adapting the Z-80 to 8502 bus protocol. Note, however, that every other device
and the translated bus (except two that will be explained later) shares the Processor Data Bus as a
common data bus.
The Translated Address Bus
Another C 128 system bus is the Translated Address Bus, which is produced by the MMU during
AEC high. This bus consists of only high order addressing lines, designated TAS - TA15. These lines
reflect the action of the MMU on the normal high order address lines, which mayor may not include
some sort of translation. The MMU can translate the address of page zero or page one in normal opera-
tion, and it translates the Z-80 address from $0000 thru $OFFF in order to direct it to read the Z-80
BIOS. A more complete description of MMU translations can be found in the MMU section. Normally
the Translated Address Bus indirectly drives the DRAMs and the VIC chip by driving the Multiplexed
Address Buses. It directly drives System ROM 4 address line 12 to allow the Z-80 ROM relocation.
Finally, this bus becomes address lines S thru 15 of the C64 compatible expansion port.
During a VIC cycle or a DMA, the MMU pulls TA12 - TA15 high, while TAS - TA1l are tri-stated.
This allows the VIC chip to drive T AS - T A 11 as VIC addresses VAS - VA 11.
The Multiplexed Address Bus
This section actually describes two related address buses, the Multiplexed Address Bus and the
VIC Multiplexed Address Bus, known respectively as MAO - MA 7 and VMAO - VMA 7. The VIC
Multiplexed Address Bus is created during AEC high by multiplexing the high order Translated Ad-
dress Bus
(T
AS - TA15) with the low order Processor Address Bus (AO - A7), controlled via the MUX
signal. This bus, driven though series resistors, is called the Multiplexed Address bus. The VIC Multi-
plexed Address Bus is used in addressing the VIC chip registers while the Multiplexed Address Bus
is the processor's DRAM address for both 64K banks of DRAM.
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