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SAA7324 – DECODER, DIGITAL SERVO IC AND D/A-CONVERTER CD10 (low voltage version)
Pin
Name
Direction
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
→ CD10
1
HFREF
→ CD10
2
HFIN
CD10 →
3
ISLICE
4
VSSA1
GND
5
VDDA1
+3
CD10 →
6
IREF
CD10 →
7
VRIN
HF-preamp → CD10
8
D1
HF-preamp → CD10
9
D2
HF-preamp → CD10
10
D3
HF-preamp → CD10
11
D4
HF-preamp → CD10
12
R1
HF-preamp → CD10
13
R2
14
VSSA2
GND
CD10 → X-TAL
15
CROUT
X-TAL → CD10
16
CRIN
17
VDDA2
+3
CD10 →
18
LN
CD10 →
19
LP
→ CD10
20
VNEG
→ CD10
21
VPOS
CD10 →
22
RN
CD10 →
23
RP
24
SELPLL
+3
25
TEST1
GND
CD10 →
26
CL16
CD10 →
27
DATA
CD10 →
28
WCLK
CD10 →
29
SCLK
CD10 →
30
EF
31
TEST2
GND
CD10 →
32
KILL
33
VSSD1
GND
CD10 ↔
34
V2/V3
→ CD10
35
WCLI
→ CD10
36
SDI
→ CD10
37
SCLI
µP → CD10
38
RESETn
µP ↔ CD10
39
SDA
µP → CD10
40
SCL
→ CD10
41
RAB
µP → CD10
42
SILD
CD10 →
43
STATUS
44
TEST3
GND
→ CD10
45
RCK
CD10 →
46
SUB
CD10 →
47
SFSY
CD10 →
48
SBSY
CD10 →
49
CL11/4
50
VSSD2
GND
CD10 →
51
DOBM
52
VDDD1P
+3
CD10 →
53
CFLG
CD10 → servo driver
54
RA
CD10 → servo driver
55
FO
CD10 → servo driver
56
SL
57
VDDD2C
+3
58
VSSD3
GND
CD10 → servo driver
59
MOTO1
CD10 →
60
MOTO2
CD10 →
61
V4
CD10 → HF-gain switch
62
V5
inner switch → CD10
63
V1
CD10 → HF-preamp
64
LDON
CS 46 647
3-2
Description
comparator common mode input
comparator signal input
current feedback from data slicer
analog ground 1
analog supply voltage 1
reference current output pin
reference voltage for servo ADC's
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (satellite diode signal input)
unipolar current input (satellite diode signal input)
analog ground 2
crystal/resonator output
crystal/resonator input
analog supply voltage 2
DAC left channel differential output - negative
DAC left channel differential output - positive
DAC negative reference input
DAC positive reference input
DAC right channel differential output - negative
DAC right channel differential output - positive
selects whether internal clock multiplier PLL is used
test control input 1; this pin should be tied low
16.9344 MHz system clock output
serial data output (3-state)
word clock output (3-state)
serial bit clock output (3-state)
C2 error flag output (3-state)
test control input 2; this pin should be tied low
kill output (programmable; open-drain)
digital ground 2
versatile I/O: input versatile pin 2 or output versatile pin 3 (open-drain)
word clock input (for data loopback to DAC)
serial data input (for data loopback to DAC)
serial bit clock input (for data loopback to DAC)
power-on reset input (active low)
microcontroller interface data I/O line (open-drain output)
microcontroller interface clock line input
microcontroller interface R/W and load control line input (4-wire bus mode)
microcontroller interface R/W and load control line input (4-wire bus mode)
servo interrupt request line/decoder status register output (open-drain)
test control input 3; this pin should be tied low
subcode clock input
P-to-W subcode bits output (3-state)
subcode frame sync output (3-state)
subcode block sync output (3-state)
11.2896 MHz or 4.2336 MHz (for microcontroller) clock output
digital ground 3
bi-phase mark output (externally buffered; 3-state)
digital supply voltage 2 for periphery
correction flag output (open-drain)
radial actuator output
focus actuator output
slide control output
digital supply voltage 3 for core
digital ground 4
motor output 1; versatile (3-state)
motor output 2; versatile (3-state)
versatile output pin 4
versatile output pin 5
versatile input pin 1
laser drive on output (open-drain)
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