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9 - 5
COMBI BOARD - CIRCUIT DIAGRAM
PART 5
+VDD_3
0R
3640
3634
3634A opt
Bead&
3633A opt
ROMWRb
3628
0R
+VDD_EP
2640
100n
7640
C_A7
P26
5
29
A7
A14
C_A6
P25
6
28
A6
A13
C_A5
P20
7
27
A5
A8
C_A4
AT27LV010A
P21
8
26
A4
A9
C_A3
P23
9
25
A3
A11
C_A2
PSEN
10
24
A2
OE#
C_A1
P22
11
23
A1
A10
C_A0
12
22
A0
CE#
P00
P07
13
21
DQ0
DQ7
+VDD_M
+VDD_M
3641
7641
Bead&
1
54
VDD1
VSS1
M_D0
M_D15
2641
2
53
DQ0
DQ15
3
52
VDDQ1
VSSQ3
10u/50
M_D1
M_D14
4
51
DQ1
DQ14
M_D2
M_D13
2642
5
50
DQ2
DQ13
100n
6
49
VSSQ1
VDDQ3
M_D3
M_D12
2643
7
48
DQ3
DQ12
M_D4
M_D11
100n
8
47
DQ4
DQ11
2644
9
46
VDDQ2
VSSQ4
M_D5
M_D10
100n
10
45
DQ5
DQ10
M_D6
M_D9
2645
11
44
DQ6
DQ9
100n
12
43
VSSQ2
VDDQ4
M_D7
M_D8
13
42
DQ7
DQ8
14
41
VDD2
VSS2
15
40
LDQM
NC
M_WE
M_CLKR
16
39
WE
UDQM
M_CAS
M_CLK
17
38
CAS
CLK
M_RAS
M_CKE
18
37
5659
Bead_120Z
RAS
CKE
M_CS
19
36
CS
NC/A12
M_BA0
M_A11
20
35
BA0
A11
M_BA1
M_A9
21
34
BA1
A9
M_A10
M_A8
22
33
A10/AP
A8
M_A7
M_A0
23
32
A0
A7
M_A1
M_A6
24
31
A1
A6
M_A2
M_A5
25
30
A2
A5
M_A3
M_A4
26
29
A3
A4
27
28
VDD3
VSS3
2697
100n
IS42S16400A-7T
+VDD_3
+VDD_M
10u/50
M_CAS
3642 100K
3643 10K
M_CS
2609
M_A6
3644 opt
3645 10K
3646 opt
M_A5
3647 10K
M_A4
3648A opt
3649 10K
3650 10K
M_A3
3651 10K
M_A2
M_A1
3652 10K
3653 opt
3654 10K
M_A0
+TU
IOTRAP8
0 : CPU Clock is from PLL
M_CAS
1 : CPU clock is from crystal
IOTRAP7
0 : 8-bit address mode
1 : 16-bit address mode (this
M_CS
mode can save latch circuit)
USB phase-lock-loop input clock source.
3'b000 : 6MHz CRYSTAL
IOTRAP
3'b001 : 12MHz CRYSTAL
3'b010 : 16.9MHz CRYSTAL
[6:4]
3'b011 : 24MHz CRYSTAL
M_A[6:4]
3'b100 : 33.868MHz CRYSTAL
Other: disable the USB phase lock loop and
a 48MHz crystal is connected to the
IOTRAP3
0 : USE BUILD-IN USB TRANSCEIVER
PU8591.
M_A3
1 : USE EXTERNAL USB TRANSCEIVER
IOTRAP2
0 : NORMAL RESET(10ms)
M_A2
1 : FAST RESET(32 CRYSTAL CLOCK)
IOTRAP1
0 : USE INTERNAL ROM
M_A1
1 : USE EXTERNAL ROM
IOTRAP0
0 : USE INTERNAL CPU
M_A0
1 : USE EXTERNAL CPU
Ver0.5: 1. Use SPCA758 P30 (Pin76) for TAPE PAUSE Key.
2. Add Pull-up RES 100K for TAPE PAUSE Key.
+VDD_3
UI[2..0]
UI[2..0]
GPIO[3..0]
GPIO[3..0]
REC_DET#
3614
100K
3685
47K
AF_MUTE
+VDD_3
+VDD25
2601
2611
100n
100n
2602
2612
100n
100n
2603
2613
100n
100n
2604
2614
100n
100n
+VDD_3
ROMWRb
7600
+VDD_3
P21
97
P21
P20
98
P20
C_A7
99
P0AL7
C_A6
100
P0AL6
C_A5
101
P0AL5
C_A4
102
P0AL4
C_A3
103
P0AL3
C_A2
104
P0AL2
C_A1
105
P0AL1
C_A0
106
P0AL0
P22
107
P22
108
+VDD_3
VDDIO
109
VSS
110
+VDD25
VDD
P00
111
P00
P01
112
SPCA758B
P01
P02
113
P02
P03
114
P03
P04
115
P04
P05
116
P05
P06
+VCC_ADC
117
P06
2607
P07
118
P07
PSEN
119
10u/50
PSEN
A_BCK
120
AUD_BCK
A_DATA
121
2606
AUD_DATA
A_LRCK
122
100n
AUD_LRCK
A_XCK
AGND_A
123
AUD_XCKOUT
SYS_RST
124
RESET
125
VDDADC
AMPI
126
AMPI
AGC
127
AGC
AMPO
128
AMPO
+
AGND_A
MIC_IN
2620
MICP
10n
MICN
2621
10n
2622
+VDD25
AGND_A
10u/50
2623
CMB
100n
MICO
3620
51K
2624
AGND_A
3621
100K
1u
2626
MIC_OUT
KEY[2..0]
2625
390p
1u
KEY[2..0]
+VCC_ADC
TP54
5682
Bead
12
TP53
5681
Bead
MIC_IN
11
TP52
5680
Bead
10
TP51
5679
Bead
KEY2
9
TP50
5678
Bead
KEY1
8
TP49
5677
Bead
KEY0
7
TP48
5676
Bead
+VDD_UI
6
TP47
5675
Bead
UI_STB
5
TP46
5674
Bead
4
TP45
5673
Bead
UI_CLK
3
TP44
5672
Bead
UI_DATA
2
TP43
5671
Bead
1
1670
FFC_1.25mm_12P
AGND_A
+VDD_3
+VDD_3
1610
3612
5611 0R
TP07
1
100K
5610 0R
TP08
2
DOOR_SW
DIPMATE_2.5mm_2P
PAUSE#
T640
PAUSE#
T641
MCU_SCL
P31
MCU_SDA
CD_SUB
CD_RCK
CD_SFSY
CD_STATUS
CD_DET#
CD_RESET
+VDD25
2618
33R
3618
20p
1619
6MHz
2619
100R
3617
20p
CD_EF
+VDD_PLL
64
VSSAUD
2615
63
100n
VDDPLL
62
VSSPLL
61
VDDUSB
60
DP
+VDD_USB
59
DM
58
VSSUSB
57
YFCLK
AUD_XCKIN
56
AUD_XCKIN
YFLAG
55
YFLAG
I2S_BCLK
54
CD_BCLK
53
CD_C2PO
I2S_DATA
52
CD_DATA
I2S_LRCK
51
CD_LRCK
50
VDD
+VDD25
49
VSS
48
+VDD_3
VDDIO
M_D15
47
DRAMD15
M_D14
46
DRAMD14
M_D13
45
DRAMD13
M_D12
44
DRAMD12
M_D11
43
DRAMD11
M_D10
42
DRAMD10
M_D9
41
DRAMD9
M_D8
40
DRAMD8
M_D0
39
DRAMD0
M_D1
38
DRAMD1
M_D2
37
DRAMD2
M_D3
36
DRAMD3
M_D4
35
DRAMD4
M_D5
34
DRAMD5
M_D6
33
DRAMD6
+VDD_3
3638
10K
3637 3K3
470n
2635
3636
470K
CD_EF
3635
10K
BAS316
+VDD_3
6636
C2FEN
1N4148
6635
DE_EMPH
A_XCK
3669 220R
7660
WM8714
A_LRCK
3662 100R
1
14
LRCIN
SCKI
+VCC_DAC
A_DATA
3661 100R
2
13
DIN
FORMAT
A_BCK
3668 100R
3
12
BCKIN
DEEMPH
4
11
NC1
NC2
2662
2661 220u/16
5
10
CAP
MUTE
6
9
10u/50
VOUTR
VOUTL
2660
7
8
GND
VDD
100n
AGND_D
2663
2664
+
+
AGND_D
10u/50
10u/50
AGND_D
3663
3664
10R
10R
5663
5664 10uH&
10uH&
CD_L
CD_R
9 - 5
MCU_SCL
T610
CD_SUB
T626
T601
MCU_SCL
CD_SUB
+VCC3
MCU_SDA
CD_RCK
T611
T627
MCU_SDA
CD_RCK
CD_SFSY
T628
T602
UI_CLK
T612
CD_SFSY
+VCC5
CD_STATUS
UI_CLK
T629
UI_STB
T613
CD_STATUS
UI_STB
T603
UI_DATA
T614
+VCC25
UI_DATA
T600
SELECT
3616
0R
3615
0R
CD_DET#
T620
DGND
CD_DET#
T_ON
T619
T_ON
REC_DET#
CD_RESET
T618
T624
REC_DET#
CD_RESET
AF_MUTE
CD_EF
T617
T625
AF_MUTE
CD_EF
MULTI_A0
DE_EMPH
T615
T623
MULTI_A0
DE_EMPH
MULTI_A1
T616
MULTI_A1
7680
74LVC157
CD_SCLK
3681
100R
I2S_BCLK
2
4
I0A
ZA
ADC_BCLK
3682
1K
AUD_XCKIN
3
7
I1A
ZB
CD_CLK16
3683
100R
I2S_LRCK
5
12
I0B
ZC
ADC_CLK6
3684
100R
I2S_DATA
6
9
I1B
ZD
CD_WCLK
14
I0C
ADC_LRC
13
I1C
CD_DATA
11
I0D
ADC_DATA
10
I1D
SELECT
1
S
15
E
+VCC_3
5603
16
VCC
Bead&
2680
100n
CD_CLK16
AUD_XCKIN
T681
T631
CD_CLK16
AUD_XCKIN
T682
CD_WCLK
I2S_LRCK
T632
CD_WCLK
I2S_LRCK
CD_SCLK
I2S_BCLK
T683
T633
CD_SCLK
I2S_BCLK
T684
CD_DATA
I2S_DATA
T634
CD_DATA
I2S_DATA
T685
ADC_CLK6
ADC_CLK6
ADC_LRC
T686
ADC_LRC
T687
ADC_BCLK
ADC_BCLK
ADC_DATA
T688
ADC_DATA
SELECT
T680
SELECT
On this version 0.4 PCB
+VDD_3
+VDD_UI
+VCC3
+VDD_3
3600, 3603, 3640, 3641 and 3660
3600
3602
0R&
Bead&
are RES , now change to BEAD,
Next version
+VDD_3
+VDD_USB
+VCC25
+VDD25
be modified.
3606
0R&
3601
0R&
On this version 0.4 PCB
+VCC3
+VCC_DAC
+VDD25
+VDD_PLL
5610 and 5611
3604
5602
Bead&
change to RES,
opt
2610
+VDD_3
+
the
label
should be modified.
10u/50
3660
Bead&
+VCC3
+VCC_ADC
opt
5601
+VDD_3
3603
Bead&
+VCC3
MIC_OUT
T606
MIC_OUT
T605
+VCC5
AGND_M
AGND_A
+VCC25
CD_L
T607
CD_L
CD_R
T608
CD_R
T609
AGND_D
AGND_D
+MW
T604
+MW
+TU
Layout,
the
label
should
Layout,
are BEAD, now
Next version
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