Sony SDP-EP9ES Service Manual page 38

Pin No. Pin Name
TSTIN6
76
77 TSTIN7
MUTI
78
79 VDD
GND
80
81 DOUT
DIN
82
83 XSEL
PSEL
84
85 EPCK
EYEI
86
87 EYEQ
BTR
88
89 ELB
C9M
90
91 TSTIN8
GND
92
93 IDST
IDCK
94
IDO
95
96 WINGT
SYST0
97
98 SYST1
ADST0
99
100 ADST1
I/O
I
For testing IC (Fixed at "L")
I
I Muting input. Muted at "H"
–
Power supply (+5V)
– Ground
O
QPSK inverted output (Not used)
I QPSK signal input
I
Crystal select. Used at "H" (Fixed at "H")
I PLL select. Used at "L" (Fixed at "L")
O
QPSK eye pattern clock. 288 kHz (Not used)
O Eye pattern output. I phase (Not used)
O
Eye pattern output. Q phase (Not used)
O
Not used
O
O 9.216 MHz (Not used)
I
For testing IC (Not used)
– Ground
O
Signal indicating ID start position (Not used)
ID signal sample clock
O
Data changes at falling edge of clock. 576 kHz (Not used)
O ID data output (MSB first) (Not used)
O
"L" while searching for sync signal of correction block (Not used)
O
Displays lock state of sync signal of correction block (Not used)
O
O
Displays continuous state of ID address of correction block (Not used)
O
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Function Function