1. Manuals
  2. Brands
  3. Conexant Manuals
  4. Media Converter
  5. Fusion 878A
  6. Manual

Conexant Fusion 878A Manual

Pci video decoder
Hide thumbs
Table of Contents

Advertisement

Quick Links

Fusion™ 878A
PCI Video Decoder
The Fusion 878A is a complete, low cost, single-chip solution for analog
broadcast signal capture on the PCI bus. The Fusion 878A takes advantage
of the PCI-based system's high bandwidth and inherent multimedia
capability. It is designed to be interoperable with any other PCI multimedia
device at the component or board level.
The Fusion 878A has all the video and audio capture features of the
Bt878, plus a whole lot more. Designed to address the demanding
requirements of the Personal Computing and digital video industry, Fusion
878A meets PC98/PC99 requirements as well as being fully PCI 2.2
compliant. Fusion 878A addresses the current analog PC TV requirements
since it is pin for pin compatible and software compatible with the current
Bt878. But, Fusion 878A can also be used in an array of MPEG digital
transport stream products as well. The world is turning digital, with new
standards in Television – ATSC and COFDM – and Television recording
technologies using MPEG compression. Fusion 878A can be used as the hub
into the PC connecting the multiple analog and digital video formats in the
PC via a single PCI connection.
Functional Block Diagram
Composite 1
Composite 2
40 MHz
Composite 3
ADC
Composite 4
Composite S-Video (Y)
40 MHz
S-Video (C)
ADC
2
I
S (dig. audio)
TV
FM
Mic
879A_001
Data Sheet
GPIO and Digital/Video Port
Pixel
Format
Conversion
GPIO
Video FIFO
DMA
Controller
Video
Decode
and Scaling
DMA
Controller
Ultralock™
and Clock
Generation
Audio FIFO
Audio
Stream
Format
Input
High BW
Gain
Audio
Control
ADC
Distinguishing Features
• NTSC/PAL/SECAM video decoding
• Supports capture resolutions up to 768 x 576 (full
PAL)
• On-chip PCI bus mastering and bridge
functionality
• Supports HDTV/audio/MPEG2 transport data
across PCI bus
• High-speed serial port support MPEG transport
stream up to rates of 40 Mbps
• High-speed parallel port supports MPEG transport
streams up to 20 Mbps
• Flexible 24-bit wide GPIO
• CCIR656 interface
• Interfaces to a Digital TV data stream from a VSB
or OFDM demodulator
• Multiple YCrCb and RGB pixel formats and YUV
planar formats supported on output
• Selectable pixel density: 8, 16, 24, and 32 bits per
pixel
• Performs complex clipping of video source and
VGA video overlay
• Permits different program control and color
space/scaling for even and odd fields
• Executes Windows 98 "Scatter and Gather"
• Integrates advanced chroma and luma comb
filters/scalers
• Image scaleable in X and Y direction
• Y/C, 6-tap luma/2-tap chroma polyphase filter
• Receives Digital audio via I2S serial port
• Includes VBI data capture (closed captioning,
teletext, and Intercast data decoding)
• 100% PCI Rev. 2.2 compliant
• PC 98/PC 99 compliant
2
I
C
• WHQL-certifiable
• Accepts Mono audio input
• Packaged in compact 128-pin plastic QFP
Target
Fusion 878A Specific Features
Initiator
• Full stereo decoding for both TV audio (BTSC) and
PCI
PCI I/F
FM radio
Bus
• Enhanced GPIO/I
Target
• ACPI support
Initiator
• Byte alignment
• Vital product data
• High speed serial port
• High speed parallel port
Applications
• PC television
• Digital television
• Digital VCR
• Desktop video phone
• Still frame capture
• VBI data service capture
2
S
100600B
December 3, 1999

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Fusion 878A and is the answer not in the manual?

Questions and answers

Summary of Contents for Conexant Fusion 878A

  • Page 1 • Interfaces to a Digital TV data stream from a VSB or OFDM demodulator Bt878. But, Fusion 878A can also be used in an array of MPEG digital • Multiple YCrCb and RGB pixel formats and YUV transport stream products as well. The world is turning digital, with new planar formats supported on output standards in Television –...

  • Page 2: Ordering Information

    Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents, copyrights, or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    Y/C Separation and Chroma Demodulation ........2-4 Conexant...
  • Page 4 Fusion 878A Table of Contents PCI Video Decoder Video Scaling, Cropping, and Temporal Decimation ....... . . 2-7 Down-Scaling .
  • Page 5 GPIO Modes in Fusion 878A ........
  • Page 6 Fusion 878A Table of Contents PCI Video Decoder I2C Serial EEPROM Interface ..........3-23 EEPROM Address Mapping .
  • Page 7 Fusion 878A Table of Contents PCI Video Decoder MSB Cropping Register) ..........5-11 0x00C—Even Field (E_CROP)
  • Page 8 Fusion 878A Table of Contents PCI Video Decoder 0x0B4—Total Line Count Register (VTOTAL_HI) ......5-27 0x0D4—Color Format Register (COLOR_FMT) .

  • Page 9: List Of Figures

    Fusion 878A Detailed Block Diagram........
  • Page 10 Fusion 878A List of Figures PCI Video Decoder Figure 3-8. GPIO SPI Input Mode ........... . 3-12 Figure 3-9.
  • Page 11 Video Input Formats Supported by the Fusion 878A ....... 2-3...
  • Page 12 Fusion 878A List of Tables PCI Video Decoder Conexant 100600B...

  • Page 13: Product Overview

    The audio function features a completely independent DMA/PCI bus master for FM radio or TV sound capture. The Fusion 878A is based on the Bt848A video capture chip. The Fusion 878A is a Bt848A upgraded to include various audio capture capabilities. The...

  • Page 14: Figure 1-1. Fusion 878A Detailed Block Diagram

    Fusion 878A 1.0 Product Overview 1.1 Functional Overview PCI Video Decoder Figure 1-1. Fusion 878A Detailed Block Diagram Digital Audio DMA Controller PCI Initiator Address Generator Analog Audio FIFO FIFO Data MUX Audio 35x36 Decoder Instruction Queue I 2 S...

  • Page 15: Figure 1-2. Fusion 878A Audio/Video Decoder And Scaler Block Diagram

    Fusion 878A 1.0 Product Overview PCI Video Decoder 1.1 Functional Overview Figure 1-2. Fusion 878A Audio/Video Decoder and Scaler Block Diagram Composite 1 Clocking Composite 2 Composite 3 Digital Audio Audio Composite/S-Video (Y) Audio Processing Packetizer S-Video (C) Chroma Demod...

  • Page 16: Detailed Features

    As a PCI initiator, the Fusion 878A can take control of the PCI bus as soon as it is available, thereby avoiding the need for on-board frame buffers.

  • Page 17: Video Dma Channels

    1.2 Detailed Features 1.2.5 Video DMA Channels The Fusion 878A enables separate destinations for the odd and even fields, each controlled by a pixel RISC instruction list. This instruction list is created by the Fusion 878A device driver and placed in the host memory. The instructions control the transfer of pixels to target memory locations on a byte resolution basis.

  • Page 18: Pci Bus Interface

    1.2.10 Scaling and Cropping The Fusion 878A can reduce the video image size in both horizontal and vertical directions independently, using arbitrarily selected scaling ratios. The X and Y dimensions can be scaled down to one-sixteenth of the full resolution. Horizontal scaling is implemented with a 6-tap interpolation filter, while up to 5-tap interpolation is used for vertical scaling with a line store.

  • Page 19: Gpio Port

    24 general purpose I/O signals. Alternatively, the GPIO port can be used as a means to input video data. For example, the Fusion 878A can input the video data from an external digital camera and bypass the Fusion 878A’s internal video decoder block.

  • Page 20: Pin Descriptions

    1.3 Pin Descriptions PCI Video Decoder 1.3 Pin Descriptions Figure 1-3 displays the pinout diagram. Table 1-2 provides a description of pin functions grouped by common function. Figure 1-3. Fusion 878A Pinout Diagram VRXN BGND AD[31] AD[30] BGND AD[29] SMXC...

  • Page 21: Table 1-2. Pin Descriptions Grouped By Pin Function

    This input provides timing for all PCI transactions. All PCI signals except RST and INTA are sampled on the rising edge of CLK, and all other timing parameters are defined with respect to this edge. The Fusion 878A supports a PCI clock of up to 33.3333 MHz. Reset This input three-states all PCI signals asynchronous to the CLK signal.
  • Page 22 Fusion 878A 1.0 Product Overview 1.3 Pin Descriptions PCI Video Decoder Table 1-2. Pin Descriptions Grouped by Pin Function (2 of 4) Pin # Pin Name Signal Description FRAME Cycle Frame This sustained, three-state signal is driven by the current master to indicate the beginning and duration of an access.
  • Page 23 GPCLK GP Clock Video clock. Internally pulled up to VDD. 56–61, GPIO[23:0] General Purpose Fusion 878A pin decoding in normal mode. Pins pulled up to 67–72, VDD. For additional information, see Tables 3-3 and 3-5. 75–86 Digital Audio Input/Audio Test Signals (3 Pins)
  • Page 24 Fusion 878A 1.0 Product Overview 1.3 Pin Descriptions PCI Video Decoder Table 1-2. Pin Descriptions Grouped by Pin Function (4 of 4) Pin # Pin Name Signal Description VRXP Audio input circuitry reference voltage. This pin should be connected to an external filtering 0.1 µF capacitor.

  • Page 25: Functional Description

    The Fusion 878A requires an 8 × Fsc (28.63636 MHz for NTSC and 35.46895 MHz for PAL) reference time source. The 8 × Fsc clock signal, or CLK x 2, is divided down to CLK x 1 internally (14.31818 MHz for NTSC and 17.73 MHz...

  • Page 26: Figure 2-1. Ultralock Behavior For Ntsc Square Pixel Output

    Fusion 878A 2.0 Functional Description 2.1 UltraLock Functionality PCI Video Decoder pixels per line. UltraLock then interpolates the required number of pixels in a way that maintains the stability of the original image despite variation in the line length of the incoming analog waveform.

  • Page 27: Composite Video Input Formats

    [7:0] 0x70 0x70 0x7F 0x70 0x7F 0x7F 0x7F BDELAY [7:0] 0x5D 0x5D 0x72 0x5D 0x72 0x72 0xA0 NOTE(S): The Fusion 878A will not output square pixel resolution for PAL N-combination. A smaller number of pixels must be output. Conexant 100600B...

  • Page 28: Y/C Separation And Chroma Demodulation

    In addition to the Y/C separation and chroma demodulation illustrated in Figure 2-2, the Fusion 878A also supports chrominance comb filtering as an optional filtering stage after chroma demodulation. The chroma demodulation generates baseband I and Q (NTSC) or U and V (PAL/SECAM) color difference signals.

  • Page 29: Figure 2-3. Y/C Separation Filter Responses

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.3 Y/C Separation and Chroma Demodulation Figure 2-3. Y/C Separation Filter Responses Luma Notch Filter Frequency Responses Chroma Band Pass Filter Frequency Responses for NTSC and PAL/SECAM for NTSC and PAL/SECAM NTSC...

  • Page 30: Figure 2-4. Filtering And Scaling

    Fusion 878A 2.0 Functional Description 2.3 Y/C Separation and Chroma Demodulation PCI Video Decoder Figure 2-4. Filtering and Scaling Horizontal Scaler Vertical Scaler – – – – – – Luminance Luminance – – Chrominance Chrominance (Chroma Comb) -- - -- - Z Vertical Filter Options –...

  • Page 31: Video Scaling, Cropping, And Temporal Decimation

    2.4 Video Scaling, Cropping, and Temporal Decimation 2.4 Video Scaling, Cropping, and Temporal Decimation The Fusion 878A provides three mechanisms to reduce the amount of video pixel data in its output stream: down-scaling, cropping, and temporal decimation. All three can be controlled independently.

  • Page 32: Figure 2-5. Optional Horizontal Luma Low-Pass Filter Responses

    Fusion 878A 2.0 Functional Description 2.4 Video Scaling, Cropping, and Temporal Decimation PCI Video Decoder Figure 2-5. Optional Horizontal Luma Low-Pass Filter Responses NTSC PAL/SECAM QCIF QCIF ICON ICON Frequency in MHz Frequency in MHz 879A_009 Figure 2-6. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (NTSC)

  • Page 33: Figure 2-7. Combined Luma Notch, 2X Oversampling And Optional

    NTSC Frequency in MHz 879A_012 Vertical Scaling For vertical scaling, the Fusion 878A uses a line store to implement four different filtering options. The filter characteristics are illustrated in Figure 2-9. The Fusion 878A provides up to 5-tap filtering to ensure removal of aliasing artifacts.

  • Page 34: Peaking

    4-tap 5-tap Frequency/Sampling_Frequency 879A_013 2.4.1.4 Peaking The Fusion 878A enables four different peaking levels by programming the PEAK bit and HFILT bits in the SCLOOP register. The filters are illustrated in Figure 2-10 Figure 2-11. For more information, refer to SC Loop Control Register.

  • Page 35: Figure 2-10. Peaking Filters

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.4 Video Scaling, Cropping, and Temporal Decimation Figure 2-10. Peaking Filters HFILT = 01 HFILT = 00 HFILT = 11 HFILT = 10 Frequency in MHz 879A_014 Enhanced Resolution of Passband HFILT = 01...

  • Page 36: Figure 2-11. Luma Peaking Filters With 2X Oversampling Filter And Luma Notch

    Fusion 878A 2.0 Functional Description 2.4 Video Scaling, Cropping, and Temporal Decimation PCI Video Decoder Figure 2-11. Luma Peaking Filters with 2x Oversampling Filter and Luma Notch (1 of 2) HFILT = 10 HFILT = 00 HFILT = 01 HFILT = 11...

  • Page 37: Chrominance Scaling

    HSCALE is programmed with the horizontal scaling ratio. When outputting Ratio Register (HSCALE) unscaled video (in NTSC), the Fusion 878A produces 910 pixels per line. This corresponds to the pixel rate at fCLK x 1 (4 × Fsc). This register is the control for scaling the video to the desired size.
  • Page 38 VSCALE is programmed with the vertical scaling ratio. It defines the number of Ratio Register (VSCALE) vertical lines output by the Fusion 878A. The following formula should be used to determine the value to be entered into this 13-bit register. The loaded value is a two’s-complement, negative value.
  • Page 39 Fusion 878A 2.0 Functional Description PCI Video Decoder 2.4 Video Scaling, Cropping, and Temporal Decimation The following C-code fragment illustrates changing the vertical scaling value: #define VSCALE_HI 0x13 #define VSCALE_LO 0x14 typedef unsigned char BYTE; typedef unsigned int WORD; BYTE ReadFromFusion878A(BYTE regAddress);...

  • Page 40: Image Cropping

    Fusion 878A 2.0 Functional Description 2.4 Video Scaling, Cropping, and Temporal Decimation PCI Video Decoder Table 2-3. Scaling Ratios for Popular Formats Using Frequency Values VSCALE Register Values Output HSCALE Scaling Ratio Format Total Resolution Resolution Register Use Both Single...

  • Page 41: Figure 2-12. Effect Of The Cropping And Active Registers

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.4 Video Scaling, Cropping, and Temporal Decimation Figure 2-12. Effect of the Cropping and Active Registers Video frame Cropped image Horizontally Inactive Horizontally Active Video frame Cropped image scaled to 1/2 size...

  • Page 42: Cropping Registers

    Fusion 878A 2.0 Functional Description 2.4 Video Scaling, Cropping, and Temporal Decimation PCI Video Decoder 2.4.2.1 Cropping Registers Horizontal Delay For video decoding, HDELAY is programmed with the number of pixels between Register (HDELAY) horizontal sync and the first pixel of each line to be displayed or captured. For GPIO SPIOUT, the HDELAY is programmed with the number of pixels between the falling edge of HRESET and the rising edge of HACTIVE.

  • Page 43: Temporal Decimation

    The Fusion 878A provides temporal decimation on either a field or frame basis. The temporal decimation register (TDEC) is loaded with a value from 1 to 60 (NTSC) or 1 to 50 (PAL/SECAM). This value is the number of fields or frames skipped by the chip during a sequence of 60 for NTSC or 50 for PAL/SECAM.
  • Page 44 TDEC = 0x00 Decimation is not performed. Full frame rate video is out- put by the Fusion 878A. When changing the programming in the temporal decimation register, 0x00 should be loaded first, and then the decimation value. This ensures that the decimation counter is reset to 0.

  • Page 45: Video Adjustments

    PCI Video Decoder 2.5 Video Adjustments 2.5 Video Adjustments The Fusion 878A provides programmable hue, contrast, saturation, and brightness. 2.5.1 The Hue Adjust Register The Hue Adjust Register (HUE) is used to offset the hue of the decoded signal. In NTSC, the hue of the video signal is defined as the phase of the subcarrier with reference to the burst.

  • Page 46: Automatic Chrominance Gain Control

    Fusion 878A 2.0 Functional Description 2.6 Automatic Chrominance Gain Control PCI Video Decoder 2.6 Automatic Chrominance Gain Control The Automatic Chrominance Gain Control (ACGC) compensates for reduced chrominance and color-burst amplitudes. Here, the color-burst amplitude is calculated and compared to nominal. The color-difference signals are then increased or decreased in amplitude according to the color-burst amplitude difference from nominal.

  • Page 47: Coring

    2.8 Coring 2.8 Coring The Fusion 878A video decoder can perform a coring function, in which it forces all values below a programmed level to be 0. This is useful as the human eye is more sensitive to variations in black images. By taking near-black images and turning them into black, the image appears clearer to the eye.

  • Page 48: Vbi Data Output Interface

    Fusion 878A 2.0 Functional Description 2.9 VBI Data Output Interface PCI Video Decoder 2.9 VBI Data Output Interface A frame of video is composed of 525 lines for NSTC and 625 for PAL/SECAM. Figure 2-15 illustrates an NTSC video frame, in which there are a number of distinct regions.

  • Page 49: Vbi Line Output Mode

    PCI Video Decoder 2.9 VBI Data Output Interface The Fusion 878A is able to capture VBI data and store it in the host memory for later processing by the Fusion 878A VBI decoder software. Two modes of VBI capture exist: VBI line output mode and VBI frame output mode. Both types of data may be captured during the same field.

  • Page 50: Figure 2-18. Vbi Section Block Diagram

    Fusion 878A 2.0 Functional Description 2.9 VBI Data Output Interface PCI Video Decoder Figure 2-18. VBI Section Block Diagram Video Data Format Converter FIFOs DMA Controller PCI Initiator YCrCb 4:2:2, 4:1:1 Y: 70x36 Analog Address Generator Video Format Data CSC/Gamma...

  • Page 51: Video Data Format Conversion

    (see Section 2.12). Fusion 878A also offers a Y8 color format, in which the chroma component of the packed 4:2:2 data is stripped and the luma component is packed into 8 bits. This format is otherwise known as gray scale.

  • Page 52: Figure 2-19. Video Data Format Converter

    Fusion 878A 2.0 Functional Description 2.10 Video Data Format Conversion PCI Video Decoder Figure 2-19. Video Data Format Converter Linear Gamma Correction Removal FI[31:0] From Bt879 Family 8-Bit dithered To FIFO Color Video Decoder/Scaler Up-Sample Space Dither Chroma Packed 4:2:2...

  • Page 53: Table 2-5. Color Formats

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.10 Video Data Format Conversion Table 2-5. Color Formats Pixel Data [31:0] Format DWORD Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0 [31:24] [23:16] [15:8] [7:0] Alpha RGB32...

  • Page 54: Ycrcb To Rgb Conversion

    PCI Video Decoder 2.10.3 YCrCb to RGB Conversion The 4:2:2 YCrCb data stream from the video decoder portion of the Fusion 878A must be converted to 4:4:4 YCrCb before the RGB conversion occurs, using an interpolation filter on the chroma data path. The even valid chroma data passes through unmodified, while the odd data is generated by averaging adjacent even data.

  • Page 55: Byte Swapping

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.10 Video Data Format Conversion sub-sampling is achieved. In the YUV9 format, lines 2–4 of Cr/Cb data are discarded, and hence 4:1:1 vertical sub-sampling is achieved. 2.10.6 Byte Swapping Before the data enters the FIFO it passes through a 4-way MUX to allow swapping of the bytes to support Macintosh (big endian) color data formats.

  • Page 56: Video And Control Data Fifo

    Fusion 878A 2.0 Functional Description 2.11 Video and Control Data FIFO PCI Video Decoder 2.11 Video and Control Data FIFO The FIFO block accepts data from the video data format conversion process, buffers the data in FIFO memory, then outputs DWORDs to the DMA Controller to be burst onto the PCI bus.

  • Page 57: Fifo Data Interface

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.11 Video and Control Data FIFO 2.11.2 FIFO Data Interface Loading data into the FIFO can begin only when valid pixels are present during the even or the odd field. The pixel DWORD Pixel Data (PD) [31:0] is stored in FI[31:0], and the video control code STATUS[3:0] is stored in FI[35:32].

  • Page 58: Physical Implementation

    (33 MHz). All three FIFOs can be read simultaneously. Some bus systems may be designed with PCI clocks slower than 33 MHz. The Fusion 878A data FIFO only supports systems where the maximum input data rate is less than the output data rate.

  • Page 59: Table 2-9. Table Of Pci Bus Access Latencies

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.11 Video and Control Data FIFO Table 2-9. Table of PCI Bus Access Latencies Max Bus Video Format Resolution Mode Latency Before FIFO µ Overflow ( NTSC 30 fps 640 x 480...

  • Page 60: Dma Controller

    PCI target, the RISC program puts its own starting address in a Fusion 878A register and makes it available to the DMA controller. The DMA controller then requests the PCI initiator to fetch an instruction. The RISC instructions available are WRITE, SKIP, SYNC, and JUMP.

  • Page 61: Target Memory

    879A_026 2.12.1 Target Memory The Fusion 878A’s FIFO DWORDs are perfectly aligned to the PCI bus: i.e., bit 0 of the FIFO DWORDs lines up with bit AD[0] on the PCI bus. Thus, video scan line data is aligned to target memory locations, and data path combinational logic between the FIFO and the PCI bus is not required.

  • Page 62: Risc Instructions

    Fusion 878A 2.0 Functional Description 2.12 DMA Controller PCI Video Decoder The software will set up a pixel data flow by creating a RISC instruction sequence in the host memory for the odd and even fields. The DMA controller normally branches through the RISC instruction sequence via JUMP instructions.
  • Page 63 Fusion 878A 2.0 Functional Description PCI Video Decoder 2.12 DMA Controller Table 2-10. RISC Instructions (2 of 5) Instruction Opcode DWORDs Description WRITE123 1001 Write pixels to memory in planar mode from the FIFOs beginning at the specified target addresses.
  • Page 64 Fusion 878A 2.0 Functional Description 2.12 DMA Controller PCI Video Decoder Table 2-10. RISC Instructions (3 of 5) Instruction Opcode DWORDs Description WRITE1S23 1011 Write pixels to memory in planar mode from the FIFO1 beginning at the specified target addresses. Skip pixels from FIFO2 and FIFO3. This instruction is used to achieve the YUV9 and YUV12 color modes, where the chroma components are sub-sampled.
  • Page 65 Fusion 878A 2.0 Functional Description PCI Video Decoder 2.12 DMA Controller Table 2-10. RISC Instructions (4 of 5) Instruction Opcode DWORDs Description SKIP 0010 Skip pixels by discarding byte-count number of bytes from the FIFO. This may start and stop in the middle of a DWORD.
  • Page 66 Fusion 878A 2.0 Functional Description 2.12 DMA Controller PCI Video Decoder Table 2-10. RISC Instructions (5 of 5) Instruction Opcode DWORDs Description JUMP 0111 Jump the RISC program counter to the jump address. This allows unconditional branching of the sequencer program.

  • Page 67: Complex Clipping

    A clip list is provided through the graphics system DirectDRAW Interface provider to the Fusion 878A device driver software. This indicates the areas of the display where the video image is to be occluded. The Fusion 878A driver...

  • Page 68: Executing Instructions

    Fusion 878A 2.0 Functional Description 2.12 DMA Controller PCI Video Decoder Figure 2-22. Example of Complex Clipping System DRAM Graphics Controller Frame Buffer Video in a Window Dialog Odd Field Prog Write #Bytes @ Line 0 Packed RGB Write #B @ L40, Skip #B, Wr #B @ L40...

  • Page 69: Fifo Overrun Conditions

    This allows the FIFO overruns to be handled gracefully, with minimal loss of data. The Fusion 878A is not required to abort a whole scan during FIFO overruns. The DMA controller keeps track of the data to the nearest byte, and is able to deliver the rest of the scan line in case the FIFO overrun condition is cleared.

  • Page 70: Fifo Data Stream Resynchronization

    Y data. 2.12.7 FIFO Data Stream Resynchronization The Fusion 878A DMA controller is constantly monitoring whether there is a mismatch between the amount of data expected by the RISC instruction and the amount of data being provided by the FIFO. The DMA controller then corrects for the mismatches and realigns the RISC program and the FIFO data stream.

  • Page 71: Byte Alignment

    Byte alignment in the Fusion 878A, which applies only to packed modes, disables the PCI byte and enables C/BE# during the initial part of a line transfer.

  • Page 72: Multifunction Arbiter

    An internal arbiter is necessary to determine whether the video or audio DMA controller claims the PCI bus when a GNT is issued to the Fusion 878A. Only one of the two functions may actually see the GNT active during any one PCI clock cycle.

  • Page 73: Interfacing With Non-Pci 2.1 Compliant Core Logic

    GNT is de asserted. This also has the side effect of not being able to take advantage of bus parking, thus lowering arbitration performance. The Fusion 878A drivers must query for these non-compliant devices, and set the EN_VSFX bit only if required.

  • Page 74: Audio A/D

    Fusion 878A 2.0 Functional Description 2.15 Audio A/D PCI Video Decoder 2.15 Audio A/D 2.15.1 Muxing and Anti-aliasing Filtering Before entering the audio A/D, the TV, FM, and microphone/line audio inputs are selected by A_SEL and multiplexed. The MUX selects are break-before-make. If A_SEL is set to 3, no mux is enabled.
  • Page 75 Fusion 878A 2.0 Functional Description PCI Video Decoder 2.15 Audio A/D Table 2-12. Gain Control (2 of 2) Input Nominal A_GAIN GAIN Input V 2.667 8.52 0.188 0.530 2.833 9.05 0.176 0.499 3.000 9.54 0.167 0.471 In addition to the switched capacitor gain control, there is a +6 dB switch in the pre-amp.

  • Page 76: High Speed Serial Interface Mode

    Fusion 878A 2.0 Functional Description 2.16 High Speed Serial Interface Mode PCI Video Decoder 2.16 High Speed Serial Interface Mode The same interface used for digital audio may be used for other types of digital serial data. With default settings, the maximum data rate into the serial interface is 16.6 MHz, due to PCI clock resampling of the ASCLK.

  • Page 77: Asynchronous Data Parallel Mode: Raw Data Capture

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.17 Asynchronous Data Parallel Mode: Raw Data Capture 2.17 Asynchronous Data Parallel Mode: Raw Data Capture The asynchronous data parallel port interface allows the user to multiplex raw data from the GPIO port into the audio packetizer. Normally, the audio processor selects the 16-bit digitized analog data from the audio A/D and from the 16-bit digital audio input data.

  • Page 78: Digital Audio Packetizer

    Fusion 878A 2.0 Functional Description 2.18 Digital Audio Packetizer PCI Video Decoder 2.18 Digital Audio Packetizer The Digital Audio Packetizer (DAP) block can packetize data input on ASCLK, ALRCK, and ADATA in two additional modes besides normal I S mode. It can also packetize asynchronous parallel data from the GPIO pins (Asychronous Data Parallel Port).

  • Page 79: Fifo Interface

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.18 Digital Audio Packetizer 2.18.3 FIFO Interface The audio FIFO de couples the high-speed PCI interface from the slow audio data packetizer. The size chosen provides for efficient PCI bursts and effective PCI...

  • Page 80: Audio Packets And Data Capture

    Fusion 878A 2.0 Functional Description 2.18 Digital Audio Packetizer PCI Video Decoder 2.18.4 Audio Packets and Data Capture Audio samples are grouped into a line packet of length ALP_LEN bytes. The audio line packets are grouped to form an audio field packet of length AFP_LEN audio lines.

  • Page 81: Digital Audio Input

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.18 Digital Audio Packetizer bytes. The data following one line of length ALP_LEN will begin the next line (no data lost). The ALP_LEN sequence is repeated AFP_LEN times. The last 36-bit word written to the FIFO contains the VRO end-of-audio-field status code (DWORD data portion = don’t care).

  • Page 82: Data Packet Mode

    Fusion 878A 2.0 Functional Description 2.18 Digital Audio Packetizer PCI Video Decoder There can be any number of ASCLKs ≥ 16 (usually 16–32 between ALRCK edges. Thus there may be extra ASCLKs versus collected data bits. There is no requirement for ASCLK (or ALRCK or ADATA)) to be continuous. A specified edge of ASCLK is used to sample the other two signals.

  • Page 83: Audio Data Formats

    Fusion 878A 2.0 Functional Description PCI Video Decoder 2.18 Digital Audio Packetizer 2.18.7 Audio Data Formats Table 2-14 provides a summary of audio data formats (signed integer 16/8-bit) flowing through the audio FIFO. The audio data path is illustrated in Figure 2-27.

  • Page 84: Digital Television Support

    Fusion 878A 2.0 Functional Description 2.19 Digital Television Support PCI Video Decoder 2.19 Digital Television Support Digital television support will be available through upcoming application notes. Please contact the local sales office for availability. Conexant 2-60 100600B...

  • Page 85: Electrical Interfaces

    In the second configuration, connect three inputs to the composite sources and the other input to the luma component of the S-Video connector. When an S-Video source is input to the Fusion 878A, the luma component feeds through the input analog multiplexer, and the chroma component feeds directly into the C input pin.

  • Page 86: Multiplexer Considerations

    Fusion 878A 3.0 Electrical Interfaces 3.1 Input Interface PCI Video Decoder Figure 3-1. Typical External Circuitry Audio Optional Video Antialiasing Filter 3.3 µH 0.1 µF 0.1 µF 0.1 µF REFP MUX(0–3) BGND 75 Ω 330 pF 330 pF 0.1 µF AGND 9.53 kΩ...

  • Page 87: Flash A/D Converters

    Fusion 878A defaults to NTSC-M format. 3.1.6 Automatic Gain Controls The Fusion 878A controls the voltage for the top of the reference ladder for each A/D. The automatic gain control adjusts the REFP, YREF+, and CREF+ voltage levels until the back porch sampling of the Y video input, as controlled by ADELAY, generates a digital code 0x38 from the A/D.
  • Page 88 • 28.63636 MHz • Third overtone or fundamental • Parallel resonant • 30 pF load capacitance • 50 ppm • Series resistance 40 Ω or less Recommended crystals for use with the Fusion 878A are listed in Table 3-1. Conexant 100600B...

  • Page 89: Table 3-1. Recommended Crystals

    CMOS voltage levels are required. The load capacitance in the crystal configurations may vary depending on the magnitude of board parasitic capacitance. The Fusion 878A is dynamic, and to ensure proper operation, the clocks must always be running with a minimum frequency of 28.63636 MHz.

  • Page 90: Oversampling And Input Filtering

    Digitized video needs to be band-limited in order to avoid aliasing artifacts. Because the Fusion 878A samples the video data at 8 × Fsc (over twice the normal rate), no filtering is required at the input to the A/Ds. The analog video needs to be band-limited to 14.32 MHz in NTSC and 17.73 MHz in PAL/SECAM...

  • Page 91: Figure 3-3. Luma And Chroma 2X Oversampling Filter

    Fusion 878A 3.0 Electrical Interfaces PCI Video Decoder 3.1 Input Interface Figure 3-3. Luma and Chroma 2x Oversampling Filter PAL/SECAM NTSC PAL/SECAM NTSC Frequency in MHz Frequency in MHz 879A_034 Conexant 100600B...

  • Page 92: Pci Bus Interface

    3.2 PCI Bus Interface The PCI local bus is an architectural, timing, electrical, and physical interface that allows the Fusion 878A to interface to the local bus of a host CPU. The Fusion 878A is fully compliant with PCI Rev. 2.2 specifications.

  • Page 93: Figure 3-4. Pci Video Block Diagram

    Fusion 878A 3.0 Electrical Interfaces PCI Video Decoder 3.2 PCI Bus Interface Figure 3-4. PCI Video Block Diagram FIFO Data PCI Control Signals Controller Initiator FIFO Control Signals Target C Master PCI Config. Registers Local Registers GPIO Video Decoder INTA...

  • Page 94: General Purpose I/O Port

    The Normal mode of the GPIO port can be used to input or output general board-level signals to or from the PCI interface in the Fusion 878A. The GPIOMODE bits are in the default state of 00 during Normal mode. The GPIO port in Normal mode was not designed to support a high-speed interface for video data or other types of data.

  • Page 95: Figure 3-7. Gpio Normal Mode

    Fusion 878A 3.0 Electrical Interfaces PCI Video Decoder 3.3 General Purpose I/O Port Figure 3-7. GPIO Normal Mode Video Video Data DMA Controller Scaler FIFO Decoder Format Converter and PCI Initiator Local Registers GPIO Port 24 Bits of General I/O...

  • Page 96: Spi Input Mode

    Fusion 878A 3.0 Electrical Interfaces 3.3 General Purpose I/O Port PCI Video Decoder 3.3.4 SPI Input Mode SPI Input mode is used to input Synchronous Pixel Interface video information into the part. The interface accepts 16-bit YCrCb video data. Because the incoming video is inserted after the decoder and scaler, no adjustments can be made on hue, contrast, saturation, or brightness.

  • Page 97: Spi Output Mode

    Fusion 878A 3.0 Electrical Interfaces PCI Video Decoder 3.3 General Purpose I/O Port Table 3-2. SPI Input GPIO Signals (2 of 2) GPIO Signal Description Number [17] VACTIVE An active high signal that indicates the beginning of the active video and is accepted on the rising edge of GPCLK.

  • Page 98: Table 3-3. Spi Gpio Output Signals

    Fusion 878A 3.0 Electrical Interfaces 3.3 General Purpose I/O Port PCI Video Decoder Table 3-3. SPI GPIO Output Signals GPIO Signal Description Number [23] HRESET A 64-clock-long active low pulse, output following the rising edge of CLKx1. The falling edge of HRESET indicates the beginning of a new video line.

  • Page 99: Figure 3-10. Basic Timing Relationships For Spi Output Mode

    Fusion 878A 3.0 Electrical Interfaces PCI Video Decoder 3.3 General Purpose I/O Port Figure 3-10. Basic Timing Relationships for SPI Output Mode Y[7:0] [7:0] DVALID HACTIVE GPCLK CBFLAG 879A_043 Related video timing signals for both fields are illustrated in Figure 3-11.

  • Page 100: Figure 3-11. Video Timing In Spi Output Mode

    Fusion 878A 3.0 Electrical Interfaces 3.3 General Purpose I/O Port PCI Video Decoder Figure 3-11. Video Timing in SPI Output Mode Beginning of Fields 1, 3, 5, 7 HRESET VRESET FIELD HACTIVE VACTIVE VBISEL 2-6 Scan Lines VDELAY/2 Scan Lines...

  • Page 101: Gpio Spi Mode Timing Parameters

    Fusion 878A 3.0 Electrical Interfaces PCI Video Decoder 3.3 General Purpose I/O Port 3.3.6 GPIO SPI Mode Timing Parameters For the timing parameters of GPIO SP1 mode, refer to Table 3-4. Table 3-4. GPIO SPI Mode Timing Parameters Parameter Symbol Units NTSC: 4 ×...

  • Page 102: Digital Video Input Mode

    Additional digital interfaces may be implemented by changing the TG_RAM contents. Contact your local Conexant sales office for more information. Table 3-5. Pin Definition of GPIO Port When Using Digital Video-In Mode...

  • Page 103: Modified Smpte-125

    Fusion 878A 3.0 Electrical Interfaces PCI Video Decoder 3.3 General Purpose I/O Port Figure 3-12. CCIR 656 Interface to Digital Input Port Clock GPCLK CCIR 656 Fusion 878A Video Generator DATA[7:0] GPIO[7:0] 879A_044 3.3.7.2 Modified The Modified SMPTE-125 interface is the same as CCIR656, but the clock runs SMPTE-125 at 24.54 MHz, with 640 active pixels on a 780 pixel line.

  • Page 104: Gpio Timing Diagram For Spi And Digital Video Input Modes

    Fusion 878A 3.0 Electrical Interfaces 3.3 General Purpose I/O Port PCI Video Decoder 3.3.8 GPIO Timing Diagram for SPI and Digital Video Input Modes Figure 3-13 illustrates an overview of the GPIO timing for SPI Input and Digital Video Input modes.

  • Page 105: I 2 C Interface

    SDA transfer data between the bus master and the slave device. The I C bus within the Fusion 878A supports repeated starts, up to 396.8 kHz timing, and multi-byte sequential transactions. The I2CRATE signal specifies either 99.2 kHz or 396.8 kHz timing rate. If the PCI clock runs at less than the maximum rate, these rates will slow down proportionately.

  • Page 106: Figure 3-15. I 2 C Typical Protocol Diagram

    The R/W mode was saved from the first register write when the START was transmitted, so I2CDB0 is a Don’t Care during 1-byte reads. For detailed information on the I C bus, refer to The I C-Bus Reference Guide, reprinted by Conexant. Conexant 3-22 100600B...

  • Page 107: I2C Serial Eeprom Interface

    3.5.1 EEPROM Address Mapping Fusion 878A can support one EEPROM (max 256 B), typically a single 24C02. Re-map the 8-bit addressable physical memory space to an 8-bit logical address space by inverting the address A[7:0], and subtracting 4. The 7-bit slave device address is 1010_xxx where the xxx bits are (normally used for A[10:8]) set to zero.

  • Page 108: Subsystem Vendor Id

    Fusion 878A 3.0 Electrical Interfaces 3.5 I2C Serial EEPROM Interface PCI Video Decoder 3.5.2 Subsystem Vendor ID PCI Configuration Header Location 0x2C specifies the subsystem vendor ID and the subsystem ID. If an external EEPROM is present, the subsystem vendor ID and subsystem ID and vital product data are uploaded.

  • Page 109: Programming And Write-Protect

    15-bit address to the appropriate bits in the VPD Capability register. After four bytes are written to the EEPROM, the Fusion 878A resets the flag bit to 0. The VPD Data Register is byte-accessible; however, all data transfers between the EEPROM and the Fusion 878A are 4-byte transactions.

  • Page 110: Vital Product Data Read Sequence

    Fusion 878A 3.0 Electrical Interfaces 3.5 I2C Serial EEPROM Interface PCI Video Decoder 3.5.3.2 Vital Product When SW resets the VPD flag bit, the device initiates the following I C sequence Data Read Sequence to read four bytes from the EEPROM (assumes VPD address was set to 0): Table 3-8.
  • Page 111 Fusion 878A 3.0 Electrical Interfaces PCI Video Decoder 3.5 I2C Serial EEPROM Interface The device resets the VPD flag bit once all four bytes from the VPD data register are programmed into the EEPROM. If a slave NACK is received during either page write, the sequence is aborted and the flag bit is not reset.

  • Page 112: Power Management Interface

    3.0 Electrical Interfaces 3.6 Power Management Interface PCI Video Decoder 3.6 Power Management Interface Fusion 878A supports the new capabilities feature for power management as outlined in PCI Bus Power Management Interface Specification, Revision 1.1. Power management states D0, D3 and D3 are supported.

  • Page 113: Jtag Interface

    JTAG’s approach to testability uses boundary scan cells placed at each digital pin and digital interface. In the Fusion 878A, a digital interface is the boundary between an analog block and a digital block. All cells are interconnected into a boundary scan register that applies or captures test data used for functional verification of the integrated circuit.

  • Page 114: Optional Device Id Register

    3.7.4 Verification with the TAP Controller A variety of verification procedures can be performed through the TAP controller. With a set of four instructions, the Fusion 878A can verify board connectivity at all digital interfaces and pins. The instructions (listed below) are accessible by using a state machine standard to all JTAG controllers: •...

  • Page 115: Pc Board Layout Considerations

    4.0 PC Board Layout Considerations 4.1 Layout Considerations The PC board layout should be optimized for lowest noise on the Fusion 878A power and ground lines. Route digital traces away from analog traces. All shields must be connected to the ground plane with low impedance connection. Use shielded connectors.

  • Page 116: Components

    4.0 PC Board Layout Considerations 4.1 Layout Considerations PCI Video Decoder and around the Fusion 878A, if possible. Avoid creating a cut in the plane with feed-throughs: instead, disperse them. To fill: • Copper fill ground on the component side •...

  • Page 117: Split Planes And Voltage Regulators

    4.2 Split Planes and Voltage Regulators 4.2 Split Planes and Voltage Regulators The reference designs included in the Bt878/Fusion 878A Hardware Users Guide have no split planes. Careful attention has been given to creating one continuous ground plane and one continuous power plane. This implementation produces optimal video and audio performance.

  • Page 118: Latchup Avoidance

    Latchup can also occur if the voltage on any power pin exceeds the voltage on any other power pin by more than 0.5 V . To avoid latchup of the Fusion 878A, follow these precautions: • Apply power to the device before or at the same time as you apply power to the interface circuit.

  • Page 119: Control Register Definitions-Function 0

    0. Internal addressing of Fusion 878A registers occurs via AD[7:2] and the byte enable bits of the PCI bus. The 8-bit byte address for each of the following register locations is {AD[7:2], 00}.

  • Page 120: Figure 5-1. Function 0 Pci Configuration Space Header

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.1 PCI Configuration Space PCI Video Decoder Figure 5-1. Function 0 PCI Configuration Space Header AD[7:2] 0x00 Device ID Vendor ID 0x04 Status Command 0x08 Class Code Revision ID 0x0C Reserved Header Type 0...

  • Page 121: Pci Configuration Registers (Header)

    The Command[15:0] register provides control over ability to generate and respond to PCI cycles. When a 0 is written to this register, Fusion 878A is logically disconnected from the PCI bus except for configuration cycles. The unused bits in this register are set to a logical 0. The Status[31:16] register is used to record status information regarding PCI bus related events.

  • Page 122: 0X08-Revision Id And Class Code Register

    Parity Error Response A value of 1 enables parity error reporting. Bus Master A value of 1 enables Fusion 878A to act as a bus initiator. Memory Space A value of 1 enables response to memory space accesses (target decode to memory mapped registers).

  • Page 123: 0X3C-Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register

    250 ns. Affects the desired settings for the latency timer value. Set for 128 DWORDs, with 0 wait states. [15:8] 0x01 Interrupt Fusion 878A interrupt pin is connected to INTA, the only one usable by a single function device. [7:0] Interrupt Communicates interrupt line routing information between the POST code and Line the device driver.

  • Page 124: 0X44-Vpd Capability Register

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.2 PCI Configuration Registers (Header) PCI Video Decoder 0x44 VPD Capability Register — Bits Type Default Name Description [31] VPD_Flag This flag is set to a value of 1 when the device completes reading and transfer of 4 bytes between the EEPROM and the VPD data register.

  • Page 125: 0X50-Power Management Support Registers

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.2 PCI Configuration Registers (Header) 0x50 Power Management Support Registers — Bits Type Default Name Description [31:24] 0x00 Pwr-Data This field is used to report the state dependent data requested by Data_Select and scaled by Data_Scale.

  • Page 126: Local Registers (Memory Mapped)

    5.3 Local Registers (Memory Mapped) Fusion 878A’s local registers reside in the 4 kB memory addressed space reserved for each function. All of the registers correspond to DWORD or a subset thereof. Local registers may be written to or read through the PCI bus at any time.

  • Page 127: 0X000-Device Status Register (Dstatus)

    This bit identifies the number of lines found in the video stream. This bit is used to determine the type of video input to the Fusion 878A. Before this status bit will change, 32 consecutive fields with the same number of lines are required.

  • Page 128: 0X004-Input Format Register (Iform)

    Reserved This bit must be set to 0. [6:5] MUXSEL Used for software control of video input selection. The Fusion 878A can select between four composite video sources, or three composite sources, and one S-Video source. 00 = Select MUX3...

  • Page 129: Msb Cropping Register)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) MSB Cropping Register) 0x00C—Even Field (E_CROP) 0x08C—Odd Field (O_CROP) Upon reset this register is initialized to 0x12. HACTIVE_MSB(0) is the LSB. See the VACTIVE, VDELAY, HACTIVE, and HDELAY registers for descriptions on the operation of this register.

  • Page 130: Horizontal Delay Register, Lower Byte

    Upon reset it is initialized to 0x80. HACTIVE_LO(0) is the LSB. HACTIVE defines the number of horizontal active pixels per line output by the Fusion 878A. This 8-bit register is the lower byte of the 10-bit HACTIVE register. The two MSBs of HACTIVE are contained in the CROP register.

  • Page 131: 0X028-Brightness Control Register (Bright)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x028—Brightness Control Register (BRIGHT) Upon reset this register is initialized to 0x00. Bits Type Default Name Description [7:0] 0x00 BRIGHT The brightness control involves the addition of a two’s complement number to the luma channel.

  • Page 132: Miscellaneous Control Register

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder Miscellaneous Control Register 0x02C—Even Field (E_CONTROL) 0x0AC—Odd Field (O_CONTROL) Upon reset this register is initialized to 0x20. SAT_V_MSB is the LSB. Bits Type Default Name...

  • Page 133: 0X030-Luma Gain Register, Lower Byte (Contrast_Lo)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x030—Luma Gain Register, Lower Byte (CONTRAST_LO) Upon reset CONTRAST_LO is initialized to 0xD8. CONTRAST_LO(0) is the LSB. Bits Type Default Name Description [7:0] 0xD8 CONTRAST_LO The CON_MSB bit and the CONTRAST_LO register concatenate to form the 9-bit CONTRAST register.

  • Page 134: 0X034-Chroma (U) Gain Register, Lower Byte (Sat_U_Lo)

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x034—Chroma (U) Gain Register, Lower Byte (SAT_U_LO) Upon reset SAT_U_LO is initialized to 0xFE. SAT_U_LO(0) is the LSB. SAT_U_MSB in the Miscellaneous CONTROL register, and SAT_U_LO concatenate to create a 9-bit register (SAT_U). Use this register to add a gain adjustment to the U component of the video signal.

  • Page 135: 0X038-Chroma (V) Gain Register, Lower Byte (Sat_V_Lo)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x038—Chroma (V) Gain Register, Lower Byte (SAT_V_LO) Upon reset SAT_V_LO is initialized to 0xB4. SAT_V_LO(0) is the LSB. SAT_V_MSB in the Miscellaneous CONTROL register and SAT_V_LO concatenate to create a 9-bit register (SAT_V). Use this register to add a gain adjustment to the V component of the video signal.

  • Page 136: 0X03C-Hue Control Register (Hue)

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x03C—Hue Control Register (HUE) Upon reset HUE is initialized to 0x00. HUE(0) is the LSB. Bits Type Default Name Description [7:0] 0x00 Hue adjustment involves the addition of a two’s complement number to the demodulating subcarrier phase.

  • Page 137: Sc Loop Control Register

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) SC Loop Control Register 0x040—Even Field (E_SCLOOP) 0x0C0—Odd Field (O_SCLOOP) Bits Type Default Name Description PEAK This bit determines whether the normal luma low-pass filters are implemented via the HFILT bits, or the peaking filters are implemented.

  • Page 138: 0X044-White Crush Up Register (Wc_Up)

    RANGE Luma Output Range. This bit determines the range for the luminance output on the Fusion 878A. Limit the range when using the control codes as video timing. 0 = Normal operation (Luma range 16–253, chroma range 2–253). Y = 16 is black (pedestal).

  • Page 139: Vertical Scaling Register, Upper Byte

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) Vertical Scaling Register, Upper Byte 0x04C—Even Field (E_VSCALE_HI) 0x0CC—Odd Field (O_VSCALE_HI) Upon reset this register is initialized to 0x60. Bits Type Default Name Description VSFLDALIGN...

  • Page 140: 0X5B-Audio Reset Register (Areset)

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x5B—Audio Reset Register (ARESET) Upon reset, ARESET is initialized to 0x00. Bits Type Default Name Description ARESET This bit must be toggled high and then low to reset the audio circuitry. ARESET must be toggled at least once anytime the audio path is enabled.

  • Page 141: 0X068-Adc Interface Register (Adc)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x068—ADC Interface Register (ADC) Upon reset, ADC is initialized to 0x82. CRUSH is the LSB. Bits Type Default Name Description [7:6] Reserved This bit is reserved and must be set to 0.

  • Page 142: Video Timing Control Register

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder Video Timing Control Register 0x6C—Even Field (E_VTC) 0xEC—Odd Field (O_VTC) Upon reset, this register is initialized to 0x00. VFILT(0) is the LSB. Bits Type Default...

  • Page 143: 0X078-White Crush Down Register

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x078—White Crush Down Register This control register may be written to or read by the MPU at any time, and upon reset is initialized to 0x7F.

  • Page 144: 0X084-Timing Generator Control (Tgctrl) Register

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x084—Timing Generator Control (TGCTRL) Register Upon reset, TGCTRL is initialized to 00. Reserved Must be written with a logical zero. [6:5] TGCKO GPCLK Output Clock Select...

  • Page 145: X0B0—Total Line Count Register (Vtotal_Lo)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x0B0—Total Line Count Register (VTOTAL_LO) If this register is set to non-zero, the 10-bit value will change the decoder’s vertical synchronization line count from the normal 525/625.

  • Page 146: 0X0D4-Color Format Register (Color_Fmt)

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x0D4—Color Format Register (COLOR_FMT) Bits Type Default Name Description [7:4] 0000 COLOR_ODD Odd Field Color Format 0000 = RGB32 0001 = RGB24 0010 = RGB16...

  • Page 147: X0D8—Color Control Register (Color_Ctl)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x0D8—Color Control Register (COLOR_CTL) A value of 1 enables byte swapping of data entering the FIFO. B3[31:24] is swapped with B2[23:16] and B1[15:8] is swapped with B0[7:0].

  • Page 148: 0X0E8-Field Capture Counter Register (Fcap)

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x0E0—VBI Packet Size Register (VBI_PACK_SIZE) Bits Type Default Name Description [7:0] 0x00 VBI_PKT_LO Lower 8 bits for the number of raw data DWORDS (four 8-bit samples) to capture while in VBI capture mode.

  • Page 149: 0X0F8-Integer Register (Pll-Xci)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x0F8—Integer Register (PLL-XCI) Upon reset this register is initialized to 00. Bits Type Default Name Description PLL_X PLL Ref XTAL pre-divider. 0 = Use 1 for pre-divider...

  • Page 150: 0X100-Interrupt Status Register (Int_Stat)

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x100—Interrupt Status Register (INT_STAT) This register provides status of pending interrupt conditions. To clear the interrupts, read this register and write the same data back. A 1 in the write data clears the particular register bit. The interrupt/status bits can be polled at any time.

  • Page 151: 0X104-Interrupt Mask Register (Int_Mask)

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) Bits Type Default Name Description VPRES Set when the analog video signal input changes from present to absent or vice versa. HLOCK Set if the horizontal lock condition changes on incoming video.

  • Page 152: 0X10C-Gpio And Dma Control Register (Gpio_Dma_Ctl)

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x10C—GPIO and DMA Control Register (GPIO_DMA_CTL) Bits Type Default Name Description [15] GPINTC A value of 0 selects the direct non-inverted/inverted input from GPINTR to go to the interrupt status register.

  • Page 153: 0X110-I2C Data/Control Register

    Fusion 878A 5.0 Control Register Definitions-Function 0 PCI Video Decoder 5.3 Local Registers (Memory Mapped) 0x110—I2C Data/Control Register Bits Type Default Name Description [31:24] — I2CDB0 First byte sent in an I C transaction. Typically this will be the base or chip 7-bit address and the R/W bit.

  • Page 154: 0X114-Risc Program Start Address Register (Risc_Strt_Add)

    Fusion 878A 5.0 Control Register Definitions-Function 0 5.3 Local Registers (Memory Mapped) PCI Video Decoder 0x114—RISC Program Start Address Register (RISC_STRT_ADD) Bits Type Default Name Description [31:0] 0x00000000 RISC_IPC Base address for the RISC program. Standard 32-bit memory space byte address, although the software must DWORD-align by setting the lowest two bits to 00.

  • Page 155: Control Register Definitions-Function 1

    0. Internal addressing of Fusion 878A registers occurs via AD[7:2] and the byte enable bits of the PCI bus. The 8-bit byte address for each of the following register locations is {AD[7:2], 00}.

  • Page 156: Figure 6-1. Function 1 Pci Configuration Space Header

    Fusion 878A 6.0 Control Register Definitions–Function 1 6.1 PCI Configuration Space PCI Video Decoder Figure 6-1. Function 1 PCI Configuration Space Header AD[7:2] 0x00 Device ID Vendor ID 0x04 Status Command Class Code Revision ID 0x08 0x0C Reserved Header Type 0...

  • Page 157: Pci Configuration Registers (Header)

    The Command[15:0] register provides control over ability to generate and respond to PCI cycles. When a 0 is written to this register, Fusion 878A is logically disconnected from the PCI bus except for configuration cycles. The unused bits in this register are set to a logical 0. The Status[31:16] register is used to record status information regarding PCI bus related events.

  • Page 158: 0X08-Revision Id And Class Code Register

    Parity Error Response A value of 1 enables parity error reporting. Bus Master A value of 1 enables Fusion 878A to act as a bus initiator. Memory Space A value of 1 enables response to memory space accesses (target decode to memory-mapped registers).

  • Page 159: 0X2C-Subsystem Id And Subsystem Vendor Id Register

    DWORDs, 33 MHz, with 0 wait states. [15:8] 0x01 Interrupt Pin Fusion 878A interrupt pin is connected to INTA, the only one usable by a single function device. [7:0] Interrupt Line The Interrupt Line register communicates interrupt line routing information between the POST code and the device driver.

  • Page 160: 0X40-Device Control Register

    Fusion 878A 6.0 Control Register Definitions–Function 1 6.2 PCI Configuration Registers (Header) PCI Video Decoder 0x40 Device Control Register — Bits Type Default Name Description [7:3] 00000 Reserved EN_VSFX Enables VIA/SIS PCI controller compatibility mode for both Functions 0 and 1.

  • Page 161: 0X48-Vpd Data Register

    Fusion 878A 6.0 Control Register Definitions–Function 1 PCI Video Decoder 6.2 PCI Configuration Registers (Header) 0x48—VPD Data Register Bits Type Default Name Description [31:0] — VPD Data Always transfers 4 bytes between the VPD data register and the EEPROM. The LSByte...MSByte is transferred from/to VPD_Adr...VPD_Adr+3.

  • Page 162: 0X50-Power Management Support Register

    Fusion 878A 6.0 Control Register Definitions–Function 1 6.2 PCI Configuration Registers (Header) PCI Video Decoder 0x50—Power Management Support Register Bits Type Default Name Description [31:24] 0x00 Pwr-Data This field is used to report the state-dependent data requested by Data_Select and scaled by Data_Scale. Optional and not supported.

  • Page 163: Local Registers (Memory Mapped)

    DWORDs or a subset thereof. The local registers may be written to or read through the PCI bus at any time. Internal addressing of the Fusion 878A local registers occurs via AD[11:2] and the byte enable bits of the PCI bus. The local memory-mapped register address locations are specified as 12-bit offsets to the value loaded into the function’s memory-base address register.

  • Page 164: 0X100-Interrupt Status Register (Int_Stat)

    Fusion 878A 6.0 Control Register Definitions–Function 1 6.3 Local Registers (Memory Mapped) PCI Video Decoder 0x100—Interrupt Status Register (INT_STAT) This register provides the status of pending interrupt conditions. To clear the interrupts, read this register, then write the same data back. A 1 in the write data clears the particular register bit. The interrupt /status bits can be polled at any time.

  • Page 165: 0X104-Interrupt Mask Register (Int_Mask)

    Fusion 878A 6.0 Control Register Definitions–Function 1 PCI Video Decoder 6.3 Local Registers (Memory Mapped) Bits Type Default Name Description OFLOW Set when an overflow is detected in audio A/D nominal range. Reserved Reserved Reserved 0x104—Interrupt Mask Register (INT_MASK) Bits...
  • Page 166 Fusion 878A 6.0 Control Register Definitions–Function 1 6.3 Local Registers (Memory Mapped) PCI Video Decoder Bits Type Default Name Description [21] DA_MLB Selects most significant or LSB format for ADATA 0 = MSB first for I S format 1 = LSB first for Sony format...

  • Page 167: 0X110-Audio Packet Lengths Register

    Fusion 878A 6.0 Control Register Definitions–Function 1 PCI Video Decoder 6.3 Local Registers (Memory Mapped) 0x110—Audio Packet Lengths Register Bits Type Default Name Description [23:16] 0x00 AFP_LEN Number of audio lines in an audio field: max value 255. [15:10] —...
  • Page 168 Fusion 878A 6.0 Control Register Definitions–Function 1 6.3 Local Registers (Memory Mapped) PCI Video Decoder Conexant 6-14 100600B...

  • Page 169: Parametric Information

    MUX0, MUX1, MUX2, and MUX3 Input Range — 1.00 2.00 (AC coupling required) CIN Amplitude Range (AC coupling required) — 1.00 2.00 STV, SFM, SML Input Range (AC coupling required) — — 1.00 Ambient Operating Temperature — °C Conexant 100600B...

  • Page 170: Table 7-2. Absolute Maximum Ratings

    Fusion 878A 7.0 Parametric Information 7.1 DC Electrical Parameters PCI Video Decoder Table 7-2. Absolute Maximum Ratings Parameter Symbol Units (measured to AGND) — 7.00 (measured to GND) — 7.00 — DGND – 0.5 + 0.5 Voltage on any signal pin Analog Input Voltage —...
  • Page 171 Fusion 878A 7.0 Parametric Information PCI Video Decoder 7.1 DC Electrical Parameters Table 7-3. DC Characteristics (2 of 2) Parameter Symbol Units Input High Current (V = 2.7 V — — µA Input Low Current (V = 0.5 V) —...

  • Page 172: Ac Electrical Parameters

    Fusion 878A 7.0 Parametric Information 7.2 AC Electrical Parameters PCI Video Decoder 7.2 AC Electrical Parameters AC electrical parameters are specified in Tables 7-4 through 7-7. Timing diagrams for clock, GPIO, and JTAG are provided in Figures 7-1 through 7-2, respectively.

  • Page 173: Figure 7-2. Jtag Timing Diagram

    Fusion 878A 7.0 Parametric Information PCI Video Decoder 7.2 AC Electrical Parameters Figure 7-2. JTAG Timing Diagram TDI, TMS 879A_052 Table 7-7. Decoder Performance Parameters Parameter Symbol Units ±7 Horizontal Lock Range % of Line Length ±800 Fsc, Lock-in Range Gain Range –6...

  • Page 174: Package Mechanical Drawing

    Fusion 878A 7.0 Parametric Information 7.3 Package Mechanical Drawing PCI Video Decoder 7.3 Package Mechanical Drawing Figure 7-3 provides a mechanical drawing of the 128-pin PQFP package. Figure 7-3. 128-pin PQFP Package Mechanical Drawing TOP VIEW BOTTOM VIEW ALL DIMENSIONS IN MILLIMETERS MIN.

  • Page 175: Appendix A. Acronym List

    Complementary Metal-Oxide Semiconductor Central Processing Unit Digital Audio Packetizer Digital Decimation Filter Direct Memory Access DWORD Double Word Electromagnetic Interference Electrostatic Discharge FAFULL FIFO Almost Full FIFO First In First Out Frequency Modulation Frames Per Second Frequency of Subcarrier Conexant 100600B...
  • Page 176 Fusion 878A Appendix A . Acronym List PCI Video Decoder Graphics Controller GPIO General Purpose Input/output Inter-integrated Circuit Integrated Circuit Identification IEEE Institute of Electrical and Electronic Engineers Integer International Telecommunications Union JTAG Joint Test Action Group Low Pass Filter...
  • Page 177 Fusion 878A Appendix A . Acronym List PCI Video Decoder Video Cassette Recorder VDFC Video Data Format Conversion Video Front End Vital Product Data Video Timing Controller Luminance And Chrominance Conexant 100600B...
  • Page 178 Fusion 878A Appendix A . Acronym List PCI Video Decoder Conexant 100600B...
  • Page 180 U.S. Southeast Phone: (972 9) 952 4064 Phone: (919) 858-9110 Fax: (972 9) 951 3924 Fax: (919) 858-8669 Japan Headquarters U.S. Southwest Conexant Systems Japan Co., Ltd. Phone: (949) 483-9119 Shimomoto Building Fax: (949) 483-9090 1-46-3 Hatsudai, Shibuya-ku, Tokyo APAC Headquarters 151-0061 JAPAN Conexant Systems Singapore, Pte.

Table of Contents

Save PDF