C66X Corepac - Texas Instruments TMS320C6670 Data Manual

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012

5 C66x CorePac

The C66x CorePac consists of several components:
• The C66x DSP core
• Level-one and level-two memories (L1P, L1D, L2)
• RSA accelerator (on cores 1 and 2 only)
• Data Trace Formatter (DTF)
• Embedded Trace Buffer (ETB)
• Interrupt controller
• Power-down controller
• External memory controller
• Extended memory controller
• A dedicated power/sleep controller (LPSC)
The C66x CorePac also provides support for memory protection and bandwidth management (for resources local
to the CorePac). Figure 5-1
Figure 5-1 C66x CorePac Block Diagram
Boot
Controller
PLLC LPSC
GPSC
98 C66x CorePac
shows a block diagram of the C66x CorePac.
32KB L1P
Memory Controller (PMC) With
Memory Protect/Bandwidth Mgmt
C66x DSP Core
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
In-Circuit Emulation
Instruction Decode
Data Path A
A Register File
A31-A16
A15-A0
.M1
.L1 .S1 xx .D1
xx
Data Memory Controller (DMC) With
Memory Protect/Bandwidth Mgmt
RSA
Cores 1 & 2
only
Data Path B
B Register File
B31-B16
B15-B0
.M2
.D2 xx .S2 .L2
xx
32KB L1D
Copyright 2012 Texas Instruments Incorporated
L2 Cache/
SRAM
1024KB
MSM
SRAM
2048KB
DDR3
SRAM
DMA Switch
Fabric
CFG Switch
Fabric
RSA
Cores 1 & 2
only
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