Motorola M68HC08 Manual page 28

3-Phase BLDC Low Voltage Reference Design
4.2.2 Control Algorithm Description
Designer Reference Manual
28
Freescale Semiconductor, Inc.
3-phase gate driver. The key disadvantages are the considerable
fluctuation of PWM duty cycle due to the software interrupt service and
interrupts latency; difficulties in getting PWM duty cycles close to 0 and
100% boundaries, due to the necessary software execution, and last but
not least, the MCU overloading due to the frequent highest priority PWM
interrupts at each PWM edge. As a result the technique has just a limited
use.
The second option gives more precise output control signals with the
disadvantage of more complex hardware. The PWM is generated by the
on-chip timer output compare function, and the general purpose pins
serve just to deliver the PWM to the respective input of 3-phase gate
driver. Such topology enables controlling the power stage and the BLDC
motor in independent unipolar mode, while the same PWM is always
present on one top and one bottom switch of two different phases. The
other power switches are turned off. The advantages are stable PWM
signals, possibility of generating duty cycles from 0 to 100%, and
off-loading the MCU. The draw-back is the increased hardware
complexity. This topology has been selected for the reference design of
BLDC drive.
The state of the user interface is periodically scanned, while the speed
of the motor is measured on each new coming edge from the Hall
sensors (only one phase is used for speed measurement). According to
the state of the control signals (run/stop switch, speed pot) the speed
command is calculated. The acceleration/deceleration ramp is
implemented. The comparison between the actual speed command and
the measured speed generates a speed error. This speed error is input
to the speed PI controller, that generates a new corrected PWM duty
cycle.
The Hall sensor signals are scanned independently on a speed control
loop. According to the Hall sensor signals the proper commutation vector
is selected and applied to the MCU output pins.
The PWM duty cycle value, together with commutation vector, defines
the PWM control signals for the BLDC power stage. The PWM is
3-Phase BLDC Low Voltage Reference Design
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