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11-5
11
C
90
10/11
PRESCALER
GENERAL
DESCRIPTION
-
The
11C90
is
a
high
speed
prescaler
designed
specifically for
com-
munication
and
instrumentation
applications.
It
will
divide
by
either
10
or 11
over
a
frequency
range from dc
to typically
650 MHz. The
division
ratio
is
controlled
by the
mode
control.
The
di-
vide
by
10
or 11 capability
allows the
use
of
pulse
swallowing techniques
to
control
high
speed
counting
moduios by
lower
speed
circuits.
The
1 1
C90 may
be
used
with
either
ECL
or
TTL power
supplies.
In
addition
to
the
ECL
outputs
Q4
and
Q4,
the
1
1C90
contains
an ECL-to-TTL
converter
and
a
TTL
output.
The TTL
output
operates
from
the
same
Vqq
and
Vgg
levels
as the counter, but
a
separate
pin
is
used
for
the
TTL
circuit
This
minimizes
noise coupling
when
the
TTL
output switches
and
also
allows
power
consumption
to
be reduced by
leaving the
separate
Vgg
pin
open
if
the
TTL
out-
put
is
not used.
To
facilitate
capacitive coupling
of
the
clock
signal, a
400
Q
resistor
(Vp^p)
Is
connected
internally
to
the
V33
reference.
Connecting
this resistor to
the Clock Pulse
input (CP)
automatically centers
the input
signal
about
the switching threshold.
Maximum
frequency
operation
is
achieved with
a
50%
duty
cycle.
Each
of
the
Mode
Control inputs
is
connected
to
an
internal
2
k resistor
with the other
end
uncom-
mitted
(RM-j
and RM2).
An
M
input
can be
driven
from
a
TTL
circuit
operating
from the
same
Vqq
by connecting the
free
end
of
the associated
2
k resistor
to
When
an
M
input
is
driven
from
an
ECL
circuit,
the
2
k
resistor
can be
left
open
or,
if
required,
can
be
connected
to
V33
to
act
as a
puH-down
resistor.
The
device
is
packaged
in
a
hermetic
16-pin
ceramic Dual
In-line
package.
It
is
available
in
commercial and
military
temperature
ranges.
•
VERY
HIGH
SPEED
- 650
MHz
TYPICAL
•
DIVIDE
BY
10/11
MODE
CONTROL
•
OPERATES
FROM
TTL
OR
ECL
POWER
SUPPLY
• HIGH
SPEED
TOTEM
POLE
TTL
OUTPUT -
20
mA
FAN-OUT
•
COMPLEMENTARY
ECL
OUTPUTS
DRIVE 50
Q
LINES
•
SEPARATE
TTL
GND
{Vgg) PIN
MINIMIZES NOISE
COUPLING
•
PULL-UP
RESISTORS
ON MODE CONTROL
INPUTS
FOR
TTL
COMPATIBILITY
• INTERNAL
BIASING
REFERENCE FOR
AC
COUPLED CLOCKING
• INTERNAL
50
kO
INPUT
PULL-DOWNS -
UNUSED
INPUTS
MAY
BE
LEFT
OPEN
•
COUNT
ENABLE CONTROL FOR GATED CLOCKING
•
ASYNCHRONOUS
MASTER
SET
FOR
INITIALIZING
PINJJAMES
CE
CP
Mn
MS
04,04
om
RMn
''ref
Count
Enable
Input {Active
LOW)
Clock Pulse
Input
Count Modulus
Control Input
Asynchronous Master
Set
Input
Complementary ECL
Outputs
TTL
Output
2
k Resistor to
M^
400
O
Resistor
to
V3g
LOGIC
SYMBOL
2
3
Vcc=Pin4
VgE=
Pin
12
Vee
(TTL)
=
Pin
13
CONNECTION DIAGRAM
DIP
(TOP VIEW)
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