NEC switch User Manual page 218

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T
Item
Data hold supply voltage
Release signal set time
Oscillation stabilization
Note 1
time
Notes 1. During the oscillation stabilization time, CPU operations are disabled to prevent them from becoming
unstable upon the start of oscillation.
12 15
2. 2 /f , 2 /f , or 2
X X
oscillation stabilization time selection register.
Remark f : System clock oscillation frequency
X
Data Hold timing (STOP Mode Release by RESET )
V
DD
STOP instruction execution
RESET
Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
218
CHAPTER 16 ELECTRICAL SPECIFICATIONS
Symbol Conditions
V
DDDR
t
SREL
Release by RESET
t
WAIT
Release by interrupt request
17
/f can be selected according to the setting of bits 0 to 2 (OSTS0 to OSTS2) of the
X
STOP mode
Data hold mode
V
DDDR
STOP mode
Data hold mode
V
DDDR
User's Manual U12978EJ3V0UD
= − − − − 40 to +85° ° ° ° C)
A
MIN. TYP. MAX.
4.0
0
15
2 /f
X
Note 2
Internal reset operation
HALT mode
t
SREL
t
WAIT
HALT mode
Operating mode
t
SREL
t
WAIT
Unit
5.5 V
µ s
ms
ms
Operating mode