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LSI PIN DESCRIPTION
YM3436DK (XG948E0) DIR2 (Digital Format Interface Receiver)
PIN
NAME
I/O
NO.
1
DAUX
I
Auxiliary input for audio data
2
HDLT
O
Asynchronous buffer operation flag
3
DOUT
O
Audio data output
4
VFL
O
Parity flag output
5
OPT
O
Fs x 1 Synchronous output signal for DAC
6
SYNC
O
Fs x 1 Synchronous output signal for DSP
7
MCC
O
Fs x 64 Bit clock output
8
WC
O
Fs x 1 Word clock output
9
MCB
O
Fs x 128 Bit clock output
10
MCA
O
Fs x 256 Bit clock output
11
SKSY
I
Clock synchronization control input
12
XI
I
Crystal oscillator connection or external
clock input
13
XO
O
Crystal oscillator connection
14
P256
O
VCO oscillating clock connection
15
LOCK
O
PLL lock flag
16
Vss
Logic section power (GND)
17
TC
O
PLL time constant switching output
18
DIM1
I
Data input mode selection
19
DIM0
I
Data input mode selection
20
DOM1
I
Data output mode selection
21
DOM0
I
Data output mode selection
22
KM1
I
Clock mode switching input 1
AK5392-VS-E2 (XV065A00) ADC (Analog to Digital Converter)
PIN
NAME
I/O
NO.
1
VREFL
O
L ch standard voltage output (+3.75 V)
2
GNDL
-
L ch Ground
3
VCOML
O
L ch common voltage (+2.5 V)
4
AINL+
I
L ch analog (+) input
5
AINL-
-
L ch analog (-) input
6
ZCAL
I
Zero calibration
"L": VCOML,VCOMR
"H": Analog input (AINL+/-,AINRR+/-)
7
VD
-
Power supply for digital
8
DGND
-
Ground for digital
9
CAL
O
Calibration status
10
/RST
I
Reset
11
SMODE2
I
Serial interface mode select
12
SMODE1
I
MSB first, 2's compliment
SMODE2
13
LRCK
I/O
L/R ch select clock
14
SCLK
I/O
Serial data clock
14
FUNCTION
FUNCTION
SMODE1
MODE
LRCK
L
L
Slave mode
H/L
L
H
Master mode
H/L
H
L
Slave mode
L/H
H
H
Master mode
L/H
PIN
NAME
I/O
NO.
23
RSTN
I
System reset input
24
Vdda
VCO section power (+5 V)
25
CTLN
I
VCO control input N
26
PCO
O
PLL phase comparison output
27
(NC)
28
CTLP
I
VCO control input P
29
Vssa
VCO section power (GND)
30
TSTN
I
Test terminal. Open for normal use
31
KM2
I
Clock mode switching input 2
32
KM0
I
Clock mode switching input 0
33
FS1
O
Channel status sampling frequency
display output 1
34
FS0
O
Channel status sampling frequency
display output 0
35
CSM
I
Channel status output method selection
36
EXTW
I
External synchronous auxiliary input
word clock
37
DDIN
I
EIAJ (AES/EBU) data input
38
LR
O
PLL word clock output
39
Vdd
Logic section power (+5 V)
40
ERR
O
Data error flag output
41
EMP
O
Channel status emphasis control code
output
42
CD0
O
3-wire type microcomputer interface data
output
43
CCK
I
3-wire type microcomputer interface clock
input
44
CLD
I
3-wire type microcomputer interface load
input
PIN
NAME
I/O
NO.
15
SDATA
O
Serial data output
16
FSYNC
I/O
Frame synchronization clock
17
MCLK
I
Master clock input
CMODE="H":384 fs
CMODE="L":256 fs
18
CMODE
I
Master clock select
"L": MCLK=256 fs (12.288 MHz @fs=48 kHz)
"H": MCLK=384 fs (18.432 MHz @fs=48 kHz)
19
HPFE
I
HPF enable "L": OFF "H": ON
20
TEST
I
TEST pin
Connect it with DGND.
21
BGND
-
Ground
22
AGND
-
Ground for analog
23
VA
-
Power supply for analog (+5 V)
24
AINR-
I
R ch analog (+) input
25
AINR+
I
R ch analog (-) input
26
VCOMR
O
R ch common voltage (-2.5 V)
27
GNDR
-
R ch ground
28
VREFR
O
R ch standard voltage output (+3.75 V)
MAIN: IC921, 922
FUNCTION
AD: IC105, 305, 505, 705
FUNCTION
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