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9-5. IC501 IX1697GE
Pin No.
Symbol
45
DQ
/A
15
-1
25, 24~18,
A
-A
8~4
0
12
3~15,
A
-A
48, 17
13
17
29, 31, 33,
35, 38, 40,
DQ
-DQ
0
7
42, 44
30, 32, 34, 36,
DQ
-DQ
39, 41, 43, 45
8
15
26
CE#
12
RP#
28
OE#
11
WE#
15
RY/BY#
47
BYTE#
13
Vpp
37
Vcc
27, 46
GND
9, 10, 14, 16
NC
• Block Diagram
FLASH
Type
Byte selection address: When the device is in the x8 mode, the low or high order
Input
byte is selected. It is not used in the x16 mode.
(If BYTE# is high, DQ
Word selection address: Selection of one word of 16k byte block. These addresses
Input
are latched during data wiring operation.
Block selection address: Selection of 1/32 erase block. These addresses are latched
Input
during data writing, erasing and lock block operation.
Low order byte data input/output: Command user interface writing cycle data and
Input/Output
commandinput. Various data read memory identifier and status data output Chip
nonselection or output disable: Float state
High order byte data input/output: The function is the same as that of low order byte
Input/Output
data input/output. Operative only in x16 mode. x8 mode: Float state DQ
Chip enable: Device control logic, input buffer, decoder and sense amp. are activated.
Input
Chip becomes active only when CE# is "Low".
Reset/Power down: If RP# is set to "Low", the control circuit is initialized when power is turned
on. Hence, the RP#pin is set to "Low". When power is turned on or off or in case of fluctuation
it is kept at "Low" so as to protect data from noise.
Input
When RP# is in "Low" state, the device is in deep power down state. 480 ns is required to
recover from the deep power down state. If the RP# pin becomes "Low", the whole chip
operation is interrupted and reset. After recovery the device is set to array read state.
Output enable: When OE# is set to "Low", data is output from the DQ pin. When
Input
OE# is set to "High", the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access
Input
is controlled. In "Low" state WE# becomes active. At rise edge the address and data
are fetched.
Ready/busy: The state of internal write state machine is output. In "Low" state it is
indicated that the write state machine is in operation. If the write state machine waits for
Output
next operation instruction, erase is suspended or it is in deep power down state, the RY/
BY# pin is in float state.
Byte enable: When BYTE# is set to "Low", the device is set to the x8 mode. At this
time the DQ
8
Input
byte. When BYTE# is "High", the device is set to the x16 mode. The A
disabled.
Write/erase power supply: 5.0 ± 0.5V is applied during writing/erasing.
Device power supply: 5.0 ± 0.5V
Ground
Nonconnection
DQ
8-15
Output
Buffer
Input
Buffer
Y-DECODER
ADDRESS
QUEUE
LATCHES
X-DECODER
ADDRESS
COUNTER
Name and function
/A
input circuit does not operate.)
15
-1
-DQ
pin becomes float state. Address A
15
DQ
0-7
Output
Input
Input
Buffer
Buffer
Buffer
I/O Logic
DATA
QUEUE
ID
REGISTER
Register
CSR
Register
ESRs
Data
Comparator
Y GATING/SENSING
Program Erase
Voltage Switch
25
/A
15
-1
selects high order/low order
-1
input circuit is
-1
BYTE#
CE#
OE#
WE#
RP#
RY/BY#
V
PP
V
CC
GND
DV-L70S
DV-L70BL
DV-L70W
is address.
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