Motorola MC68HC908AB32 Manuals

Manuals and User Guides for Motorola MC68HC908AB32. We have 1 Motorola MC68HC908AB32 manual available for free PDF download: Technical Data Manual

Motorola MC68HC908AB32 Technical Data Manual (392 pages)

HCMOS Microcontroller Unit

Brand: Motorola | Category: Controller | Size: 3.8 MB

Table of Contents
3
Contents
29
Section 1. General Description

30
- Introduction
  30
- Features
  30
- MCU Block Diagram
  31
- MC68HC908AB32 Block Diagram
  32
- Pin Assignments
  33
- 64-Pin QFP Pin Assignment
  33
- Pin Functions
  34
- Power Supply Pins (VDD and VSS )
  34
- Power Supply Bypassing
  34
- Oscillator Pins (OSC1 and OSC2)
  35
- External Reset Pin (RST)
  35
- External Interrupt Pin (IRQ)
  35
- Analog Power Supply Pin (VDDA )
  35
- Analog Ground Pin (VSSA )
  35
- Analog Ground Pin (AVSS /VREFL )
  35
- ADC Voltage Reference Pin (VREFH)
  36
- Analog Supply Pin (VDDAREF )
  36
- External Filter Capacitor Pin (CGMXFC)
  36
- Port a Input/Output (I/O) Pins (PTA7-PTA0)
  36
- Port B I/O Pins (PTB7/ATD7-PTB0/ATD0)
  36
- Port C I/O Pins (PTC5-PTC0)
  36
- Port D I/O Pins (PTD7-PTD0)
  37
- Port E I/O Pins (PTE7/SPSCK-Pte0/Txd)
  37
- Port F I/O Pins (PTF7-PTF0/TACH2)
  37
- Port G I/O Pins (PTG2/KBD2-PTG0/KBD0)
  37
- Port H I/O Pins (PTH1/KBD4-PTH0/KBD3)
  37
- I/O Pin Summary
  38
- I/O Pins Summary
  38
- Signal Name Conventions
  40
- Clock Source Summary
  40
- MC68HC908AB32 Rev
  40
Section 2. Memory Map

41
- Contents
  41
- Introduction
  41
- Unimplemented Memory Locations
  41
- Reserved Memory Locations
  42
- Input/Output (I/O) Section
  42
- Section 4. FLASH Memory
  43
- Memory Map
  43
- Control, Status, and Data Registers
  45
- Vector Addresses
  56
Section 2. Memory Map

57
- Contents
  57
- Introduction
  57
- Functional Description
  57
Section 3. Random-Access Memory (RAM)

57
- Contents
  59
- Introduction
  59
- Functional Description
  59
Section 4. FLASH Memory

59
- FLASH Control Register
  60
- FLASH Control Register (FLCR)
  60
- FLASH Page Erase Operation
  61
- FLASH Mass Erase Operation
  62
- FLASH Program/Read Operation
  63
- FLASH Block Protection
  64
- FLASH Programming Flowchart
  65
- FLASH Block Protect Register
  66
- FLASH Block Protect Start Address
  66
- FLASH Block Protect Register (FLBPR)
  66
- Wait Mode
  67
- Stop Mode
  67
Section 4. FLASH Memory

69
- Introduction
  69
Section 5. EEPROM

69
- Features
  70
- EEPROM I/O Register Summary
  70
- Functional Description
  71
- EEPROM Configuration
  71
- EEPROM Timebase Requirements
  72
- EEPROM Security Options
  72
- EEPROM Block Protection
  72
- EEPROM Programming and Erasing
  73
- EEPROM Array Address Blocks
  73
- EEPROM Programming
  74
- EEPROM Erasing
  75
- Low Power Modes
  76
- Wait Mode
  76
- Stop Mode
  77
- EEPROM Registers
  77
- EEPROM Control Register
  77
- EEPROM Control Register (EECR)
  77
- EEPROM Program/Erase Mode Select
  78
- EEPROM Array Configuration Register
  79
- EEPROM Array Configuration Register (EEACR)
  79
- EEPROM Non-Volatile Register
  80
- EEPROM Timebase Divider Register
  80
- EEPROM Non-Volatile Register (EENVR)
  80
- EEPROM Divider Register High (EEDIVH)
  81
- EEPROM Divider Register Low (EEDIVL)
  81
- EEPROM Timebase Divider Non-Volatile Register
  82
- EEPROM Divider Non-Volatile Register High(EEDIVHNVR)
  82
- EEPROM Divider Non-Volatile Register Low (EEDIVLNVR)
  82
Section 6. Configuration Register (CONFIG)

85
- Configuration Register 1 (CONFIG1)
  86
- Functional Description
  86
- Configuration Register 2 (CONFIG2)
  88
  - Introduction
    89
Section 7. Central Processor Unit (CPU)

89
- CPU Registers
  90
  - Features
    90
- Accumulator
  91
- CPU Registers
  91
- Accumulator (A)
  91
- Index Register
  92
- Stack Pointer
  92
- Index Register (H:X)
  92
- Program Counter
  93
- Condition Code Register
  93
- Stack Pointer (SP)
  93
- Program Counter (PC)
  93
- Condition Code Register (CCR)
  94
- Arithmetic/Logic Unit (ALU)
  96
- Low-Power Modes
  96
- Wait Mode
  96
- Stop Mode
  97
- CPU During Break Interrupts
  97
- Instruction Set Summary
  97
- Opcode Map
  97
- Instruction Set Summary
  98
- Opcode Map
  107
Section 8. System Integration Module (SIM)

109
- Contents
  109
- Introduction
  110
- Signal Naming Conventions
  111
- SIM Block Diagram
  111
- SIM Bus Clock Control and Generation
  112
- Bus Timing
  113
- Clock Start-Up from por or LVI Reset
  113
- Clocks in Stop and Wait Modes
  113
- Reset and System Initialization
  113
- External Pin Reset
  114
- Active Resets from Internal Sources
  114
- PIN Bit Set Timing
  114
- Power-On Reset
  115
- Computer Operating Properly (COP) Reset
  116
- Illegal Opcode Reset
  117
- Illegal Address Reset
  117
- Low-Voltage Inhibit (LVI) Reset
  117
- SIM Counter
  117
- SIM Counter During Power-On Reset
  118
- SIM Counter During Stop Mode Recovery
  118
- SIM Counter and Reset States
  118
- Exception Control
  118
- Interrupts
  119
- Hardware Interrupts
  120
- SWI Instruction
  121
- Vector Addresses
  122
- Reset
  123
- Break Interrupts
  123
- Status Flag Protection in Break Mode
  123
- Low-Power Modes
  124
- Wait Mode
  124
- Stop Mode
  125
- Stop Mode Entry Timing
  126
- SIM Registers
  127
- SIM Break Status Register
  127
- SIM Reset Status Register
  128
- SIM Break Flag Control Register
  129
Section 9. Clock Generator Module (CGM)

131
- Contents
  131
- Introduction
  132
- Features
  132
- Functional Description
  133
- Crystal Oscillator Circuit
  134
- Phase-Locked Loop (PLL) Circuit
  135
- PLL Circuits
  135
- Acquisition and Tracking Modes
  136
- Manual and Automatic PLL Bandwidth Modes
  136
- Programming the PLL
  138
- Special Programming Exceptions
  139
- Base Clock Selector Circuit
  140
  - CGM External Connections
    140
- CGM External Connections
  141
- I/O Signals
  142
- Crystal Amplifier Input Pin (OSC1)
  142
- Crystal Amplifier Output Pin (OSC2)
  142
- External Filter Capacitor Pin (CGMXFC)
  142
- PLL Analog Power Pin (VDDA )
  142
- MC68HC908AB32 - Rev
  142
- Oscillator Enable Signal (SIMOSCEN)
  142
  - PLL Analog Power Pin
    142
  - Dda
    142
- Crystal Output Frequency Signal (CGMXCLK)
  143
- CGM Base Clock Output (CGMOUT)
  143
- CGM CPU Interrupt (CGMINT)
  143
- CGM Registers
  143
- PLL Control Register (PCTL)
  144
- PLL Bandwidth Control Register (PBWC)
  146
- PLL Programming Register (PPG)
  148
- VCO Frequency Multiplier (N) Selection
  149
- Interrupts
  150
- Low-Power Modes
  150
- Wait Mode
  150
- Stop Mode
  151
- CGM During Break Interrupts
  151
- Acquisition/Lock Time Specifications
  151
- Acquisition/Lock Time Definitions
  152
- Parametric Influences on Reaction Time
  153
- Choosing a Filter Capacitor
  154
- Reaction Time Calculation
  155
- Contents
  157
- Introduction
  157
- Section 10. Monitor ROM (MON)
  157
Section 10. Monitor ROM (MON)

158
- Features
  158
- Functional Description
  158
- Monitor Mode Circuit
  159
- Entering Monitor Mode
  160
- Monitor Mode Entry Conditions
  160
- Data Format
  161
- Mode Differences
  161
- Echoing
  162
- Break Signal
  162
- Commands
  163
- READ (Read Memory) Command
  163
- WRITE (Write Memory) Command
  164
- IREAD (Indexed Read) Command
  164
- IWRITE (Indexed Write) Command
  165
- READSP (Read Stack Pointer) Command
  165
- Baud Rate
  166
- RUN (Run User Program) Command
  166
- Monitor Baud Rate Selection
  166
- Security
  167
- Extended Security
  168
- Contents
  169
- Section 11. Timer Interface Module a (TIMA)
  169
- Section 11. Timer Interface Module a (TIMA)
  
  170
  - Features
    170
  - Introduction
    170
  - Functional Description
    171
  - Pin Name Conventions
    171
  - TIMA Counter Prescaler
    171
  - TIMA Block Diagram
    172
  - TIMA I/O Register Summary
    173
  - Input Capture
    174
  - Output Compare
    175
  - Unbuffered Output Compare
    175
  - Buffered Output Compare
    176
  - Pulse Width Modulation (PWM)
    177
  - Unbuffered PWM Signal Generation
    178
  - Buffered PWM Signal Generation
    179
  - PWM Initialization
    180
  - Interrupts
    181
  - Low-Power Modes
    181
  - Stop Mode
    182
  - TIMA During Break Interrupts
    182
  - Wait Mode
    182
  - I/O Signals
    183
  - TIMA Channel I/O Pins
    183
  - TIMA Clock Pin
    183
  - I/O Registers
    184
  - TIMA Status and Control Register
    184
  - Prescaler Selection
    186
  - TIMA Counter Registers
    186
  - TIMA Counter Modulo Registers
    187
  - TIMA Channel Status and Control Registers
    188
  - TIMA Channel 2 Status and Control Register (TASC2)
    189
  - Mode, Edge, and Level Selection
    191
  - TIMA Channel Registers
    192
  - TIMA Channel 1 Register High (TACH1H)
    193
  - TIMA Channel 3 Register High (TACH3H)
    194
- Section 12. Timer Interface Module B (TIMB)
  
  195
  - Contents
    195
  - Features
    196
  - Introduction
    196
  - Functional Description
    197
  - Pin Name Conventions
    197
  - TIMB Counter Prescaler
    197
  - TIMB Block Diagram
    198
  - TIMB I/O Register Summary
    199
  - Input Capture
    200
  - Output Compare
    201
  - Unbuffered Output Compare
    201
  - Buffered Output Compare
    202
  - Pulse Width Modulation (PWM)
    203
  - Unbuffered PWM Signal Generation
    204
  - Buffered PWM Signal Generation
    205
  - PWM Initialization
    206
  - Interrupts
    207
  - Low-Power Modes
    207
  - Stop Mode
    208
  - TIMB During Break Interrupts
    208
  - Wait Mode
    208
  - I/O Signals
    209
  - TIMB Channel I/O Pins
    209
  - TIMB Clock Pin
    209
  - I/O Registers
    210
  - TIMB Status and Control Register
    210
  - TIMB Counter Registers
    212
  - TIMB Counter Modulo Registers
    213
  - TIMB Channel Status and Control Registers
    214
  - TIMB Channel 2 Status and Control Register (TBSC2)
    215
  - Mode, Edge, and Level Selection
    217
  - TIMB Channel Registers
    218
  - TIMB Channel 1 Register High (TBCH1H)
    219
  - TIMB Channel 3 Register High (TBCH3H)
    220
  - Contents
    221
  - Introduction
    221
Section 13. Programmable Interrupt Timer (PIT)

221
- Features
  222
- Functional Description
  222
- PIT Counter Prescaler
  223
- Low-Power Modes
  224
- PIT During Break Interrupts
  224
- Stop Mode
  224
- Wait Mode
  224
- I/O Registers
  225
- PIT Status and Control Register
  225
- PIT Counter Registers
  227
- PIT Counter Modulo Registers
  228
- Contents
  229
Section 14. Analog-To-Digital Converter (ADC)

229
- Features
  230
- Introduction
  230
- Functional Description
  231
- ADC Port I/O Pins
  232
- Conversion
  232
- Conversion Time
  232
- Voltage Conversion
  232
- Accuracy and Precision
  233
- I/O Signals
  233
- Interrupts
  233
- Low-Power Modes
  233
- Stop Mode
  233
- Wait Mode
  233
- ADC Analog Ground Pin (AVSS /V REFL )
  234
- ADC Analog Power Pin
  234
- ADC Voltage in
  234
- ADC Voltage Reference High Pin
  234
- Adin )
  234
- Ddaref
  234
- I/O Registers
  234
- Refh )
  234
- ADC Status and Control Register (ADSCR)
  235
- Mux Channel Select
  236
- ADC Clock Register (ADCLK)
  237
- ADC Data Register (ADR)
  237
- ADC Clock Divide Ratio
  238
Section 15. Serial Communications Interface

239
Section 14. Analog-To-Digital Converter (ADC)

239
- Contents
  239
Module (SCI)

239
- Features
  240
- Introduction
  240
- Functional Description
  242
- Pin Name Conventions
  242
- SCI Module Block Diagram
  243
- SCI I/O Register Summary
  244
- Data Format
  245
- Transmitter
  245
- SCI Transmitter
  246
- Character Length
  247
- Character Transmission
  247
- Break Characters
  248
- Idle Characters
  248
- Inversion of Transmitted Output
  249
- Transmitter Interrupts
  249
- Character Length
  250
- Character Reception
  250
- Receiver
  250
- SCI Receiver Block Diagram
  251
- Data Sampling
  252
- Start Bit Verification
  253
- Baud Rate Tolerance
  254
- Framing Errors
  254
- Slow Data
  255
- Fast Data
  256
- Receiver Wakeup
  257
- Error Interrupts
  258
- Receiver Interrupts
  258
- Low-Power Modes
  259
- MC68HC908AB32 - Rev
  259
- Stop Mode
  259
- Wait Mode
  259
- I/O Signals
  260
- Pte0/Txd (Transmit Data)
  260
- Pte1/Rxd (Receive Data)
  260
- SCI During Break Module Interrupts
  260
- I/O Registers
  261
- SCI Control Register 1
  261
- SCI Control Register 1 (SCC1)
  262
- SCI Control Register 2
  264
- SCI Control Register 2 (SCC2)
  265
- SCI Control Register 3
  267
- SCI Status Register 1
  269
- Flag Clearing Sequence
  272
- SCI Status Register 2
  273
- SCI Data Register
  274
- SCI Baud Rate Register
  275
- SCI Baud Rate Selection
  276
- SCI Baud Rate Selection Examples
  277
- Contents
  279
Section 16. Serial Peripheral Interface Module (SPI)

279
- Features
  280
- Introduction
  280
- Functional Description
  281
- Pin Name Conventions and I/O Register Addresses
  281
- SPI Module Block Diagram
  282
- Master Mode
  283
- Slave Mode
  284
- Clock Phase and Polarity Controls
  285
- Transmission Formats
  285
- Transmission Format When CPHA = 0
  286
- Transmission Format (CPHA = 0)
  287
- Transmission Format When CPHA = 1
  288
- Transmission Initiation Latency
  289
- Transmission Start Delay (Master)
  290
- Queuing Transmission Data
  291
- Error Conditions
  292
- Overflow Error
  292
- Missed Read of Overflow Condition
  293
- Mode Fault Error
  294
- Interrupts
  296
- SPI Interrupt Request Generation
  297
- Resetting the SPI
  298
- Low-Power Modes
  299
- Stop Mode
  299
- Wait Mode
  299
- I/O Signals
  300
- SPI During Break Interrupts
  300
- MISO (Master In/Slave Out)
  301
- MOSI (Master Out/Slave In)
  301
- SPSCK (Serial Clock)
  302
- SS (Slave Select)
  302
- CGND (Clock Ground)
  303
- I/O Registers
  304
- SPI Control Register
  304
- SPI Status and Control Register
  306
- SPI Master Baud Rate Selection
  308
- SPI Data Register
  309
- Contents
  311
Section 17. Input/Output (I/O) Ports

311
- Introduction
  312
- Port Control Register Bits Summary
  314
- Data Direction Register a (DDRA)
  316
- Port a
  316
- Port a Data Register (PTA)
  316
- Port a I/O Circuit
  317
- Port B
  318
- Port B Data Register (PTB)
  318
- Data Direction Register B (DDRB)
  319
- Port C
  320
- Port C Data Register (PTC)
  320
- Data Direction Register C (DDRC)
  321
- Port C I/O Circuit
  322
- Port D
  323
- Port D Data Register (PTD)
  323
- Data Direction Register D (DDRD)
  324
- Port D Input Pullup Enable Register (PTDPUE)
  325
- Port E
  326
- Port E Data Register (PTE)
  326
- Data Direction Register E (DDRE)
  328
- Port F
  329
- Port F Data Register (PTF)
  329
- Data Direction Register F (DDRF)
  330
- Port F I/O Circuit
  331
- Port F Input Pullup Enable Register (PTFPUE)
  332
- Port G
  332
- Port G Data Register (PTG)
  332
- Data Direction Register G (DDRG)
  333
- Port G I/O Circuit
  334
- Data Direction Register H (DDRH)
  335
- Port H
  335
- Port H Data Register (PTH)
  335
- Data Direction Register H (DDRH)
  336
- Port H Pin Functions
  337
- Contents
  339
- Features
  339
- Introduction
  339
Section 18. External Interrupt (IRQ)

339
- Functional Description
  340
- IRQ Module Block Diagram
  341
- IRQ Pin
  342
- IRQ Status and Control Register (ISCR)
  343
- IRQ Module During Break Interrupts
  344
- Contents
  345
- Introduction
  345
Section 19. Keyboard Interrupt Module (KBI)

345
- Features
  346
- I/O Pins
  346
- Functional Description
  347
- Keyboard Initialization
  349
- Keyboard Status and Control Register
  349
- Keyboard Status and Control Register (KBSCR)
  350
- Keyboard Interrupt Enable Register
  351
- Stop Mode
  351
- Wait Mode
  351
- Keyboard Module During Break Interrupts
  352
- Introduction
  353
Section 20. Computer Operating Properly (COP)

353
- Functional Description
  354
- Cgmxclk
  355
- COPCTL Write
  355
- I/O Signals
  355
- Power-On Reset
  355
- STOP Instruction
  355
- COPD (COP Disable)
  356
- COPRS (COP Rate Select)
  356
- Internal Reset
  356
- Reset Vector Fetch
  356
- COP Control Register
  357
- Interrupts
  357
- Low-Power Modes
  357
- Monitor Mode
  357
- COP Module During Break Mode
  358
- Stop Mode
  358
- Wait Mode
  358
Section 20. Computer Operating Properly (COP)

359
- Contents
  359
- Features
  359
- Introduction
  359
- MC68HC908AB32 - Rev
  359
Section 21. Low-Voltage Inhibit (LVI)

359
- Functional Description
  360
- False Reset Protection
  361
- Forced Reset Operation
  361
- Polled LVI Operation
  361
- LVI Interrupts
  362
- LVI Status Register (LVISR)
  362
- Low-Power Modes
  363
- Stop Mode
  363
- Wait Mode
  363
- Contents
  365
- Introduction
  365
Section 22. Break Module (BRK)

365
- Features
  366
- Functional Description
  366
- Break Module Block Diagram
  367
- COP During Break Interrupts
  368
- CPU During Break Interrupts
  368
- Flag Protection During Break Interrupts
  368
- Low-Power Modes
  368
- PIT, TIMA, and TIMB During Break Interrupts
  368
- Wait Mode
  368
- Break Module Registers
  369
- Break Status and Control Register
  369
- Stop Mode
  369
- Break Address Registers
  370
- SIM Break Status Register
  370
- SIM Break Status Register (SBSR)
  371
- SIM Break Flag Control Register
  372
  - Introduction
    373
Section 23. Electrical Specifications

373
- Absolute Maximum Ratings
  374
- Functional Operating Range
  375
- Thermal Characteristics
  375
- V DC Electrical Characteristics
  376
- EEPROM and Memory Characteristics
  377
- Timer Interface Module Characteristics
  378
- V Control Timing
  378
- ADC Characteristics
  379
- SPI Characteristics
  380
- SPI Master Timing
  381
- SPI Slave Timing
  382
- CGM Component Information
  383
- CGM Operating Conditions
  383
- Clock Generation Module Characteristics
  383
- CGM Acquisition/Lock Time Information
  384
- FLASH Memory Characteristics
  385
- Contents
  387
- Introduction
  387
Section 24. Mechanical Specifications

387
- 64-Pin Plastic Quad Flat Pack (QFP)
  388
Section 25. Ordering Information

389

Motorola Categories

Cell Phone Two-Way Radio Baby Monitor

Cordless Telephone Radio

More Motorola Manuals

Motorola MC68HC908AB32 Manuals

Motorola MC68HC908AB32 Technical Data Manual (392 pages)

Table of Contents

Section 1. General Description

Section 2. Memory Map

Section 2. Memory Map

Section 3. Random-Access Memory (RAM)

Section 4. FLASH Memory

Section 4. FLASH Memory

Section 5. EEPROM

Section 6. Configuration Register (CONFIG)

Section 7. Central Processor Unit (CPU)

Section 8. System Integration Module (SIM)

Section 9. Clock Generator Module (CGM)

Section 10. Monitor ROM (MON)

Section 11. Timer Interface Module a (TIMA)

Section 12. Timer Interface Module B (TIMB)

Section 13. Programmable Interrupt Timer (PIT)

Section 14. Analog-To-Digital Converter (ADC)

Section 15. Serial Communications Interface

Section 14. Analog-To-Digital Converter (ADC)

Module (SCI)

Section 16. Serial Peripheral Interface Module (SPI)

Section 17. Input/Output (I/O) Ports

Section 18. External Interrupt (IRQ)

Section 19. Keyboard Interrupt Module (KBI)

Section 20. Computer Operating Properly (COP)

Section 20. Computer Operating Properly (COP)

Section 21. Low-Voltage Inhibit (LVI)

Section 22. Break Module (BRK)

Section 23. Electrical Specifications

Section 24. Mechanical Specifications

Section 25. Ordering Information

Related Products

Motorola Categories