NEC Barracuda Service Manual page 14

Barracuda PDA Maintenance
The line clock toggles after all pixels in a line have been transmitted to the LCD driver and a programmable
number of pixel clock wait states have elapsed both at the beginning and end of each line. In passive mode,
the frame clock is asserted during the first line of the screen. In active mode, the frame clock is asserted
at the beginning of each frame after a programmable number of line clock wait states occur. In passive
display mode, the pixel clock does nit transition when the line clock is asserted. However, in active display
mode, the pixel clock transitions continuously and the ac bias bin used as an output enable to signal when
valid pixels are present on the LCD's data lines. In passive mode, the ac bias pin can be configured to
transition each time a programmable number of line clocks have elapsed to signal the display to reverse the
polarity of its voltage to counteract DC offset in the screen.
LCD Controller Operation
The LCD controller supports a variety of user-programmable options including display type and size frame
buffer, encoded pixel size, and output data width. Although all programmable combinations are possible,
the selection of displays available within the market dictate which combinations of these programmable
options are practical. The type of external memory system implemented by the user limits the bandwidth
of the LCD's DMA controller, which, in turn, limits the size and type of screen that can be controlled. The
user must also determine the maximum bandwidth of the SA-1110's external bus that the LCD is allowed
to use without negatively affecting all other functions that the SA-1110 must perform. Note that the LCD's
DMA engine has highest priority on the SA-1110's internal data bus structure ( ARM system bus ) and
can "starve" other masters on the bus, including the CPU.
The following sections describe individual functional blocks within the LCD controller, frame buffer and
palette memory organization, and the LCD's DMA controller. The sections are arranged in order of data
flow, starting with the off-chip frame buffer and ending with the pins that interface to the LCD display.
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