Motorola CPU32 Reference Manual page 9

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Number
6.2.10
6.2.11
6.2.12
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.2
6.3.2.1
6.3.2.2
6.3.2.3
6.3.2.4
6.3.2.5
6.3.2.6
6.3.2.7
6.4
6.4.1
6.4.2
6.4.3
7.1
7.1.1
7.1.2
7.1.3
7.2
7.2.1
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.3
7.2.4
7.2.5
7.2.5.1
7.2.5.2
7.2.5.3
7.2.6
7.2.7
7.2.7.1
MOTOROLA
viii
TABLE OF CONTENTS (Continued)
Title
Page
Number
Tracing ...................................................................................................... 6-13
Interrupts .................................................................................................. 6-14
Return from Exception ........................................................................... 6-16
Fault Recovery ........................................................................................ 6-17
Types of Faults ........................................................................................ 6-19
Type I: Released Write Faults ......................................................... 6-20
Type II: Prefetch, Operand, RMW, and MOVEP Faults ............... 6-20
Type III: Faults During MOVEM Operand Transfers ................... 6-21
Type IV: Faults During Exception Processing ............................. 6-22
Correcting a Fault ................................................................................... 6-22
(Type I) Completing Released Writes via Software ..................... 6-23
(Type I) Completing Released Writes via RTE ............................. 6-23
(Type II) Correcting Faults via RTE ................................................. 6-24
(Type III) Correcting Faults via Software ....................................... 6-24
(Type III) Correcting Faults by Conversion and Restart .............. 6-25
(Type III) Correcting Faults via RTE ................................................ 6-25
(Type IV) Correcting Faults via Software ....................................... 6-25
CPU32 Stack Frames ................................................................................ 6-26
Normal Four-Word Stack Frame .......................................................... 6-26
Normal Six-Word Stack Frame ............................................................ 6-27
BERR Stack Frame ................................................................................. 6-27
Section 7
Development Support
CPU32 Integrated Development Support .............................................. 7-1
Background Debug Mode (BDM) Overview ...................................... 7-1
Deterministic Opcode Tracking Overview .......................................... 7-2
On-Chip Hardware Breakpoint Overview .......................................... 7-3
Background Debug Mode (80M) ............................................................ 7-3
Enabling BDM ......................................................................................... 7-4
BDM Sources .......................................................................................... 7-4
External BKPT Signal ....................................................................... 7-5
BGND Instruction ............................................................................... 7-5
Double Bus Faults ............................................................................. 7-5
Peripheral Breakpoints ..................................................................... 7-5
Entering BDM .......................................................................................... 7-5
Command EXecution ............................................................................. 7-6
Background Mode Registers ................................................................ 7-6
Fault Address Register (FAR) ......................................................... .7-6
Return Program Counter (RPC) ..................................................... .7-6
Current Instruction Program Counter (PCC) ................................. 7-8
Returning from BDM ............................................................................... 7-8
Serial Interface ........................................................................................ 7-8
CPU Serial Logic ............................................................................... 7-10
CPU32 REFERENCE MANUAL