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12
V. BLOCK DIAGRAM DESCRIPTION
1. Input channels A and B
The PM 6650 has two identical input channels A and
B, consisting
of input conditioning
circuits
operated
with
front
panel
controls
ATT.,
COUPLING,
and
SLOPE.
An amplifier and trigger circuit shapes
the
signal which
is routed to the Function
Selector. The
desired triggering
level can
be set with front panel
control LEVEL and is accessible at output LEVEL OUT
at the front and rear panels.
2. Input channel C
Channels C contains an automatic gain control circuit
which
keeps the output signal at an
optimum
level
independent of the input amplitude. This signal is also
fed to the Function Selector.
3. 10 MHz clock oscillator
The internal 10 MHz
clock signal is fed through the
external/internal selector circuit to the Function Selec-
tor. If an external clock is used, the internal clock is
disconnected.
4. Function Selector
In general,
two
signals
are
routed
to the Function
Selector:
the input signal from channels A, B, or C,
and the clock signal. One of the signals is used to
control the main gate. The first pulse of the control
signal will open the gate allowing the other signal to
pass through until the next pulse of the control signal
is closing
the gate.
The
information
from
the
last
counting interval is stored in the memories during the
new counting interval.
When
the main
gate is closed,
the control
circuits
generates a transfer pulse enabling the new informa-
tion to pass on to the display. After the set display
time, the decade counters are reset and a new meas-
urement can start.
At time interval measurement,
the start signal applied
to channel A and the stop signal applied at channel B
control the main gate via the Function
Selector. The
10 MHz
clock signal
is multiplied to 100 MHz
and
counted during the start to stop interval.
5. Frequency dividers
At frequency measurement, the clock signal is scaled
in the frequency dividers as determined
by the TIME
BASE switch. The scaled signal controls the main gate
and the input signal
applied
to channel
A or C is
counted during the set gate time interval.
At period measurement,
the signal from input A con-
trols the main gate directly. The clock signal is multi-
plied to
100
MHz
and
is scaled
in the frequency
dividers. The scaling factor is set with the MULTIPLIER
switch. The scaled
signal is then counted
during an
interval determined. by the input A signal.
In period averaging
situations, the A signal is scaled
in the frequency dividers and used to control the main
gate. The
10 MHz
clock signal
is multiplied to 100
MHz and counted during an interval determined by the
scaled input signal.
6. Decade counters, memories
and display
The fastest HF decade
provides the most significant
digit to the memories and the TTL decades the remain-
ing digits in parallel form. The
memories
are
shift
registers which
convert
the parallel
information
into
serial form for the decoder drivers and the display.
7. Time interval average synchronizer
The
synchronizer
provides
bursts
of clock
pulses
which
are counted
during a time determined
by the
MULTIPLIER switch. The number of clock pulses within
each burst corresponds
to the average time interval
between
signals A and
B. The
MULTIPLIER
setting
represents the number of averagings selected.
A detailed description is given in the Service Manual.
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