Cosr Codec Receive Overrun Error Flag Bit (Croe) Bit 1; Cosr Codec Transmit Data Empty Bit (Ctde) Bit 2; Cosr Codec Receive Data Full Bit (Crdf) Bit 3; Cosr Reserved Bits (Bits 4-15) - Motorola DSP56156 Manual

INTERFACE WITH THE DSP56156 CORE PROCESSOR
6.4.6.2

COSR Codec Receive Overrun Error Flag Bit (CROE) Bit 1

The Codec Receive Overrun Error Flag bit is set when a new sample is received from the
codec section while the previous received sample in the CRX receive register has not
been read by the DSP (overrun error). In this case, the previous received sample is over-
written in the CRX register.
Hardware and software reset and STOP reset clear CROE. CROE is also cleared by read-
ing the COSR with CROE set followed by reading CRX. Clearing the COE bit in the COCR
does not affect CTUE.
6.4.6.3

COSR Codec Transmit Data Empty Bit (CTDE) Bit 2

The Codec Transmit Data Empty (CTDE) bit indicates that the D/A Transmit register CTX
is empty and can be written by the DSP. CTDE is set when the CTX register is transferred
to the D/A comb filter input. CTDE is cleared when the CTX register is written by the DSP.
CTDE is also set entering the Codec power down mode (COE cleared) and by a DSP re-
set (Hardware RESET and RESET instruction) and STOP reset.
6.4.6.4

COSR Codec Receive Data Full Bit (CRDF) Bit 3

The Codec Receive Data Full (CRDF) bit indicates that the A/D Data Receive register
CRX contains data from the codec A/D section. CRDF is set when data is transferred from
the A/D comb filter output to the CRX register. CRDF is cleared when the CRX Register
is read by the DSP. CRDF is also cleared entering the Codec power down mode (COE
cleared), by a DSP reset (Hardware RESET and RESET instruction) and STOP reset.
6.4.6.5

COSR Reserved Bits (Bits 4-15)

These bits are reserved. They should be written as zero by the user program and will read
as zero.
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