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Transmit buffer empty interrupt
To use this interrupt, set TINTE/I2CM_ICTL register to 1. If TINTE is set to 0 (default), interrupt requests for
this cause will not be sent to the ITC.
If transmit buffer empty interrupts are enabled (TINTE = 1), an interrupt request is output to the ITC as soon as
the transmit data set in RTDT[7:0]/I2CM_DAT register is transferred to the shift register.
The transmit buffer empty interrupt will only occur during data transmission.
To clear the cause of transmit buffer empty interrupt
The cause of transmit buffer empty interrupt can be cleared by writing data to RTDT[7:0]/I2CM_DAT reg-
ister. If TXE/I2CM_DAT register is set to 0 at the same time, I2CM only clear the cause of interrupt with-
out sending the data written.
Receive buffer full interrupt
To use this interrupt, set RINTE/I2CM_ICTL register to 1. If RINTE is set to 0 (default), interrupt requests for
this cause will not be sent to the ITC.
If receive buffer full interrupts are enabled (RINTE = 1), an interrupt request is output to the ITC as soon as the
data received in the shift register is loaded to RTDT[7:0].
The receive buffer full interrupt will only occur during data reception.
To clear the cause of receive buffer full interrupt
The cause of receive buffer full interrupt can be cleared by reading data from RTDT[7:0]/I2CM_DAT regis-
ter.
note: After an I2CM interrupt occurs, determine whether a transmit buffer empty interrupt or a receive
buffer full interrupt has occurred according to the I
executed at that time. Note that it cannot be checked using a register.
For more information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
20.7
Control Register Details
address
0x4340
I2CM_EN
I
2
C Master Enable Register
0x4342
I2CM_CTL
I
2
C Master Control Register
0x4344
I2CM_DAT
I
C Master Data Register
2
0x4346
I2CM_ICTL
I
2
C Master Interrupt Control Register
The I2CM module registers are described in detail below. These are 16-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
i
C Master enable Register (i2CM_en)
2
Register name address
Bit
i
2
C Master en-
0x4340
D15–1 –
able Register
(16 bits)
(i2CM_en)
D0
D[15:1]
Reserved
D0
i2CMen: i
2
C Master enable Bit
Enables or disables I2CM module operation.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting I2CMEN to 1 starts the I2CM module operation, enabling data transfer. Setting I2CMEN to 0
stops the I2CM module operation.
S1C17624/604/622/602/621 TeChniCal Manual
Table 20.
7.1 List of I2CM Registers
Register name
name
Function
reserved
i2CMen
I
2
C master enable
Seiko epson Corporation
C master transmit/receive processing being
2
Function
Enables the I
2
C master module.
Controls the I
2
C master operation and indicates transfer status.
Transmit/receive data
Controls the I
2
C master interrupt.
Setting
–
1 Enable
0 Disable
2
20 i
C MaSTeR (i2CM)
init. R/W
Remarks
–
–
0 when being read.
0
R/W
20-7
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