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A 74 HC 4046 Phase Lock Loop
(
IC 1 C
)
is used for
determining
whether an unlock condition
exists
,
connected to
a
74 HC 123
one shot
(
monostable multivibrator
)
whose output drives a
D
-
flip
/
flop
( IC 5 CA
-
74 HC 74 )
.
UNLOCK LED
is driven
from the D
-
flip
/
flop output
.
The error output is
The
Central
Processing
Unit
(
CPU
) Board Overview
4.5
.
13
The CPU board is the system
controller for the APR
-
5000
Series
Tape Machines
.
It communicates directly with the
Transport
Control Panel
(
Function Block
) KBD
assembly for
LOCAL commands and status indication
.
Remote Control
input
comes from the
LNT (
originating
at the CNX board )
.
Audio
system
communication
is
also done
via the
LNT board
.
A
major
upgrade to the assembly has been performed with the inception
of the
APR
-
5003 V
machine and has been
incorporated on
all
APR
-
5000
Series
machines
.
The newer CPU
assembly
has a PROM
in
the IC 11 location
.
The previous assembly
(
which can not
accommodate the SERIAL REMOTE upgrade
)
utilizes a 74 HC 138 in
the IC 11 location
.
4.5
.
13.1
CPU
Operating Principles
The transport CPU manages all of the tasks and functions of
the
tape machine
.
It addresses
,
reads and
writes data to all
portions
of the machine
.
Several
major
complex functions are
carried out on the CPU Board itself
.
This reduces the
external harnessing and bus
activity
,
and
provides
flexibility
in the design
.
This board is a
"
Dedicated
Process Controller
"
;
a small computer specifically designed
to operate an audio tape
machine
in
a modern recording
environment
.
4.5
.
13.2
Central
Processing
Unit
(
CPU
) Circuit
Description
IC 1
is
the Z 8002 16
-
bit CPU chip
,
pass
through this device
,
perlpherals
.
on the data gathered by the peripherals
,
and commands the
performance
of the transport interface circuits
.
All data bus
transactions
It
calculates
the addresses of all
It
performs logical and mathematical functions
IC 2 , IC 3
,
IC 4 and IC 5
perform
several functions
with most of
these gates employed
by memory
control functions
.
The
logic
network formed by these gates activates ROM or
RAM (
or
RWM )
.
It determines if a
memory
transaction is an even byte
,
an odd
byte
,
or a word
,
a read
,
or a write
.
IC 5 has the additional
function of enabling or disabling
the read / write
memory
4
-
38
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