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Important Note - Fujitsu CPU369-Module Documentation

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Header for Debug Signals
Power supply voltage (JP1, JP2, JP3, JP4, JP5, JP6)
JP1
JP2
JP3
JP4
JP5
JP6
MCU Peripheral Signals
Peripheral_1
BUS_PH7-0
BUS_PG7-0
ALARM
BUS_PK7-4
Peripheral_2
PM0
PM1
BUS_PN5-0
BUS_PO7-0
PQ5-2

IMPORTANT NOTE :

Some of the Pins of Peripheral_1 and Peripheral_2 are not connected ! This is because the original CPU
board was designed for the MCU MB91F362 and this MCU has some additional resources (e.g. stepper-
motor drivers, more ADC channels etc.). Please refer to the attached schematics which pins are left open.
Refer to the next chapter 3.9 Pin Assignment of Peripheral Jumpers for details which of the pins are not
connected !
- 12V – GND
- 5V – GND
- 3.3V – GND
- 2.5_1V – GND
- 2.5_2V – GND
- 2.5_3V – GND
- A/D Converter input [7:0]
- A/D Converter input [9:8]
- Alarm comparator input
- External Interrupt [7:4]
- Sound Generator SGO
- Sound Generator SGA
- Serial I/O Interface signals (SOT3-4, SIN3-4, SCK3-4)
- PPG output [7:0]
- Serial I/O Interface signals (SOT1-2, SIN1-2)
separated voltage
separated voltage
9

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