LG CED-8042B Manual page 15

Pin No. Symbol
41 DA08 O
42 DA07 O
43 DV 2
DD
44 DA06 O
45 DA05 O
46 DA04 O
47 DA03 O
48 DA02 O
49 DA01 O
50 DV 2
SS
51 XTSL I
52 MCKO O
57 FSTIO I/O
58 C4M O
59 C16M O
60 DV 3
DD
61 MD2 I
62 DOUT O
63 MUTE I
64 WFCK O
65 SCOR O
66 SBSO O
67 EXCK I
68 SQSO O
69 SQCK I
70 SCSY I
71 XRST I
74 XWO I
75 RMUTO O
76 LMUTO O
77 DV 3
SS
78 AV 4
SS
79 PWMRN O
80 PWMRP O
38
I/O
1, 0 Outputs DA8 when PSSL=1, or GFS when PSSL=0.
1, 0 Outputs DA7 when PSSL=1, or RFCK when PSSL=0.
Digital Power supply
1, 0 Outputs DA6 when PSSL=1, or C2PO when PSSL=0.
1, 0 Outputs DA5 when PSSL=1, or XRAOF when PSSL=0.
1, 0 Outputs DA4 when PSSL=1, or MNT3 when PSSL=0.
1, 0 Outputs DA3 when PSSL=1, or MNT2 when PSSL=0.
1, 0 Outputs DA2 when PSSL=1, or MNT1 when PSSL=0.
1, 0 Outputs DA1 when PSSL=1, or MNT0 when PSSL=0.
Digital GND
X'tal selection input
1, 0 Clock output. Inverse output of XTLI
1, 0 Clock input/output for Digital servo
(2/3 frequency demultiplication input of XTLI)
1, 0 1/4 frequency demultiplication output of XTLI. Affected by vari-pitch
1, 0 16.9344MHz output. Subject to vari-pitch control.
Digital power supply
Digital-Out ON/OFF control. "H" for ON, "L" for OFF.
1, 0 Digital-Out output.
"H" for muting, "L" for release.
1, 0 WFCK (Write Frame Clock) output
1, 0 "H" when subcode Sync S0 or S1 is detected.
1, 0 Serial output of Sub P to W
Clock input for reading SBSO
1, 0 Outputs 80-bit Sub Q and 16-bit PCM peak-level data.
Clock input for reading SQSO
Input of GRSCOR
System reset. "L" for resetting
Window open input for DAC synchronization. Generally, at "L" window open
1, 0 Audio DAC, zero detecting block for R channel
1, 0 Audio DAC, zero detecting block for L channel
Digital GND
Analog GND
1, Z, 0 PWM output for Audio DAC, R channel, Reverse phase
1, Z, 0 PWM output for Audio DAC, R channel
Description