Pci Power Management Interrupt Mask Register (Pcipintm) - Hitachi SH7751 Hardware Manual

22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM)

Bit: 31
—
Initial value: 0
PCI-R/W: —
PP Bus-R/W: R
Bit: 7
—
Initial value: 0
PCI-R/W: —
PP Bus-R/W: R
The PCI power management interrupt mask register (PCIPINTM) sets the interrupt mask for the
power management interrupts. This 32-bit read/write register can be accessed from the PP bus.
The PCIPINTM register is initialized to H'00000000 at a power-on reset. It is not initialized at a
software reset.
Interrupt masks can be set for both the interrupt for a transition to the power state D3 (power down
mode) and recovery to the power state D0 (normal status). Setting the respective bit to 0 disables
the interrupt and setting it to 1 enables the interrupt.
Bits 31 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 1—Power State D3 (PWRST_D3): Transition request to power-down mode interrupt mask
for SH7751 and SH7751R.
Bit 0—Power State D0 (PWRST_D0): Restore from power-down mode interrupt mask for
SH7751 and SH7751R.
30 29 . . .
— — . . .
0 0 . . .
— — . . .
R R . . .
6 5
— —
0 0
— —
R R
11 10
—
0
—
R
4 3
— —
0 0
— —
R R
Rev. 3.0, 04/02, page 871 of 1064
9
— — —
0 0
— — —
R R
2 1
— DPERR_ DPERR_
WT RD
0 0
— — —
R R/W R/W
8
0
R
0
0