Interrupt Control Register (Icrnx); Icrnx Field Descriptions; Interrupt Source Assignment For Intc0 - Motorola ColdFire MCF5281 User Manual

Register Descriptions
Field
Reset
R/W
Address
Figure 10-9. Interrupt Control Register (ICRnx)
Bits Name
7–6 — Reserved, should be cleared.
5–3 IL Interrupt level. Indicates the interrupt level assigned to each interrupt input.
2–0 IP Interrupt priority. Indicates the interrupt priority for internal modules within the interrupt-level
assignment. 000b represents the lowest priority and 111b represents the highest. For the fixed level
interrupt sources, the priority is fixed at the midpoint for the level, and the IP field will always read as
000b.
10.3.6.1 Interrupt Sources
Table 10-13 and Table 10-14 list the interrupt sources for each interrupt request line for
INTC0 and INTC1.
Table 10-13. Interrupt Source Assignment for INTC0
Source Module Flag
1 EPORT EPF1
2 EPF2
3 EPF3
4 EPF4
5 EPF5
6 EPF6
7 EPF7
8 SCM SWT1
9 DMA DONE
10 DONE
11 DONE
12 DONE
13 UART0 Multiple
14 UART1 Multiple
15 UART2 Multiple
10-12
7 6 5
—
R/W (Read only for ICRn1-ICRn7)
See Table 10-2 and Table 10-3 for register offsets
Table 10-12. ICRnx Field Descriptions
Source Description
Edge port flag 1
Edge port flag 2
Edge port flag 3
Edge port flag 4
Edge port flag 5
Edge port flag 6
Edge port flag 7
Software watchdog timeout
DMA Channel 0 transfer complete Write DONE = 1
DMA Channel 1 transfer complete Write DONE = 1
DMA Channel 2 transfer complete Write DONE = 1
DMA Channel 3 transfer complete Write DONE = 1
UART0 interrupt
UART1 interrupt
UART2 interrupt
MCF5282 User's Manual
3 2
IL
0000_0000
Description
Flag Clearing Mechanism
Write EPF1 = 1
Write EPF2 = 1
Write EPF3 = 1
Write EPF4 = 1
Write EPF5 = 1
Write EPF6 = 1
Write EPF7 = 1
Cleared when service complete
Cleared when service complete
Cleared when service complete
Cleared when service complete
0
IP
MOTOROLA