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HD64411 Q2
Hitachi HD64411 Q2 Manuals
Manuals and User Guides for Hitachi HD64411 Q2. We have
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Hitachi HD64411 Q2 manual available for free PDF download: User Manual
Hitachi HD64411 Q2 User Manual (228 pages)
Quick 2D Graphics Renderer
Brand:
Hitachi
| Category:
Video Card
| Size: 2.17 MB
Table of Contents
Table of Contents
4
Overview of Q2 (Quick 2D Graphics Renderer)
8
Q2 Overview
8
Block Diagram
9
Concepts
11
Simplicity (Optimization of System Configuration)
11
Realtime Operation
12
Upgradability
13
Summary of Functions
15
Section 2 Pins
18
Pin Arrangement and Functions
18
Overview of Pins
18
Pin Arrangement
19
Pin Functions
20
Operating Mode Pins
26
CPU Interface Pins
27
CPU Writes
27
CPU Reads
28
DMA Writes
28
Interrupts
28
Power Supply Pins
29
Normal Power Supply and PLL Power Supply
29
CPU Power Supply
29
Display Interface Pins
29
DAC Interface
29
Video Encoder Interface
30
CRT Interface
30
UGM Interface Pins
30
UGM Access
30
Unified Graphics Memory (UGM) Display Functions
32
Clocks
32
UGM (Unified Graphics Memory) Control
33
Overview
33
Memory Access
34
Memory Map
35
Display and Display Control
42
Overview
42
Double-Buffering Control
42
Color Data Formats
47
Display Functions
53
Initial States
63
Reset State (When RESET Is Driven Low)
63
Display List
66
Overview
66
Command Fetching
69
Basic Functions
70
Rendering Coordinate Systems
70
Rendering Reference Data
74
Rendering Attributes
77
Drawing Commands
82
Polygon4A
82
Polygon4B
85
Polygon4C
88
Ftrap
90
Rftrap
92
Linew
94
Rlinew
96
Line
98
Rline
100
4 . 4 . 1 0 Pline
102
4 . 4 . 1 1 Rpline
105
4 . 4 . 1 2 Move
107
4 . 4 . 1 3 Rmove
109
4 . 4 . 1 4 Lcofs
111
4 . 4 . 1 5 Rlcofs
113
4 . 4 . 1 6 Uclip
115
4 . 4 . 1 7 Sclip
117
4 . 4 . 1 8 Clrw
119
4 . 4 . 1 9 Jump
121
4 . 4 . 2 0 Gosub
123
4 . 4 . 2 1 Ret
125
4 . 4 . 2 2 Trap
126
4 . 4 . 2 3 Nop3
128
Registers
130
Overview
130
Register Updating
131
Interface Control Registers
134
System Control Register (SYSR)
134
Status Register (SR)
138
Status Register Clear Register (SRCR)
141
Interrupt Enable Register (IER)
142
Memory Mode Register (MEMR)
144
Display Mode Register (DSMR)
145
Rendering Mode Register (REMR)
149
Input Data Conversion Mode Register (IEMR)
151
Memory Control Registers
152
Display Size Registers X and y (DSRX, DSRY)
152
Display Start Address Registers 0 and 1 (DSAR0, DSAR1)
153
Display List Start Address Registers H and L (DLSARH, DLSARL)
154
Multi-Valued Source Area Start Address Register (SSAR)
154
Work Area Start Address Register (WSAR)
155
DMA Transfer Start Address Registers H and L (DMASRH, DMASRL)
155
DMA Transfer Word Count Register (DWAWR)
156
Display Control Registers
157
Display Window Registers (DSWR (HDS/HDE/VDS/VDE))
157
Horizontal Sync Pulse Width Register (HSWR)
158
Horizontal Scan Cycle Register (HCR)
158
Vertical Start Position Register (VSPR)
159
Vertical Scan Cycle Register (VCR)
159
Display off Output Registers H and L (DOORH, DOORL)
160
Color Detection Registers H and L (CDERH, CDERL)
161
Rendering Control Registers
162
Command Status Registers H and L (CSTRH, CSTRL)
162
Input Control Registers
163
Image Data Transfer Start Address Registers H and L (ISARH, ISARL)
163
Image Data Size Registers X and y (IDSRX, IDSRY)
164
Image Data Entry Register (IDER)
164
Color Palette
165
Color Palette Registers H, L000-255 (CP000RH, L-CP255H, L)
165
Section 6 Usage Notes
168
CPU Clock and Q2-CLK0
168
Horizontal Display Start Position Register Value
169
Notes on Data Transfer in YUV Mode
171
Software Reset Bit
171
Note on Use of Auto Display Change Mode
172
Note on Color Palette Register Writes During Display
172
Notes on DMA Mode
173
Power-On Sequence
174
Q2 Internal Buffers
175
Notes on Transition to Display off Mode
177
Note on Changing TV Synchronization Mode
177
Note on POLYGON4A Source Reference Location
178
Section 7 Electrical Characteristics
180
Absolute Maximum Ratings
180
Recommended Operating Conditions
181
Electrical Characteristics Test Methods
182
Timing Testing
182
Test Load Circuit (All Output and Input/Output Pins)
183
Electrical Characteristics
184
DC Characteristics
184
AC Characteristics
185
Timing Charts
195
Input Clocks
195
Reset Timing
197
CPU Read Cycle Timing
198
CPU Write Cycle Timing
199
DMA Write Cycle Timing (DMAC → Q2)
200
Interrupt Output Timing
202
UGM Read Cycle Timing
203
UGM Write Cycle Timing
205
UGM Refresh Cycle Timing
207
7 . 5 . 1 0 Master Mode Display Timing
208
TV Sync Mode Display Timing
209
Appendix A Registers
214
Appendix B Drawing Commands and Parameters
216
Relationship between Drawing Commands and Rendering Attributes
216
Drawing Command Codes
217
Drawing Command Parameter Specifications
218
Appendix C Drawing Algorithms
225
Appendix D Package Dimensions
228
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