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HD6433288F
Hitachi HD6433288F Microcomputer Manuals
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Hitachi HD6433288F Microcomputer manual available for free PDF download: Hardware Manual
Hitachi HD6433288F Hardware Manual (328 pages)
SINGLE-CHIP MICROCOMPUTER
Brand:
Hitachi
| Category:
Computer Hardware
| Size: 1.46 MB
Table of Contents
Table of Contents
3
Section 1. Overview
10
Overview
10
Block Diagram
14
Pin Assignments and Functions
15
Pin Arrangement
15
Pin Functions
18
Section 2. MCU Operating Modes and Address Space
24
Overview
24
Mode Selection
24
Mode and System Control Registers (MDCR and SYSCR)
25
System Control Register (SYSCR)-H'FFC4
25
Mode Control Register (MDCR)-H'FFC5
27
Address Space Maps
28
Section 3. CPU
32
Overview
32
Features
32
Register Configuration
33
General Registers
33
Control Registers
34
Initial Register Values
35
Addressing Modes
36
Addressing Mode
36
How to Calculate Where the Execution Starts
38
Data Formats
42
Data Formats in General Registers
43
Memory Data Formats
44
Instruction Set
45
Data Transfer Instructions
47
Arithmetic Operations
49
Logic Operations
50
Shift Operations
50
Bit Manipulations
52
Branching Instructions
56
System Control Instructions
58
Block Data Transfer Instruction
59
CPU States
60
Program Execution State
61
Exception-Handling State
61
Power-Down State
62
Access Timing and Bus Cycle
62
Access to On-Chip Memory (RAM and ROM)
62
Access to On-Chip Register Field and External Devices
64
Section 4. Exception Handling
68
Overview
68
Reset
68
Reset Sequence
68
Disabling of Interrupts after Reset
71
Interrupts
71
Overview
71
Interrupt-Related Registers
73
External Interrupts
75
Internal Interrupts
76
Interrupt Handling
76
Interrupt Response Time
81
Precaution
81
Note on Stack Handling
82
Section 5. I/O Ports
84
Overview
84
Port 1
86
Port 2
89
Port 3
93
Port 4
97
Port 5
105
Port 6
109
Port 7
120
Section 6. 16-Bit Free-Running Timer
122
Overview
122
Features
122
Block Diagram
123
Input and Output Pins
124
Register Configuration
124
Register Descriptions
125
Free-Running Counter (FRC)-H'FF92
125
Output Compare Registers a and B (OCRA and OCRB)-H'FF94
126
Input Capture Registers a to D (ICRA to ICRD)-H'FF98, H'FF9A, H'FF9C, H'FF9E
126
Timer Interrupt Enable Register (TIER)-H'FF90
129
Timer Control/Status Register (TCSR)-H'FF91
131
Timer Control Register (TCR)-H'FF96
134
Timer Output Compare Control Register (TOCR)-H'FF97
136
CPU Interface
137
Operation
139
FRC Incrementation Timing
139
Output Compare Timing
141
Input Capture Timing
142
Setting of FRC Overflow Flag (OVF)
145
Interrupts
146
Sample Application
146
Application Notes
147
Section 7. 8-Bit Timers
152
Overview
152
Features
152
Block Diagram
152
Input and Output Pins
153
Register Configuration
154
Register Descriptions
154
Timer Counter (TCNT)-H'FFCC (TMR0), H'FFD4 (TMR1)
154
Time Constant Registers a and B (TCORA and TCORB)- H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1)
155
Timer Control Register (TCR)-H'FFC8 (TMR0), H'FFD0 (TMR1)
155
Timer Control/Status Register (TCSR)-H'FFC9 (TMR0), H'FFD1 (TMR1)
158
Serial/Timer Control Register (STCR)-H'FFC3
160
Operation
161
TCNT Incrementation Timing
161
Compare Match Timing
162
External Reset of TCNT
164
Setting of TCSR Overflow Flag (OVF)
165
Interrupts
166
Sample Application
166
Application Notes
167
Section 8. Serial Communication Interface
172
Overview
172
Features
172
Block Diagram
173
Input and Output Pins
174
Register Configuration
174
Register Descriptions
175
Receive Shift Register (RSR)
175
Receive Data Register (RDR)-H'FFDD
175
Transmit Shift Register (TSR)
175
Transmit Data Register (TDR)-H'FFDB
176
Serial Mode Register (SMR)-H'FFD8
176
Serial Control Register (SCR)-H'FFDA
179
Serial Status Register (SSR)-H'FFDC
183
Bit Rate Register (BRR)-H'FFD9
186
Serial/Timer Control Register (STCR)-H'FFC3
190
Operation
191
Overview
191
Asynchronous Mode
193
Clocked Synchronous Operation
206
SCI Interrupts
215
Application Notes
215
Section 9. A/D Converter
218
Overview
218
Features
218
Block Diagram
219
Input Pins
220
Register Configuration
220
Register Descriptions
221
A/D Data Registers (ADDR)-H'FFE0 to H'FFE6
221
A/D Control/Status Register (ADCSR)-H'FFE8
221
A/D Control Register (ADCR)-H'FFEA
224
Operation
225
Single Mode (SCAN = 0)
225
Scan Mode (SCAN = 1)
228
Input Sampling Time and A/D Conversion Time
231
External Trigger Input Timing
232
Interrupts
233
Section 10. RAM
234
Overview
234
Block Diagram
234
RAM Enable Bit (RAME) in System Control Register (SYSCR)
234
Operation
235
Expanded Modes (Modes 1 and 2)
235
Single-Chip Mode (Mode 3)
235
Section 11. ROM
236
Overview
236
Block Diagram
237
PROM Mode (H8/329, H8/327)
237
PROM Mode Setup
237
Socket Adapter Pin Assignments and Memory Map
238
Programming
241
Writing and Verifying
241
Notes on Writing
245
Reliability of Written Data
245
Erasing of Data
246
Handling of Windowed Packages
247
Section 12. Power-Down State
248
Overview
248
System Control Register: Power-Down Control Bits
249
Sleep Mode
251
Transition to Sleep Mode
251
Exit from Sleep Mode
251
Software Standby Mode
251
Transition to Software Standby Mode
252
Exit from Software Standby Mode
252
Sample Application of Software Standby Mode
252
Application Note
253
Hardware Standby Mode
254
Transition to Hardware Standby Mode
254
Recovery from Hardware Standby Mode
254
Timing Relationships
255
Section 13. Clock Pulse Generator
256
Overview
256
Block Diagram
256
Oscillator Circuit
256
System Clock Divider
259
Section 14. Electrical Specifications
260
Absolute Maximum Ratings
260
Electrical Characteristics
260
DC Characteristics
260
AC Characteristics
266
A/D Converter Characteristics
270
MCU Operational Timing
271
Bus Timing
271
Control Signal Timing
272
16-Bit Free-Running Timer Timing
275
8-Bit Timer Timing
276
Serial Communication Interface Timing
277
I/O Port Timing
278
Appendices
280
Appendix A. CPU Instruction Set
280
Instruction Set List
280
Operation Code Map
287
Number of States Required for Execution
289
Appendix B. Register Field
295
Register Addresses and Bit Names
295
Register Descriptions
299
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