Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Manuals

Manuals and User Guides for Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03. We have 1 Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 manual available for free PDF download: Technical Manual

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual (631 pages)

CMOS 32-Bit Single Chip Microcomputer

Brand: Epson | Category: Computer Hardware | Size: 3.64 MB

Table of Contents

Table of Contents
5
S1C33L03 Product Part
15
Outline

17
- Features
  17
- Block Diagram
  19
- Pin Description
  20
  - Pin Layout Diagram (Plastic Package
    20
  - Pin Functions
    21
Power Supply

28
- Power Supply Pins
  28
- Operating Voltage
  28
  - DD Ss
    28
  - Dde
    28
- Power Supply for Analog Circuits (AV DDE
  29
Internal Memory

30
- ROM and Boot Address
  30
- Ram
  31
Peripheral Circuits

32
- List of Peripheral Circuits
  32
- I/O Memory Map
  33
Power-Down Control

81
Basic External Wiring Diagram

84
Precautions on Mounting

85
Electrical Characteristics

87
- Absolute Maximum Rating
  87
- Recommended Operating Conditions
  88
- DC Characteristics
  89
- Current Consumption
  91
- A/D Converter Characteristics
  92
- AC Characteristics
  94
- Oscillation Characteristics
  123
- PLL Characteristics
  124
Package

125
- Plastic Package
  125
Pad Layout

126
- Pad Layout Diagram
  126
- Pad Coordinate
  127
Appendix A <Reference> External Device Interface Timings

129
- DRAM (70Ns
  130
- DRAM (60Ns
  133
- ROM and Burst ROM
  137
- SRAM (55Ns
  139
- SRAM (70Ns
  141
- 8255A
  143
Appendix B Pin Characteristics

144
Ioutline

149
Introduction

151
Block Diagram

153
List of Pins

155
- List of External I/O Pins
  155
- Core Block
  
  163
Introduction

165
Cpu and Operating Mode

167
- Cpu
  167
- Standby Mode
  168
  - HALT Mode
    168
  - SLEEP Mode
    168
  - Notes on Standby Mode
    169
  - Test Mode
    169
  - Debug Mode
    169
  - Trap Table
    170
Initial Reset

173
- Pins for Initial Reset
  173
- Cold Start and Hot Start
  173
- Power-On Reset
  174
- Reset Pulse
  174
- Boot Address
  175
- Notes Related to Initial Reset
  175
BCU (Bus Control Unit)

177
- Pin Assignment for External System Interface
  177
  - I/O Pin List
    177
  - Combination of System Bus Control Signals
    179
  - Memory Area
    180
    
    Memory Map
    180
    
    External Memory Map and Chip Enable
    181
    
    Using Internal Memory on External Memory Area
    183
    
    Exclusive Signals for Areas
    183
    
    Area 10
    184
    
    Area 3
    185
  - Setting External Bus Conditions
    186
    
    Setting Device Type and Size
    186
    
    Setting SRAM Timing Conditions
    187
    
    Bus Clock
    187
    
    Setting Timing Conditions of Burst ROM
    188
  - Bus Operation
    189
    
    Data Arrangement in Memory
    189
    
    Bus Operation of External Memory
    189
- Bus Clock
  193
  - Bus Speed Mode
    194
  - Bus Clock Output
    194
- Bus Cycles in External System Interface
  195
  - SRAM Read Cycles
    195
  - Bus Timing
    196
  - SRAM Write Cycles
    197
  - Burst ROM Read Cycles
    199
- DRAM Direct Interface
  200
  - Outline of DRAM Interface
    200
  - DRAM Setting Conditions
    201
  - DRAM Read/Write Cycles
    204
  - DRAM Refresh Cycles
    207
- Releasing External Bus
  208
- Power-Down Control by External Device
  209
- I/O Memory of BCU
  210
ITC (Interrupt Controller)

225
- Outline of Interrupt Functions
  225
  - Maskable Interrupts
    225
  - Interrupt Factors and Intelligent DMA
    227
  - Nonmaskable Interrupt (NMI)
    227
  - Interrupt Processing by the CPU
    227
  - Clearing Standby Mode by Interrupts
    227
- Trap Table
  228
- Control of Maskable Interrupts
  229
- IDMA Invocation
  233
- HSDMA Invocation
  235
- I/O Memory of Interrupt Controller
  236
- Programming Notes
  249
CLG (Clock Generator)

251
- Configuration of Clock Generator
  251
- I/O Pins of Clock Generator
  252
- High-Speed (OSC3) Oscillation Circuit
  252
- Pll
  253
- Controlling Oscillation
  253
- Setting and Switching over the CPU Operating Clock
  254
- Power-Control Register Protection Flag
  255
- Operation in Standby Mode
  255
- I/O Memory of Clock Generator
  256
- Programming Notes
  259
DBG (Debug Unit)

261
- Debug Circuit
  261
- I/O Pins of Debug Circuit
  261
- Peripheral Block
  
  263
Introduction

265
Prescaler

267
- Configuration of Prescaler
  267
- Source Clock
  267
- Selecting Division Ratio and Output Control for Prescaler
  268
- Source Clock Output to 8-Bit Programmable Timer
  268
- I/O Memory of Prescaler
  269
- Programming Notes
  274
8-Bit Programmable Timers

275
16-Bit Programmable Timers

293
Watchdog Timer

319
- Configuration of Watchdog Timer
  319
- Control of Watchdog Timer
  319
- Operation in Standby Modes
  320
- I/O Memory of Watchdog Timer
  321
- Programming Notes
  321
Low-Speed (Osc1) Oscillation Circuit

323
Clock Timer

331
- Configuration of Clock Timer
  331
- Control and Operation of the Clock Timer
  332
- Interrupt Function
  334
- Examples of Use of Clock Timer
  336
- I/O Memory of Clock Timer
  337
- Programming Notes
  342
Serial Interface

343
- Configuration of Serial Interfaces
  343
  - Features of Serial Interfaces
    343
  - I/O Pins of Serial Interface
    344
  - Setting Transfer Mode
    345
- Clock-Synchronized Interface
  346
- Asynchronous Interface
  354
- Irda Interface
  363
  - Outline of Irda Interface
    363
  - Setting Irda Interface
    363
  - Control and Operation of Irda Interface
    365
- Serial Interface Interrupts and DMA
  366
- I/O Memory of Serial Interface
  370
- Programming Notes
  388
Input/Output Ports

389
- Input Ports (K Ports)
  389
  - Structure of Input Port
    389
  - Input-Port Pins
    390
  - Notes on Use
    390
  - I/O Memory of Input Ports
    391
- I/O Ports (P Ports)
  392
  - Structure of I/O Port
    392
  - I/O Port Pins
    392
  - I/O Control Register and I/O Modes
    393
  - I/O Memory of I/O Ports
    394
- Input Interrupt
  400
  - Port Input Interrupt
    400
  - Key Input Interrupt
    402
  - Control Registers of the Interrupt Controller
    404
  - I/O Memory for Input Interrupts
    406
- Programming Notes
  413
Analog Block

415
Introduction

417
A/D Converter

419
- Features and Structure of A/D Converter
  419
- I/O Pins of A/D Converter
  420
- Setting A/D Converter
  421
- Control and Operation of A/D Conversion
  423
- A/D Converter Interrupt and DMA
  425
- I/O Memory of A/D Converter
  427
- Programming Notes
  433
Dma Block

435
Introduction

437
HSDMA (High-Speed DMA)

439
- Functional Outline of HSDMA
  439
- I/O Pins of HSDMA
  440
- Programming Control Information
  441
  - Setting the Registers in Dual-Address Mode
    441
  - Setting the Registers in Single-Address Mode
    444
- Enabling/Disabling DMA Transfer
  445
- Trigger Factor
  446
- Operation of HSDMA
  447
  - Operation in Dual-Address Mode
    447
  - Operation in Single-Address Mode
    450
  - Timing Chart
    451
- Interrupt Function of HSDMA
  453
- I/O Memory of HSDMA
  455
- Programming Notes
  474
IDMA (Intelligent DMA)

475
- Functional Outline of IDMA
  475
- Programming Control Information
  475
- IDMA Invocation
  479
- Operation of IDMA
  482
- Linking
  486
- Interrupt Function of Intelligent DMA
  487
- I/O Memory of Intelligent DMA
  488
- Programming Notes
  491
Sdram Controller Block

493
Introduction

495
Sdram Interface

497
- Outline of SDRAM Interface
  497
- SDRAM Controller Block Diagram
  497
- I/O Pins and Connection
  498
  - I/O Pins
    498
  - Connection Examples
    498
- SDRAM Controller Configuration
  501
  - Setting PLL
    501
  - BCU Configuration
    501
  - SDRAM Setting Conditions
    502
- SDRAM Operation
  508
  - Synchronous Clock
    508
  - Power-Up and Initialization
    509
  - SDRAM Commands
    510
  - Burst Read Cycle
    511
  - Single Read/Single Write
    512
  - Refresh Mode
    513
  - Power-Down Mode
    515
  - Bus Release Procedure
    515
- I/O Memory of SDRAM Interface
  517
- Programming Notes
  528
- Examples of SDRAM Controller Initialization Program
  529
Lcd Controller Block

531
Introduction

533
Lcd Controller

535
- Overview
  535
  - Features
    535
  - Block Diagram
    537
- I/O Pins of the LCD Controller
  538
- System Settings
  539
  - Setting the BCU
    539
  - Display Memory
    539
  - LCD Controller Setting Procedure
    540
  - Clock
    541
- Setting the LCD Panel
  542
  - Types of Panels
    542
  - Resolution
    542
  - Display Modes
    543
  - Look-Up Tables
    545
  - Frame Rates
    553
  - Other Settings
    554
- Display Control
  555
  - Controlling LCD Power Up/Down
    555
  - Reading/Writing Display Data
    556
  - Setting the Display Start Address
    556
  - Split-Screen Display
    557
  - Virtual Screen and View Port
    557
  - Inverting and Blanking the Display
    559
  - Portrait Mode
    559
  - Power Save
    563
  - Controlling the GPIO Pins
    564
- I/O Memory of LCD Controller
  565
- Programming Notes
  576
- Precautions on Using ICD33
  576
- Examples of LCD Controller Setting Program
  577
Appendix I/O Map

579

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