System Block Diagram; Overview; B (Standby) Bus; M (Main) Bus - Sony TVP-08 Training Manual

System Block Diagram

Overview

This section discusses the System Block for the RA-4 chassis and will
show the four different I²C busses. The B bus is active during standby.
The M bus is the main bus and controls most of the set. The P bus is part
of the auto-registration circuit and controls this circuit's functions. Finally,
the MID bus controls the MID functions such as PIP and Twin-View.
The diagram also shows two 3-line busses. IC1009 OSD CPU uses one
to communicate with IC1004 OSD Processor. The other bus is used by
IC1008 Main CPU to control IC2105 Dolby Processor.

B (Standby) Bus

The B bus is the only bus that is active in the standby mode. It will have
the same data on it as the M bus during regular set operation. There are
only three ICs on this bus. They are IC1008 Main CPU, IC1007 NVM and
IC1009 OSD CPU. In addition to these ICs, the factory test connector is
on this bus. This is so that data can be written right to the NVM during
production. It also allows for outside control of the set on the production
line. This connector would be the one that the Registration Jig for the
RA1 and RA2 chassis' would be connected. That jig is not usable on the
RA4 chassis due to the different convergence system.
Connector or IC
IC1008 Main CPU
IC1009 OSD CPU
IC1007 NVM

M (Main) Bus

The I²C bus controls most of the set. There is activity on it at all times
when the set is powered ON. Any IC on the bus could cause loading
problems. The following table shows which pins on each IC are on the
bus. If there is a loading problem, these pins can be lifted from the IC to
find the problem.
MSDA MSCL
48 50
50 48
6 5
37
Connector or IC
CN518 (BM)
CN521 (Bus Connector)
CN522 (BD)
IC511 Video Processor
IC515 AV Switch
IC1008 Main CPU
IC1301 Sub Chroma
IC1305 Main Chroma
IC1306 3D Comb
IC2302 L/R Tone Control
IC2303 C/S Tone Control
TU501 Main Tuner
TU502 Sub Tuner

P (Auto Registration) Bus

The P data bus handles the operation of the registration circuit. It oper-
ates independently of the M bus. There will always be activity on this bus
when the set is ON. This is because the IC1703 PJED CPU instructs
IC1707 Regi Correction to read data from IC1704 NVM to refresh its in-
ternal RAM. These commands are sent every vertical period and it takes
approximately 20+ vertical periods to refresh all the data. The reason we
refresh so often is due to registration malfunctions that occurred during
CRT arcing and ESD tests.

MID Bus

The MID bus is located on the BM board and controls the functions of the
MID circuit. Commands are sent from IC1008 Main CPU to IC009 MID
CPU, which commands IC010 MID Controller to carry out MID functions.
Data is only sent during MID operation.
MSDA MSCL
15 14
10 11
15 14
56 55
32 31
47 49
37 36
37 36
60 59
29 30
29 30
SDA SCL
SDA SCL