Chipset - Asus SynJ SB67118 User Manual

2.4.3

Chipset

Chipset Configuration
NorthBridge Configuration
Internal Graphics
NorthBridge Configuration
NorthBridge Chipset Configuration
Memory Configuration
ECC Configuration
Memory CLK
CAS Latency(Tc1)
RAS/CAS Delay(Trcd)
Row Precharge Time(Trp)
Min Active RAS(Tras)
RAS/RAS Delay(Trrd)
Row Cycle(Trc)
Memory Configuration
Advanced
Memory Configuration
Bank Interleaving
Channel Interleaving
MemClk Tristate C3/ATLVID
Memory Hole Remapping
DCT Unganged Mode
Power Down Enable
2-24
:333MHz
:5.0
:5 CLK
:5 CLK
:15 CLK
:3 CLK
:21 CLK
[Auto]
[Disabled]
[Disabled]
[Enabled]
[Auto]
[Enabled]
Memory Options &
Information
Enable Bank Memory
Interleaving
Chapter 2: BIOS setup