Diagrams; Explanation Of Ic Terminals - Sony ZS-D50 Service Manual

Personal audio system
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Adjustment Location :
[TUNER BOARD] (SIDE A)
L2 : FM Frequency
Coverage Adjustment
L4 : AM Frequency
Coverage Adjustment
L3 : AM Tracking Adjustment
– 17 –

6-1. EXPLANATION OF IC TERMINALS

IC801 CXP83232A-010Q (SYSTEM CONTROL) CD/SYSTEM BOARD
Pin No.
Pin name
1
C-SOR
2
NC
3
RMC
CFT1 : AM IF Adjustment
4
R-MUTE
5
C-XRST
6
REG-CHK
7
C-SENSE 2
8
C-CLK
L1 : FM Tracking Adjustment
9
C-DATA
10
C-SENSE 1
CT1 : FM Tracking Adjustment
11
C-SQCK
12
C-SQSO
13
C-MUTE
14
NC
CT3 : AM Tracking Adjustment
15
R-DATA
16
R-CLK
17
R-CE
18
R-COUNT
19
P-CONT
20
PL-CONT
––––––––––––––––––––––––
21
HALF (M/D)
––––––––––––––––––––––––––
22
T-HEAD POS
23
REC
24
PROOF (A)
25
PROOF (B)
26
AMS/INIT
27
R-SHIFT
28
INPUT 1
29
INPUT 2
30
CD-OP/CL
31
KEY 1
32
KEY 2
33
KEY 3
34
KEY 4
35
KEY 5
36
MO9V-CHK
37
MODEL ID
–––––––––––––––
38
RESET
39
OSC-OUT
40
OSC-IN
41
GND
42
NC
43
NC
44
V REF
45
GND
SECTION 6

DIAGRAMS

I/O
Description
I
CD DSP command data input.
Not used ("L" level).
I
Remote control signal input.
O
Tuner mute signal output.
O
CD system reset output.
I
Regulator voltage check input.
I
CD-SENSE input.
O
CD DSP command clock output.
O
CD DSP command data output.
I
CD SENSE input.
O
CD SUB-Q read out clock output.
I
CD-SQSO data input.
O
Mute signal output for DSP (IC702).
Not used (OPEN).
O
PLL IC data output.
O
PLL IC clock output.
O
PLL IC chip enable output.
I
PLL IC data input.
O
POWER ON/OFF control output.
O
Plunger ON/OFF control output.
I
Cassette half detect input.
I
Head position detect input.
O
REC bias ON/OFF control output.
I
Half pawl input at A-side.
I
Half pawl input at B-side.
I
TC AMS signal input/Initial terminal.
O
System clock shift output.
O
Loading motor control output.
O
Loading motor control output.
I
CD tray open/close detect input.
I
Key input terminal.
I
Key input terminal.
I
Key input terminal.
I
Key input terminal.
I
Key input terminal.
I
Motor power supply voltage check.
I
Model destination setting input.
I
System Reset terminal.
O
System clock oscillator output (4.21MHz).
I
System clock oscillator input (4.21MHz).
Ground terminal.
Not used (OPEN).
Not used (Ground).
I
Reference voltage input.
Ground terminal.
– 18 –
Pin No.
Pin name
I/O
Description
46
VDDL
O
LCD drive bias control output.
47
VDD3
O
LCD drive bias power supply.
48
VDD2
O
LCD drive bias power supply.
49
VDD1
O
LCD drive bias power supply.
50
COM0
O
LCD common output.
51
COM1
O
LCD common output.
52
COM2
O
LCD common output.
53
COM3
O
LCD common output.
54 – 79
SEG0–SEG25
O
LCD segment output.
80
NC
Not used (OPEN).
81
NC
Not used (OPEN).
82
NC
Not used (OPEN).
–––––––––––––––––––––
83
B/L-CONT
O
Back-light ON/OFF control output.
84
LINE
O
Function output for LINE.
85
TAPE
O
Function output for TAPE
–––––––––––––––
86
RADIO
O
Function output for RADIO
87
T-MOTOR-CONT
O
Motor control signal output.
88
X-LAT
O
CD DSP command lach output.
89
VDD
Power supply.
90
NC
Not used (connect to VDD).
91
GND
Ground.
92
CLK OUT
O
Sub system clock oscillator (32.768kHz).
93
CLK IN
I
Sub system clock oscillator (32.768kHz).
94
CD
O
Function output for CD.
95
A-MUTE
O
Audio mute signal output.
96
VR-DATA
O
Volume clock output.
97
VR-CLK
O
Volume clock output.
98
VR-CE
O
Volume enable output.
99
WP
I
Wake-up signal input.
100
TAPE END
I
Tape end detect input.
– 19 –

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