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FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
erial Input
Dual S
PLL Frequency
MB15F74UV
DESCRIPTION
The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and
a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the
2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range
is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial date. The serial data format is the same as MB15F74UL. Fast locking is achieved for adopting
the new circuit.
MB15F74UV is in the small package (BCC18) which decreases a mount area of MB15F74UV about 50
paring with the former BCC20 (for dual PLL) .
FEATURES
• High frequency operation
• Low power supply voltage
• Ultra low power supply current : I
PACKAGE
Synthesizer
: RF synthesizer : 4000 MHz Max
: IF synthesizer : 2000 MHz Max
: V
2.7 V to 3.6 V
CC
9.0 mA Typ
CC
(V
3.0 V, Ta
25 C, SW
CC
18-pin plastic BCC
(LCC-18P-M05)
DS04-21381-1E
SW
0 in IF/RF locking state)
IF
RF
com-
(Continued)
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Related Manuals for Fujitsu MB15F74UV
Summary of Contents for Fujitsu MB15F74UV
- Page 1 DESCRIPTION The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the 2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
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Page 2: Pin Assignments
MB15F74UV (Continued) • Direct power saving function : Power supply current in power saving mode • Software selectable charge pump current : 1.5 mA/6.0 mA Typ • Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65) •... -
Page 3: Pin Description
One bit data is shifted into the shift register on a rising edge of the clock. The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor. MB15F74UV Descriptions “L” ; Power saving mode “L” ; outputs LD signal... -
Page 4: Block Diagram
MB15F74UV BLOCK DIAGRAM Intermittent mode control (IF-PLL) Prescaler (IF-PLL) (32/33, 64/65) Xfin (18) Prescaler (14) (RF-PLL) Xfin (64/65, 128/129) Intermittent mode control (RF-PLL) Schmitt (15) trigger Latch selector circuit Schmitt trigger Data (16) circuit 23-bit shift register Schmitt Clock (17) -
Page 5: Absolute Maximum Ratings
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Rating Symbol... -
Page 6: Electrical Characteristics
MB15F74UV ELECTRICAL CHARACTERISTICS Parameter Symbol Power supply current Power saving current Operating frequency Input sensitivity Input available voltage OSC “H” level input voltage Data Clock “L” level input voltage “H” level input voltage PS “L” level input voltage Data “H” level input current Clock “L”... - Page 7 C) | |I C) | 2] 100 ( ) (Applied to both I –40 “0” , T1 “0” and T2 Charge pump output voltage (V) MB15F74UV 2.7 V to 3.6 V, Ta 40 C to 85 C) Value Unit and l and I “1”.
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Page 8: Functional Description
MB15F74UV FUNCTIONAL DESCRIPTION 1. Pulse swallow function [ (P : Output frequency of external voltage controlled oscillator (VCO) : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL) : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) - Page 9 • Divide ratio Data Flow 9 10 11 12 13 14 15 16 17 18 19 20 21 22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 MB15F74UV (MSB) , RF : SW , RF : FC...
- Page 10 MB15F74UV Prescaler Data Setting • Divide ratio Prescaler divide ratio IF-PLL Prescaler divide ratio RF-PLL • Charge Pump Current Setting Current value 6.0 mA 1.5 mA fout output Selectable Bit Setting • LD/fout pin state LD output fout output Phase Comparator Phase Switching Data Setting •...
- Page 11 (2) Set serial data at least 1 s after the power supply becomes stable (V (3) Release power saving mode (PS , PS : “L” “H”) at least 100 ns later after setting serial data. MB15F74UV 100 ns 2.2 V) .
- Page 12 MB15F74UV 4. Serial Data Data Input Timing Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal.
- Page 13 Locking state/Power saving state Unlocking state Locking state/Power saving state Unlocking state 2 to 2 or more. or less and continues to be so for three cycles or more. input frequency as follows. 12.8 MHz 12.8 MHz MB15F74UV LD output...
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Page 14: Test Circuit
MB15F74UV TEST CIRCUIT (for Measuring Input Sensitivity fin/OSC S.G. S.G. 1000 pF 1000 pF CCIF 0.1 F S.G. 1000 pF Controller (divide ratio setting) Clock Data Xfin MB15F74UV CCIF fout 1000 pF CCRF 0.1 F 1000 pF Xfin CCRF Oscilloscope... -
Page 15: Typical Characteristics
2500 Catalog guaranteed range 3000 3500 4000 [MHz] IF-PLL input sensitivity vs. Input frequency 1000 1500 2000 [MHz] MB15F74UV Ta = +25 C 2.7 V 3.0 V 3.6 V SPEC 4500 5000 Ta = +25 C 2.7 V 3.0 V 3.6 V... - Page 16 MB15F74UV input sensitivity Catalog guaranteed range Input sensitivity vs. Input frequency Input frequency f (MHz) 2.7 V 3.0 V 3.6 V SPEC...
- Page 17 0.00 0.50 1.00 1.50 2.00 2.50 • 6.0 mA mode 8.00 6.00 4.00 2.00 0.00 2.00 4.00 6.00 8.00 2.7 V, Ta +25 C Charge pump output voltage V 2.7 V, Ta +25 C Charge pump output voltage V MB15F74UV...
- Page 18 MB15F74UV fin input impedance START 100.000 000 MHz START 2 000.000 000 MHz input impedance 4 30.266 102.92 2 000.000 000 MHz STOP 2 000.000 000 MHz input impedance 4 20.93 39.352 4 000.000 000 MHz STOP 4 000.000 000 MHz 773.21 fF...
- Page 19 5. OSC input impedance START 3.000 000 MHz input impedance 4 278.69 1.0537 k 40.000 000 MHz STOP 40.000 000 MHz MB15F74UV 3.7761 pF 2.25 k 2.2373 k 10 MHz 881.62 1.8299 k 20 MHz 448.75 1.353 k 30 MHz...
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Page 20: Reference Information
MB15F74UV REFERENCE INFORMATION for Lock up Time Phase Noise and Reference Leakage Test Circuit S.G. Spectrum Analyzer • PLL Reference Leakage ATTEN 10 dB RL 0 dBm 50.0 kHz CENTER 2.1136000 GHz RBW 1.0 kHz • PLL Phase Noise VAVG 16 MKR 80.83 dB... - Page 21 50.0009 MHz -500 s 2.000 ms 500 s/div PLL Lock Up time 2173.6 MHz 2113.6 MHz within 1 kHz H ch L ch 1.56 ms y: 50.0013 MHz -500 s 2.000 ms 500 s/div MB15F74UV 1 kHz 4.500 ms 4.500 ms...
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Page 22: Application Example
MB15F74UV APPLICATION EXAMPLE 1000 pF TCXO OUTPUT 1000 pF Xfin 1000 pF CCIF CCIF 0.1 F Note : Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up registor to prevent oscillation when open-circuit in the input) . -
Page 23: Usage Precautions
Turn off power before inserting or removing this device into or from a socket. Protect leads with conductive sheet, when transporting a board mounted device ORDERING INFORMATION Part number MB15F74UVPVB CCRF Package 18-pin plastic BCC (LCC-18P-M05) MB15F74UV and V to keep them CCIF Remarks... -
Page 24: Package Dimension
MB15F74UV PACKAGE DIMENSION 18-pin plastic BCC (LCC-18P-M05) 2.70±0.10 (.106±.004) INDEX AREA 0.05(.002) 2003 FUJITSU LIMITED C18058S-c-1-1 0.45±0.05 (.018±.002) (Mount height) 2.01(.079) 2.40±0.10 (.094±.004) 0.45(.018) TYP. 0.075±0.025 (.003±.001) (Stand off) Details of "A" part Details of "B" part 0.14(.006) 0.25±0.06 C0.10(.004) (.010±.002) - Page 25 Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information.