HP P Class 450/500/550/600/650/700/750 Supplementary Manual page 3

VISUALIZE Graphics Architecture
HP's VISUALIZE graphics accelerators are designed with a scalable architecture that allows us to build a compatible
family of products from the same building blocks. The result is a range of price and performance points that can
address a range of customer needs. Note that there are 2 geometry pipelines per geometry chip, e.g., the
VISUALIZE-fx6+ has 3 geometry chips, or 6 geometry pipelines.
The heart of the geometry engine is based on customized silicon, using floating point technology leveraged from HP's
PA-RISC, long a leader in floating point performance.
(6) Geometry
Engines
AGP
Host
Interface
New DMA
Support
Figure 1. Block diagram of the VISUALIZE-fx6+.
If an application certifies the fx6+ graphics, it is guaranteed to work with the fx4+ and fx2+. The family is supported by
the same set of drivers. (For NT4.0, use the version 1.10 driver or later). The driver detects the configuration at
03/12/99
Table 1. The VISUALIZE-fx+ Graphics Family
Geometry Pipelines
Host Interface Chip
Rasterization Chips
RamDac Chip
Frame buffer memory
Texture Accelerators
Chips (Optional)
Texture memory
(Optional)
HP VISUALIZE fx6+
HP Visualize
Geometry
Engines
6.6 Mtri/s
Dual
Texture Engines
Optional Texture Acceleration Module
fx6+
6
1
2
1
18MB 18MB
2
32MB 16MB
Frame Buffer
18 MB SGRAM
HP Visualize
Raster
Engines
800 Mpix/s
HP Visualize
Texture
Engine
140 Mtex/s
fx4+ fx2+
4 2
1 1
2 2
1 1
18MB
1 1
16MB
RAMDAC
Texture Memory
32MB SDRAM
HP 2